CN1941629B - Apparatus and method for controlling on die termination - Google Patents
Apparatus and method for controlling on die termination Download PDFInfo
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Abstract
The present invention provides an apparatus for controlling an on die termination (ODT), which includes a counting unit for receiving an external clock signal and a delay locked loop (DLL) clock signal, and counting the toggle number of each of external clock signal and the DLL clock signal from a preset number; a comparing control unit for comparing the counted toggle number of the external clock signal with that of the DLL clock signal in response to an ODT command signal, and outputting an ODT signal for controlling the ODT based on the compared result.
Description
Technical field
The invention relates to the built-in terminal resistance of a kind of control crystal grain (On Die Termination, ODT) device and method, and more particular words it, the invention relates to a kind of ODT control device that is used to reduce the clock zone difference between delay-locked loop (DLL) clock and the internal clocking.
Background technology
Comprise that various semiconductor devices with the integrated circuit (IC) of a plurality of CPU (CPU), semiconductor memory devices and gate array construction are combined in the electric product such as personal computer, server and work station.Most of semiconductor devices comprise the receiver that is used for receiving via input pad external input signal, and are used for via the output pad to the transmitter of outside output internal signal.
Along with the running speed of electric product increases, between semiconductor device, become narrower to minimize transmission signals required time of delay as the hunting range of the signal of interface.Along with the hunting range of signal becomes narrower, the influence of external noise increases.Therefore, the signal reflex owing to the impedance mismatching of Interface Terminal is a key point.Generally speaking, impedance mismatching is changed by external noise, mains voltage variations, operational temperature variation and manufacture process and takes place.
When impedance mismatching takes place when, but the very difficult data distortion that transmits data and export with two-forty from the Interface Terminal of semiconductor device.If the impedance of terminating resistor is not suitably mated, then the signal that is transmitted can be reflected, and then causes the signal bust this.
The external stability resistor changes owing to aging, the operational temperature of integrated circuit and manufacture process changes the difficulty that has impedance matching.Therefore, when semiconductor device receives distorted signal, the frequent wrongheaded problem that takes place such as installation/maintenance failure and incoming level.
Recently, the technology that is used for regulating the impedance of terminating resistor developed that the transistorized number of connection with a plurality of transistors of being connected in parallel by control obtains and the external reference impedance phase with impedance.
Therefore, come the semiconductor device of the high running speed of construction needs with the impedance matching circuit that is called as brilliant mounted terminal resistance (on-chip termination) or the built-in terminal resistance of crystal grain (ODT).
Hereinafter, describe the problem of known ODT control method in detail referring to Figure 1A and Figure 1B.
Figure 1A is the oscillogram that is illustrated in the built-in terminal resistance of known crystal grain (ODT) control method under the low frequency running, and Figure 1B is the oscillogram that is illustrated in the built-in terminal resistance of known crystal grain (ODT) control method under the high-frequency running.
At first, after activating ODT command signal ODT_CMD, activate delay-locked loop (DLL) clock signal DLL_CLK in response to first rising edge (T0) of external timing signal EXT_CLK, and activate ODT enable signal ODTEN in response to dll clock signal DLL_CLK.
Then, ODT circuit running under the control of the ODT signal ODT that activates in response to second rising edge (T1) of external timing signal EXT_CLK.
At this moment, need the scheduled time " time of delay of DLL to ODT ", it is for operating the delay of ODT circuit substantially after activating ODT enable signal ODTEN.No matter the frequency change of external timing signal EXT_CLK, the scheduled time " time of delay of DLL to ODT " is fixing.
As shown in Figure 1A, when external timing signal EXT_CLK operates under the low frequency running, the clock cycle of external timing signal EXT_CLK, (meaning promptly, from T0 to T1) longer than the scheduled time " time of delay of DLL to ODT ". therefore, externally normal operation ODT circuit is located in second rising edge (T1) of clock signal EXT_CLK.
On the other hand, as shown in Figure 1B, when external timing signal EXT_CLK operated under the high-frequency running, the clock cycle of external timing signal EXT_CLK (anticipating promptly, from T0 to T1) was shorter than the scheduled time " time of delay of DLL to ODT ".Therefore, the ODT circuit is externally located (meaning is promptly located later at T2 or T2) but not is located running at second rising edge (T1) in the 3rd or the 3rd later rising edge of clock signal EXT_CLK.That is, the ODT circuit can be later than want regularly and operate.
Summary of the invention
Therefore, a target of the present invention provides the method for built-in terminal resistance of a kind of control crystal grain (ODT) and control circuit, and this method can operate with will regularly carry out ODT by the clock zone difference that reduces between delay-locked loop (DLL) clock and the internal clocking regardless of the operation frequency of ODT circuit.
According to an aspect of the present invention, a kind of device that is used to control the built-in terminal resistance of crystal grain (ODT) is provided, it comprises: counting unit, it is used to receive external timing signal and delay-locked loop (DLL) clock signal, and from each bifurcation shot number (toggle number) of default value counting external timing signal and dll clock signal; Control unit relatively, it is used for the command signal in response to ODT, and relatively the bifurcation shot number of being counted of external timing signal and the bifurcation shot number of being counted of dll clock signal, and result and export the ODT enable signal that is used to control ODT based on the comparison; With reset the signal generation unit, it is used for reseting signal in response to the outside, and this bifurcation shot number of output initialization this delay-locked loop clock signal first reset signal, and export at the fixed time this external timing signal of initialization this bifurcation shot number second reset signal.
According to a further aspect in the invention, provide the method for the built-in terminal resistance of a kind of control crystal grain (ODT), it comprises: reset step, it is reseted signal in response to the outside and activates first and reset signal, and activates second at the fixed time and reset signal; The dll clock counting step, it resets signal in response to first and from the bifurcation shot number of default value counting dll clock signal, and the bifurcation shot number that output is counted is as the DLL sign indicating number; The external clock counting step, it resets signal in response to second and from the bifurcation shot number of default value counting external timing signal, and the bifurcation shot number that output is counted is as foreign key; And comparison step, it determines the logic level of ODT enable signal in response to the ODT command signal by comparing foreign key and DLL sign indicating number, to produce the ODT enable signal, the logic level of this ODT enable signal is based on comparative result and determines.
Description of drawings
From below in conjunction with the accompanying drawing description of preferred embodiments, above-mentioned and other purposes of the present invention and feature will become clear, in the accompanying drawings:
Figure 1A is the oscillogram that is illustrated in the built-in terminal resistance of known crystal grain (ODT) control method under the low frequency running;
Figure 1B is the oscillogram that is illustrated in the known ODT control method under the high-frequency running;
Fig. 2 is the calcspar of ODT control circuit according to an embodiment of the invention;
Fig. 3 is the circuit diagram of reseting the signal generation unit of the ODT control circuit shown in Fig. 2;
Fig. 4 is the circuit diagram of the command signal detecting unit of the comparison control unit shown in Fig. 2;
Fig. 5 is the circuit diagram of the sign indicating number comparing unit of the comparison control unit shown in Fig. 2;
Fig. 6 is the circuit diagram of the enable signal generation unit of the comparison control unit shown in Fig. 2; And
Fig. 7 is for showing the oscillogram according to ODT control method of the present invention.
Description of reference numerals
1000 computing units
1200 external clock counters
1400 dll clock counters
2000 reset the signal generation unit
2200 DLL reset the signal generation unit
2400 postpone the duplicate model unit
The signal generation unit is reseted in 2600 outsides
3000 compare control unit
3200 command signal detecting units
3220 rising edge detecting units
3,222 first delay cells
3240 drop edge detecting units
3,242 second delay cells
3400 yards comparing units
3,420 first comparing units
3,422 first memory cell
3,424 first logical blocks
3,440 second comparing units
3,442 second memory cell
3,444 second logical blocks
3600 enable signal generation units
3620 lock units
3640 rising driver elements
3660 decline driver elements
3680 latch units
INV1 first inverter.
INV2 second inverter
INV3 the 3rd inverter
INV4 the 4th inverter
INV5 the 5th inverter
The INV6 hex inverter
INV7 the 7th inverter
INV8 the 8th inverter
NAND1 first and non-(NAND) door
NAND2 the 2nd NAND door
NAND3 the 3rd NAND door
NAND4 the 4th NAND door
NM1 first nmos pass transistor
NM2 second nmos pass transistor
The NODE1 first node
The NODE2 Section Point
NODE3 the 3rd node
PM1 the one PMOS transistor
PM2 the 2nd PMOS transistor
Embodiment
Hereinafter, will describe a kind of method in detail referring to accompanying drawing according to built-in terminal resistance of control crystal grain of the present invention (ODT) and control circuit.
Fig. 2 is the calcspar of the built-in terminal resistance of crystal grain (ODT) control circuit according to an embodiment of the invention.
The ODT control circuit comprises counting unit 1000, resets signal generation unit 2000 and compares control unit 3000.Counting unit 1000 receives external timing signal EXT_CLK and delay-locked loop (DLL) clock signal DLL_CLK, and counts the bifurcation shot number of each clock from default value.Reset signal generation unit 2000 and reset signal RESET in response to the outside and export first of the bifurcation shot number that is used for initialization dll clock signal DLL_CLK and reset signal R1, and at the fixed time output be used for initialization external timing signal EXT_CLK the bifurcation shot number second reset signal R2.Relatively control unit 3000 in response to ODT command signal ODT_CMD the bifurcation shot number of comparison external timing signal EXT_CLK and the bifurcation shot number of dll clock signal DLL_CLK, with so based on the comparison result and exporting be used to control the ODT enable signal ODTEN of the running of ODT circuit.
Relatively control unit 3000 comprises command signal detecting unit 3200, sign indicating number comparing unit 3400 and enable signal generation unit 3600.Command signal detecting unit 3200 detects the variation at the edge of ODT command signal ODT_CMD, to export the first detection signal P1 and the second detection signal P2.Sign indicating number comparing unit 3400 is in response to the first detection signal P1 and the second detection signal P2 and comparison foreign key EX_CODE and DLL sign indicating number DLL_CODE, and result and export the first comparison signal C1 and the second comparison signal C2 based on the comparison.Enable signal generation unit 3600 is determined the logic level of ODT enable signal ODTEN in response to the first comparison signal C1 and the second comparison signal C2.
Fig. 3 is the circuit diagram of reseting signal generation unit 2000 of the ODT control circuit shown in Fig. 2.
Reset signal generation unit 2000 and comprise that DLL resets signal generation unit 2200, delay duplicate model (model) unit 2400 and outside and resets signal generation unit 2600.DLL resets signal generation unit 2200 and resets signal RESET in response to the outside, and by supply voltage VDD and dll clock signal DLL_CLK is synchronous, produce first and reset signal R1.Postpone duplicate model unit 2400 by the time of delay between modelling dll clock signal DLL_CLK and the external timing signal EXT_CLK definite scheduled time, and reset signal R1 delay scheduled time with first and reset signal EN with output delay.Signal generation unit 2600 is reseted in the outside, and producing second resets signal R2 synchronously by delay being reseted signal EN and external timing signal EXT_CLK.
DLL resets signal generation unit 2200 and comprises D flip-flop, this D flip-flop receives supply voltage VDD and imports D as data, receive dll clock signal DLL_CLK and import CLK as clock, and signal RESET is reseted as reseting input RST in the reception outside, determine that first resets the logic level of signal R1, and export first and reset signal R1.
Equally, the outside is reseted signal generation unit 2600 and is comprised D flip-flop, and this D flip-flop receive delay is reseted signal EN and imported D as data, and reception external timing signal EXT_CLK imports CLK as clock, determine that second resets the logic level of signal R2, and export second and reset signal R2.
Fig. 4 is the circuit diagram of the command signal detecting unit 3200 of the comparison control unit 3000 shown in Fig. 2.
Command signal detecting unit 3200 comprises rising edge detecting unit 3220 and drop edge detecting unit 3240.Rising edge detecting unit 3220 detects the rising edge of ODT command signal ODT_CMD and triggers the first detection signal P1 with bifurcation.The second detection signal P2 is triggered with bifurcation in the drop edge that drop edge detecting unit 3240 detects anti-phase ODT command signal.
Rising edge detecting unit 3220 comprises first delay cell 3222, first and non-(NAND) the door NAND1 and the first inverter INV1.First delay cell 3222 postpones ODT command signal ODT_CMD the clock cycle of external timing signal EXT_CLK.The one NAND door NAND1 carries out the NAND computing of the output signal of the ODT command signal ODT_CMD and first delay cell 3222.The first inverter INV1 is anti-phase to export the first detection signal P1 with the output signal of a NAND door NAND1.
Drop edge detecting unit 3240 comprises the second inverter INV2 and the 3rd inverter INV3, second delay cell 3242 and the 2nd NAND door NAND2.The second inverter INV2 is anti-phase with ODT command signal ODT_CMD.Second delay cell 3242 postpones the output signal of the second inverter INV2 clock cycle of external timing signal EXT_CLK.The 2nd NAND door NAND2 carries out the NAND computing of the output signal of the ODT command signal ODT_CMD and second delay cell 3242.The 3rd inverter INV3 is anti-phase to export the second detection signal P2 with the output signal of the 2nd NAND door NAND2.
Above-mentioned first delay cell 3222 and second delay cell 3242 can comprise a plurality of inverters that are connected in series, the anti-phase by this and signal that received of output.
Fig. 5 is the circuit diagram of the sign indicating number comparing unit 3400 of the comparison control unit 3000 shown in Fig. 2.
Sign indicating number comparing unit 3400 comprises first comparing unit 3420 and second comparing unit 3440.First comparing unit 3420 is based on the first detection signal P1 and comparison foreign key EX_CODE and DLL sign indicating number DLL_CODE, and judges whether bifurcation triggers the first comparison signal C1.Second comparing unit 3440 is based on the second detection signal P2 and comparison foreign key EX_CODE and DLL sign indicating number DLL_CODE, and judges whether bifurcation triggers the second comparison signal C2.
Hereinafter, referring to the running of the detailed interpre(ta)tive code comparing unit 3400 of Fig. 5.
At first, first comparing unit 3420 of sign indicating number comparing unit 3400 begins comparison foreign key EX_CODE and DLL sign indicating number DLL_CODE when changing the first detection signal P1, and bifurcation triggers the first comparison signal C1 when foreign key EX_CODE is identical substantially with DLL sign indicating number DLL_CODE.
Secondly, second comparing unit 3440 of sign indicating number comparing unit 3400 begins comparison foreign key EX_CODE and DLL sign indicating number DLL_CODE when changing the second detection signal P2, and bifurcation triggers the second comparison signal C2 when foreign key EX_CODE is identical substantially with DLL sign indicating number DLL_CODE.
That is sign indicating number comparing unit 3400 triggers the first comparison signal C1 in the place, rising edge of ODT command signal ODT_CMD bifurcation, and triggers the second comparison signal C2 in the place, drop edge of ODT command signal ODT_CMD bifurcation.
In detail, first comparing unit 3420 comprises first memory cell 3422 and first logical block 3424.First memory cell 3422 is stored foreign key EX_CODE in response to the first detection signal P1.First logical block 3424 compares the sign indicating number and DLL sign indicating number DLL_CODE stored in first memory cell 3422, and judges whether bifurcation triggers the first comparison signal C1.
First memory cell 3422 comprises a plurality of first registers, and it can store a position, and then is that foreign key EX_CODE is preserved on unit sequence ground with a position.
First logical block 3424 comprises a plurality of first XORs (XOR) door and the 3rd NAND door NAND3.The corresponding position that each first XOR gate is carried out DLL sign indicating number DLL_CODE with corresponding one that is stored in a plurality of first registers in the XOR computing of a position.The 3rd NAND door NAND3 carry out a plurality of first XOR gate output signal the NAND computing and export the first comparison signal C1.
Second comparing unit 3440 comprises second memory cell 3442 and second logical block 3444.Second memory cell 3442 is stored foreign key EX_CODE in response to the second detection signal P2.Second logical block 3444 compares the sign indicating number and DLL sign indicating number DLL_CODE stored in second memory cell 3442, and judges whether bifurcation triggers the second comparison signal C2.
Second memory cell 3442 comprises a plurality of second registers, and it can store a position, and then is that foreign key EX_CODE is preserved on unit sequence ground with a position.
Second logical block 3444 comprises a plurality of second XORs (XOR) door and the 4th NAND door NAND4.The corresponding position that each second XOR gate is carried out DLL sign indicating number DLL_CODE with corresponding one that is stored in a plurality of second registers in the XOR computing of a position.The 4th NAND door NAND4 carry out a plurality of second XOR gate output signal the NAND computing and export the second comparison signal C2.
Fig. 6 is the circuit diagram of the enable signal generation unit 3600 of the comparison control unit 3000 shown in Fig. 2.
Enable signal generation unit 3600 comprises lock unit 3620, rising driver element 3640, decline driver element 3660 and latch unit 3680.Lock unit 3620 is synchronous with ODT enable signal ODTEN and dll clock signal DLL_CLK.Rising driver element 3640 in response to the first comparison signal C1 output supply voltage VDD as ODT enable signal ODTEN.Decline driver element 3660 is exported earthed voltage VSS as ODT enable signal ODTEN in response to the second comparison signal C2.Latch unit 3680 prevents that ODT enable signal ODTEN from floating.
In detail, lock unit 3620 comprises the 4th inverter INV4, a PMOS transistor PMI and the first nmos pass transistor NM1.The 4th inverter INV4 is anti-phase to export through anti-phase dll clock signal with dll clock signal DLL_CLK.The one PMOS transistor PM1 has reception through the grid of anti-phase dll clock signal and the source electrode-drain path between supply voltage (VDD) terminal and first node NODE1.The first nmos pass transistor NM1 has the grid of reception dll clock signal DLL_CLK and the source electrode-drain path between earthed voltage (VSS) terminal and Section Point NODE2.Therefore, when activating ODT enable signal ODT_EN with the logic level from " low " to " height ", above-mentioned lock unit 3620 is connected a PMOS transistor PM1 and the first nmos pass transistor NM1; And when using the logic level deexcitation ODT enable signal ODT_EN of oneself " low " to " height ", it is disconnected.
Rising driver element 3640 comprises the 5th inverter INV5 and the 2nd PMOS transistor PM2.The 5th inverter INV5 is anti-phase with the first comparison signal C1.The 2nd PMOS transistor PM2 has the grid of the output signal that receives the 5th inverter INV5 and the source electrode-drain path between first node NODE1 and the 3rd node NODE3.Therefore, above-mentioned rising driver element 3640 uses " height " logic level to activate ODT enable signal ODTEN in response to the first comparison signal C1.
Decline driver element 3660 comprises the second nmos pass transistor NM2.The second nmos pass transistor NM2 has the grid of the reception second comparison signal C2 and the source electrode-drain path between Section Point NODE2 and the 3rd node NODE3.Therefore, above-mentioned decline driver element 3660 is used " low " logic level deexcitation ODT enable signal ODTEN in response to the second comparison signal C2.
Latch unit 3680 comprises the inverter latch with hex inverter INV6 and the 7th inverter INV7 and the 8th inverter INV8. with signal inversion, and the 7th inverter INV7 receives hex inverter INV6 and the output signal of anti-phase hex inverter INV6 is anti-phase with output ODT enable signal ODTEN. with the output signal of hex inverter INV6 will export hex inverter INV6. the 8th inverter INV8 through anti-phase signal at the 3rd node NODE3 place
As described above, when triggering the first comparison signal C1, bifurcation activates ODT enable signal ODTEN; And deexcitation ODT enable signal ODTEN when bifurcation triggers the second comparison signal C2.That is embodiments of the invention are determined the activation timing of ODT enable signal ODTEN based on the bifurcation shot number of external timing signal EXT_CLK and dll clock signal DLL_CLK.Therefore, even external timing signal EXT_CLK and dll clock signal DLL_CLK operate under high-frequency, also may prevent with non-wanted timing activate ODT enable signal ODTEN.In addition, the user can set the activation timing of ODT enable signal ODTEN based on initial setting after activating ODT command signal ODT_CMD.
Fig. 7 is for showing the oscillogram according to ODT control method of the present invention.
At first, in reseting step, DLL resets signal generation unit 2200 and resets signal RESET in response to the outside and activate first and reset signal R1, and the outside signal generation unit 2600 of reseting activates second and resets signal R2 (seeing 1.) after the scheduled time definite by the time of delay between modelling dll clock signal DLL_CLK and the external timing signal EXT_CLK.
Secondly, in the dll clock counting step, dll clock counter 1400 is reseted signal R1 in response to first and is begun to work the bifurcation shot number of counting dll clock signal DLL_CLK from default value (anticipating promptly 0), and output bifurcation shot number is as DLL sign indicating number DLL_CODE (seeing 2.).
The 3rd, externally in the clock count step, external clock counter 1200 is reseted signal R2 in response to second and is begun to work the bifurcation shot number of counting external timing signal EXT_CLK from default value (anticipating promptly 5), and 3. output bifurcation shot number as foreign key EX_CODE (opinion).
The 4th, in comparison step, sign indicating number comparing unit 3400 is comparison foreign key EX_CODE and DLL sign indicating number DLL_CODE (seeing 4.) in response to ODT command signal ODT_CMD, and the logic level (seeing 5.) of enable signal generation unit 3600 definite ODT enable signal ODTEN in response to comparative result.
In detail, sign indicating number comparing unit 3400 is stored in the register place with foreign key EX_CODE when changing ODT command signal ODT_CMD, and follows bifurcation triggering ODT enable signal ODTEN when memory code is identical substantially with DLL sign indicating number DLL_CODE.
In comparison step, the rising edge of ODT enable signal ODTEN and ODT command signal ODT_CMD is changed " height " logic level synchronously into, and changes " low " logic level synchronously into the drop edge of ODT command signal ODT_CMD.
As described above, the built-in terminal resistance of crystal grain of the present invention (ODT) control device is determined the activation timing of ODT enable signal based on the bifurcation shot number of external timing signal and dll clock signal.Therefore, even external timing signal and dll clock signal operate under high-frequency, also may prevent with non-wanted timing activate the ODT enable signal.In addition, the user can set the activation timing of ODT enable signal based on initial setting after activating the ODT command signal.
The application's case contains korean patent application case 2005-90953 number and 2006-49027 number relevant theme of applying in Korean Patent office with on September 29th, 2005 and on May 30th, 2006, and its full content is incorporated herein by reference.
Though described the present invention about specific embodiment, those skilled in the art will easily understand, and under the spirit of the present invention that is defined in not breaking away from as claim hereinafter and the situation of category, can carry out various changes and modification.
Claims (40)
1. device of controlling the built-in terminal resistance of crystal grain, this device comprises:
Counting unit, it is used to receive external timing signal and delay-locked loop clock signal, and from each bifurcation shot number of default value counting external timing signal and this delay-locked loop clock signal;
Compare control unit, it is used in response to the built-in terminal resistance command signal of crystal grain, and relatively the bifurcation shot number of being counted of this external timing signal and the bifurcation shot number of being counted of this delay-locked loop clock signal, and result and export the built-in terminal resistance enable signal of crystal grain that is used to control the built-in terminal resistance of this crystal grain based on the comparison; With
Reset the signal generation unit, it is used for reseting signal in response to the outside, and this bifurcation shot number of output initialization this delay-locked loop clock signal first reset signal, and export at the fixed time this external timing signal of initialization this bifurcation shot number second reset signal.
2. device as claimed in claim 1, wherein this is reseted the signal generation unit and resets signal in response to this outside, and by supply voltage and this delay-locked loop clock signal is synchronous, produces this and first resets signal.
3. device as claimed in claim 1, wherein this resets the signal generation unit by this first is reseted that signal is delayed this scheduled time and the signal and this external timing signal that produce are synchronous, produces this and second resets signal.
4. device as claimed in claim 1, wherein this is reseted the signal generation unit and comprises:
Delay-locked loop is reseted the signal generation unit, and it is used for reseting signal in response to this outside, and by supply voltage and this delay-locked loop clock signal is synchronous, produces this and first resets signal;
Postpone the duplicate model unit, its be used for this first reset signal delay should the scheduled time, and export the delayed signal of reseting; And
The signal generation unit is reseted in the outside, and it is used for by this delayed is reseted signal and this external timing signal is synchronous, second resets signal and produce this.
5. device as claimed in claim 4, wherein this delay-locked loop is reseted the signal generation unit and is comprised D flip-flop, it receives this supply voltage and imports as data, receiving this delay-locked loop clock signal imports as clock, and receive this outside and reset signal as reseting input, and determine this first logic level of reseting signal.
6. device as claimed in claim 4 wherein should postpone the duplicate model unit by the time of delay between this delay-locked loop clock signal of modelling and this external timing signal, and determine this scheduled time.
7. device as claimed in claim 4, wherein this outside is reseted the signal generation unit and is comprised D flip-flop, it receives this delayed signal of reseting and imports as data, and receives this external timing signal and import as clock, and determines this second logic level of reseting signal.
8. device as claimed in claim 1, wherein this counting unit comprises:
The delay-locked loop clock counter, it is used for first reseting signal and counting this bifurcation shot number of this delay-locked loop clock signal in response to this, and the bifurcation shot number that output is counted is as the delay-locked loop sign indicating number; And
The external clock counter, it is used for second reseting signal and counting this bifurcation shot number of this external timing signal in response to this, and the bifurcation shot number that output is counted is as foreign key.
9. device as claimed in claim 8, wherein this comparison control unit comprises:
The command signal detecting unit, it is used for exporting first detection signal and second detection signal by the transformation that detects the built-in terminal resistance command signal of this crystal grain;
The sign indicating number comparing unit, it is used in response to this first detection signal and this second detection signal, and by relatively this foreign key and this delay-locked loop sign indicating number, exports first comparison signal and second comparison signal; And
The enable signal generation unit, it is used in response to this first comparison signal and this second comparison signal, and determines the logic level of the built-in terminal resistance enable signal of this crystal grain.
10. device as claimed in claim 9, wherein this command signal detecting unit is by the rising edge of detecting the built-in terminal resistance command signal of this crystal grain, and bifurcation triggers this first detection signal.
11. device as claimed in claim 9, wherein this command signal detecting unit is by the drop edge of detecting the built-in terminal resistance command signal of this crystal grain, and bifurcation triggers this second detection signal.
12. device as claimed in claim 9, wherein this command signal detecting unit comprises:
The rising edge detecting unit, it is used to detect the rising edge of the built-in terminal resistance command signal of this crystal grain, triggers this first detection signal with bifurcation; And
The drop edge detecting unit, it is used to detect the drop edge of the built-in terminal resistance command signal of this crystal grain, triggers this second detection signal with bifurcation.
13. device as claimed in claim 12, wherein this rising edge detecting unit comprises:
Delay cell, it is used for the built-in terminal resistance command signal of this crystal grain is postponed Preset Time;
Gate, it is used to carry out the NAND computing of the output signal of the built-in terminal resistance command signal of this crystal grain and this delay cell; And
Inverter, it is used for the output signal of this gate anti-phase, to export this first detection signal.
14. device as claimed in claim 13, wherein this delay cell postpones the built-in terminal resistance command signal of this crystal grain a clock cycle of this external timing signal.
15. device as claimed in claim 13, wherein this delay cell comprises a plurality of inverters that are connected in series, so that the built-in terminal resistance command signal of this crystal grain is anti-phase.
16. device as claimed in claim 12, wherein this drop edge detecting unit comprises:
First inverter, it is used for the built-in terminal resistance command signal of this crystal grain anti-phase;
Delay cell, it is used for the output signal of this first inverter is postponed Preset Time;
Gate, it is used to carry out the NAND computing of the output signal of this output signal of this first inverter and this delay cell; And
Second inverter, it is used for the output signal of this gate anti-phase, to export this second detection signal.
17. device as claimed in claim 16, wherein this delay cell postpones this output signal of this first inverter a clock cycle of this external timing signal.
18. device as claimed in claim 16, wherein this delay cell comprises a plurality of inverters that are connected in series, so that this output signal of this first inverter is anti-phase.
19. device as claimed in claim 12, wherein bifurcation triggers this first comparison signal to this yard comparing unit in response to this first detection signal when this foreign key is identical substantially with this delay-locked loop sign indicating number.
20. device as claimed in claim 12, wherein bifurcation triggers this second comparison signal to this yard comparing unit in response to this second detection signal when this foreign key is identical substantially with this delay-locked loop sign indicating number.
21. device as claimed in claim 12, wherein this yard comparing unit comprises:
First comparing unit, it is used for relatively this foreign key and this delay-locked loop sign indicating number, and judges based on this first detection signal whether bifurcation triggers this first comparison signal; And
Second comparing unit, it is used for relatively this foreign key and this delay-locked loop sign indicating number, and judges based on this second detection signal whether bifurcation triggers this second comparison signal.
22. device as claimed in claim 21, wherein this first comparing unit comprises:
Memory cell, it is used for storing this foreign key in response to this first detection signal; And
Logical block, it is used for relatively this sign indicating number and this delay-locked loop sign indicating number of storing of this memory cell, to judge whether bifurcation triggers this first comparison signal.
23. device as claimed in claim 22, wherein this memory cell comprises a plurality of registers, its each can store a position, and then be that this foreign key is preserved on unit sequence ground with a position.
24. device as claimed in claim 23, wherein this logical block comprises:
A plurality of XOR gate, each is used for carrying out each of this delay-locked loop sign indicating number and the XOR of the corresponding positions of this corresponding one foreign key that is stored in these a plurality of registers; And
Gate, it is used to carry out the NAND computing of the output signal of these a plurality of XOR gate, and exports this first comparison signal.
25. device as claimed in claim 21, wherein this second comparing unit comprises:
Memory cell, it is used for storing this foreign key in response to this second detection signal; And
Logical block, it is used for relatively this sign indicating number and this delay-locked loop sign indicating number of storing of this memory cell, to judge whether bifurcation triggers this second comparison signal.
26. device as claimed in claim 25, wherein this memory cell comprises a plurality of registers, its each can store a position, and then be that this foreign key is preserved on unit sequence ground with a position.
27. device as claimed in claim 26, wherein this logical block comprises:
A plurality of XOR gate, each and the XOR of the corresponding positions that is stored in this foreign key among corresponding of this a plurality of registers that each carries out this delay-locked loop sign indicating number; And
Gate, it is used to carry out the NAND computing of the output signal of these a plurality of XOR gate, and exports this second comparison signal.
28. device as claimed in claim 21, wherein this enable signal generation unit is in response to this first comparison signal, and activates the built-in terminal resistance enable signal of this crystal grain with logic high.
29. device as claimed in claim 21, wherein this enable signal generation unit is in response to this second comparison signal, and with the built-in terminal resistance enable signal of this crystal grain of logic low deexcitation.
30. device as claimed in claim 21, wherein this enable signal generation unit changes the built-in terminal resistance enable signal of this crystal grain in response to this delay-locked loop clock signal.
31. device as claimed in claim 21, wherein this enable signal generation unit comprises:
The rising driver element, its be used in response to this first comparison signal and output supply voltage as the built-in terminal resistance enable signal of this crystal grain;
The decline driver element, it is used for exporting earthed voltage as the built-in terminal resistance enable signal of this crystal grain in response to this second comparison signal;
Lock unit, it is used for the built-in terminal resistance enable signal of this crystal grain and this delay-locked loop clock signal synchronous; And
Latch unit, it is used to latch the built-in terminal resistance enable signal of this crystal grain.
32. device as claimed in claim 31, wherein this lock unit comprises:
First inverter, it is used for this delay-locked loop clock signal anti-phase, to export through anti-phase delay-locked loop clock signal;
The one PMOS transistor, it has and receives this through grid of anti-phase delay-locked loop clock signal and the source electrode-drain path between this power supply voltage terminal and first node; And
First nmos pass transistor, it has the grid of this delay-locked loop clock signal of reception and the source electrode-drain path between Section Point and this earthed voltage terminal,
Wherein this lock unit is respectively via this first node and this Section Point and be coupled to this rising driver element and this decline driver element.
33. device as claimed in claim 32 wherein should comprise by the rising driver element:
Second inverter, it is used for this first comparison signal anti-phase; And
The 2nd PMOS transistor, it has the grid of the output signal that receives this second inverter and the source electrode-drain path between this first node and the 3rd node,
Wherein the 3rd node is connected to this decline driver element.
34. device as claimed in claim 32 wherein should comprise the 2nd NOMS transistor by the decline driver element, the 2nd NOMS transistor has the grid of this second comparison signal of reception and the source electrode-drain path between this Section Point and the 3rd node.
35. device as claimed in claim 32, wherein this latch unit comprises:
The inverter latch, it has and is used for second inverter with signal inversion at the 3rd node place, and is used for the output signal of this second inverter anti-phase will be somebody's turn to do the 3rd inverter that exports this second inverter through anti-phase signal to; And
The 4th inverter, it is used for this output signal of this second inverter anti-phase, to export the built-in terminal resistance enable signal of this crystal grain.
36. a method of controlling the built-in terminal resistance of crystal grain, this method comprises:
Reset step, it is reseted signal in response to the outside and activates first and reset signal, and activates second at the fixed time and reset signal;
Delay-locked loop clock count step, it first resets signal and from the bifurcation shot number of default value count delay locked loop clock signal in response to this, and the bifurcation shot number that output is counted is as the delay-locked loop sign indicating number;
The external clock counting step, it second resets signal and from the bifurcation shot number of default value counting external timing signal in response to this, and the bifurcation shot number that output is counted is as foreign key; And
Comparison step, it is in response to the built-in terminal resistance command signal of crystal grain, and determine the logic level of the built-in terminal resistance enable signal of crystal grain by relatively this foreign key and this delay-locked loop sign indicating number, to produce the built-in terminal resistance enable signal of crystal grain, the logic level of the built-in terminal resistance enable signal of this crystal grain is based on comparative result and determines.
37. method as claimed in claim 36 is wherein reseted in the step at this, by the time of delay between this delay-locked loop clock signal of modelling and this external timing signal, and sets this scheduled time.
38. method as claimed in claim 36, wherein in this comparison step, when changing the built-in terminal resistance command signal of this crystal grain, this foreign key is stored in a plurality of registers, and when this foreign key of storing is identical substantially with this delay-locked loop sign indicating number, changes the built-in terminal resistance enable signal of this crystal grain.
39. method as claimed in claim 36, wherein in this comparison step, the rising edge of built-in terminal resistance enable signal of this crystal grain and the built-in terminal resistance command signal of this crystal grain is changed enabled state synchronously into.
40. method as claimed in claim 36, wherein in this comparison step, the drop edge of built-in terminal resistance enable signal of this crystal grain and the built-in terminal resistance command signal of this crystal grain is changed dead status synchronously into.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR20050090953 | 2005-09-29 | ||
| KR90953/05 | 2005-09-29 | ||
| KR1020060049027A KR100761359B1 (en) | 2005-09-29 | 2006-05-30 | On-die termination control circuit and method |
| KR49027/06 | 2006-05-30 |
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| Publication Number | Publication Date |
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| CN1941629A CN1941629A (en) | 2007-04-04 |
| CN1941629B true CN1941629B (en) | 2010-05-12 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2006101317334A Expired - Fee Related CN1941629B (en) | 2005-09-29 | 2006-09-29 | Apparatus and method for controlling on die termination |
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| Country | Link |
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| KR (1) | KR100761359B1 (en) |
| CN (1) | CN1941629B (en) |
| TW (1) | TWI316720B (en) |
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| KR100929846B1 (en) * | 2007-10-23 | 2009-12-04 | 주식회사 하이닉스반도체 | On Die Termination Control Circuit |
| KR100921832B1 (en) | 2008-03-03 | 2009-10-16 | 주식회사 하이닉스반도체 | On Die Termination controlling circuit of semiconductor memory device |
| KR100929833B1 (en) | 2008-04-02 | 2009-12-07 | 주식회사 하이닉스반도체 | Output Enable Signal Generation Circuit and Generation Method |
| KR100949276B1 (en) * | 2008-09-08 | 2010-03-25 | 주식회사 하이닉스반도체 | Termination tuning circuit and semiconductor memory device including the same |
| KR101043722B1 (en) | 2010-02-04 | 2011-06-27 | 주식회사 하이닉스반도체 | Latency control circuit and semiconductor memory device including the same |
| US10153014B1 (en) | 2017-08-17 | 2018-12-11 | Micron Technology, Inc. | DQS-offset and read-RTT-disable edge control |
| CN113808634B (en) * | 2020-06-11 | 2024-02-27 | 华邦电子股份有限公司 | Delay phase-locked loop device and updating method thereof |
| CN115599196A (en) * | 2021-07-09 | 2023-01-13 | 长鑫存储技术有限公司（Cn） | Enable control circuit and semiconductor memory |
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|---|---|---|---|---|
| CN1519853A (en) * | 2002-11-20 | 2004-08-11 | ���ǵ�����ʽ���� | On-die termination circuit and method for reducing on-chip DC current, and memory system including memory device having same |
| CN1655279A (en) * | 2004-02-13 | 2005-08-17 | 海力士半导体有限公司 | On die termination mode transfer circuit in semiconductor memory device and its method |
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| KR100468728B1 (en) * | 2002-04-19 | 2005-01-29 | 삼성전자주식회사 | On-chip terminator, Control circuit there-of and Control method there-of in semiconductor integrated circuit |
| KR100502408B1 (en) * | 2002-06-21 | 2005-07-19 | 삼성전자주식회사 | Memory system for controlling power-up sequence of memory device embedding active termination and the method of power-up and initialization thereof |
| KR100506976B1 (en) * | 2003-01-03 | 2005-08-09 | 삼성전자주식회사 | synchronous semiconductor memory device having on die termination circuit |
| KR100670674B1 (en) * | 2005-06-30 | 2007-01-17 | 주식회사 하이닉스반도체 | Semiconductor memory deivce |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1519853A (en) * | 2002-11-20 | 2004-08-11 | ���ǵ�����ʽ���� | On-die termination circuit and method for reducing on-chip DC current, and memory system including memory device having same |
| CN1655279A (en) * | 2004-02-13 | 2005-08-17 | 海力士半导体有限公司 | On die termination mode transfer circuit in semiconductor memory device and its method |
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| TW200721195A (en) | 2007-06-01 |
| KR100761359B1 (en) | 2007-09-27 |
| KR20070036635A (en) | 2007-04-03 |
| CN1941629A (en) | 2007-04-04 |
| TWI316720B (en) | 2009-11-01 |
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