1316720 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種控制一晶粒内建終端電阻（〇DT)之裝 置及方法’且更特定言之，本發明係關於一種用於減小一 延遲鎖定迴路（DLL)時脈與一内部時脈之間的一時脈域差 的ODT控制裝置。 【先前技術】</ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; An ODT control device that delays a time domain between the locked loop (DLL) clock and an internal clock. [Prior Art]
包括一用複數個中央處理單元（CPU)、半導體記憶體襞 置及閘極陣列建構之積體電路（IC)的各種半導體裝置組合 在諸如一個人電腦、一伺服器及一工作站之電氣產品内。 大多數半導體裝置包括一用於經由輸入墊而接收外部輸入 信號之接收器，及一用於經由輸出墊而向外部輸出内部信 號之傳輸器。 ° 隨著電氣產品之運作速度增大’在半導體裝置之間作為 介面之域的擺動範圍變得更窄以最小化傳輸信號所需之 延遲時間。隨著信號之擺動範圍變得更窄，外部雜訊之影 β曰大目此，—歸因於一介面端子之一阻抗失配 反射係關鍵所在。一船&一 ^ ^ s ^ L 現 般而$，阻抗失配由外部雜訊、電源 合 運作溫度變化及製造過程變化而發生。 抗失配時’很難以-高速率傳送資料且自半導 體裝置之介面端；认· 輸出的=貝料可捩扭。若一終端電阻器之 未適當匹配， 信號傳輸失敗。傳送之^可被反射，進而導致- 一外部固定雷卩日， 器由於一積體電路之老化、運作溫度變 H4686.doc 1316720 化及製造過程變化而存在阻抗匹配的困難。因此，當半導 體裝置接收一捩扭信號時，頻繁發生諸如安裝/保持失敗 及一輸入位準之判斷錯誤的問題。 最近，用於調節終端電阻器之阻抗的技術已經發展以藉 , 由控制並聯連接之複數個電晶體中之接通電晶體的數目來 得到與一外部參考阻抗相同的阻抗。 因此，用一被稱為一晶載終端電阻或晶粒内建終端電阻 (ODT)的阻抗匹配電路來建構需要一高運作速度之半導體 ’裝置。 在下文中，參看圖1A及圖1B詳細描述一習知ODT控制 方法之一問題。 圖1A為展示在一低頻率運作下之習知晶粒内建終端電阻 (ODT)控制方法的波形圖，且圖1B為展示在一高頻率運作 下之習知晶粒内建終端電阻（ODT)控制方法的波形圖。 首先，在啟動ODT命令信號ODT_CMD之後，回應於一 g 外部時脈信號EXT_CLK之一第一上升邊緣(T0)而啟動一延 遲鎖定迴路（DLL)時脈信號DLL_CLK，且回應於DLL時脈 信號DLL_CLK而啟動一 ODT啟用信號ODTEN。 接著，一ODT電路在一回應於外部時脈信號EXT—CLK之 一第二上升邊緣（T1)而啟動的ODT信號ODT之控制下運 作。 此時，需要一預定時間”DLL至ODT之延遲時間”，其為 一在啟動ODT啟用信號ODTEN之後大體上運作ODT電路的 延遲。不管外部時脈信號EXT—CLK之頻率變化，預定時 114686.doc •6· 1316720 間"DLL至〇DT之延遲時間"固定。 如圖1A中所示，當外部時脈信號ext—clk在低頻率運 作下運作時，外部時脈信號EXT_CLK2 一個時脈週期（意 即，自το至τι)比預定時間"〇1^至〇]〇1[之延遲時間，•長。因 此，可能在外部時脈信號EXT_CLK之第二上升邊緣（T1)處 - 正常運作ODT電路。 另方面’如圖1Β中所示，當外部時脈信號ext CLK φ 在南頻率運作下運作時，外部時脈信號EXT_CLK之時脈週 期（思即’自T0至T1)比預定時間"DLL至ODT之延遲時間” 短。因此，ODT電路在外部時脈信號EXT_CLK之第三或第 二以後之上升邊緣處（意即，在丁2或丁2以後處）而非在第二 上升邊緣（τι)處運作。亦即，〇DT電路可遲於一所要時序 而運作。 【發明内容】 因此，本發明之一目標為提供一種控制一晶粒内建終端 籲電阻（〇DT)及控制電路之方法，該方法能夠不管一 ODT電 路之運作頻率而藉由減小一延遲鎖定迴路（DLL)時脈與 一内部時脈之間的一時脈域差來以一所要時序執行一 〇dt 運作。 椤據本發明之一態樣，提供一種用於控制一晶粒内建終 端電阻_τ)之裝置，纟包括：—計數單元，其用於接收 外4時脈信號及一延遲鎖定迴路（DLL)時脈信號，且自 一預設值起計數外部時脈信號及DLL時脈信號之每一者的 雙態觸發數目；-比較控制單元，其用於回應於―㈣命 114686.doc 1316720 7 L號，而比較外部時脈信號的所計數之雙態觸發數目與 dll時脈信號的所計數之雙態觸發數目，且基於比較結果 而輸出一用於控制0DT之0DT啟用信號。A plurality of semiconductor devices including a plurality of central processing units (CPUs), semiconductor memory devices, and integrated circuits (ICs) constructed by gate arrays are incorporated in electrical products such as a personal computer, a server, and a workstation. Most semiconductor devices include a receiver for receiving an external input signal via an input pad, and a transmitter for outputting an internal signal to the outside via an output pad. ° As the operating speed of electrical products increases, the range of oscillation as a domain between interfaces between semiconductor devices becomes narrower to minimize the delay time required to transmit signals. As the swing range of the signal becomes narrower, the shadow of the external noise is larger, because the impedance mismatch of one of the interface terminals is critical. A ship & a ^ ^ s ^ L is now a $, impedance mismatch occurs due to external noise, power supply operating temperature changes and manufacturing process changes. When it is resistant to mismatch, it is difficult to transmit data at a high rate and from the interface end of the semiconductor device; the output = the material can be twisted. If a terminating resistor is not properly matched, the signal transmission fails. The transmitted ^ can be reflected, which in turn leads to an external fixed Thunder day, which is difficult to match due to aging of an integrated circuit, operating temperature changes, and manufacturing process variations. Therefore, when the semiconductor device receives a twist signal, problems such as mount/hold failure and an input level error are frequently caused. Recently, techniques for adjusting the impedance of a terminating resistor have been developed to obtain the same impedance as an external reference impedance by controlling the number of turn-on transistors in a plurality of transistors connected in parallel. Therefore, an impedance matching circuit called an on-chip termination resistor or a die built-in termination resistor (ODT) is used to construct a semiconductor device requiring a high operating speed. In the following, a problem of a conventional ODT control method will be described in detail with reference to Figs. 1A and 1B. 1A is a waveform diagram showing a conventional grain built-in termination resistance (ODT) control method at a low frequency operation, and FIG. 1B is a conventional grain built-in termination resistance (ODT) control method showing a high frequency operation. Waveform diagram. First, after the ODT command signal ODT_CMD is started, a delay locked loop (DLL) clock signal DLL_CLK is started in response to a first rising edge (T0) of a g external clock signal EXT_CLK, and is responsive to the DLL clock signal DLL_CLK. And start an ODT enable signal ODTEN. Next, an ODT circuit operates under the control of an ODT signal ODT initiated in response to a second rising edge (T1) of the external clock signal EXT_CLK. At this time, a predetermined time "DLL to ODT delay time" is required, which is a delay in which the ODT circuit is substantially operated after the ODT enable signal ODTEN is activated. Regardless of the frequency change of the external clock signal EXT_CLK, the predetermined delay time between the time of 114686.doc •6·1316720 "DLL to 〇DT" fixed. As shown in FIG. 1A, when the external clock signal ext_clk operates at a low frequency operation, the external clock signal EXT_CLK2 has a clock period (ie, from το to τι) to a predetermined time "〇1^ 〇]〇1[The delay time, • long. Therefore, it is possible to operate the ODT circuit normally at the second rising edge (T1) of the external clock signal EXT_CLK. On the other hand, as shown in Figure 1Β, when the external clock signal ext CLK φ operates under the south frequency operation, the clock period of the external clock signal EXT_CLK (thinking from 'T0 to T1) is longer than the predetermined time"DLL The delay time to ODT is short. Therefore, the ODT circuit is at the rising edge of the third or second after the external clock signal EXT_CLK (ie, after D2 or D2) rather than at the second rising edge ( Τι) operates, that is, the 〇 DT circuit can operate later than a desired timing. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a control for a die built-in terminal resistor (〇 DT) and a control circuit In one method, the method can perform a 〇dt operation at a desired timing by reducing a clock domain difference between a delay locked loop (DLL) clock and an internal clock regardless of the operating frequency of an ODT circuit. According to one aspect of the present invention, there is provided an apparatus for controlling a die built-in termination resistor _τ), comprising: a counting unit for receiving an external 4 clock signal and a delay locked loop (DLL) ) clock signal, and from a preset Counting the number of toggles for each of the external clock signal and the DLL clock signal; - the comparison control unit, which is used to compare the external clock signal in response to the "(4) life 114686.doc 1316720 7 L number Counting the number of toggles and the counted number of toggles of the dll clock signal, and outputting an OT enable signal for controlling 0DT based on the comparison result.
A 根據本發明之另一態樣， 電阻（ODT)之方法，其包括 提供一種控制一晶粒内建終端 •'一重設步驟，其回應於一外 部重設信號而啟動一第 啟動一第二重設信號； 一重設信號，且在一預定時間之後 一 DLL時脈計數步驟，其回應於第A method according to another aspect of the present invention, an electrical resistance (ODT) method, comprising: providing a control of a die built-in terminal, a resetting step of initiating a second start in response to an external reset signal Reset signal; a reset signal, and a DLL clock count step after a predetermined time, in response to the
重认仏號而自一預設值起計數一 DLL時脈信號之雙態觸 發數目，且輸出所計數之雙態觸發數目作為-DLL碼；-外部時脈計數步驟，其回應於第二重設信號而自—預設值 起汁數外°卩時脈信號之雙態觸發數目，且輸出所計數之 雙態觸發數目作為—外部碼；及—比較步驛，彡回應於一 ODT命令仏號而藉由比較外部碼與dll碼來確定一 〇〇了啟 用“號之一邏輯位準 以產生一 ODT啟用信號，該〇DT啟 用信號之邏輯位準係基於比較結果而確定。Re-recognizing the nickname and counting the number of toggle triggers of a DLL clock signal from a preset value, and outputting the counted number of toggles as a -DLL code; - an external clock count step, which responds to the second Reset the signal and the number of toggles from the preset value to the number of juices, and the number of toggles output by the output is the external code; and - the comparison step, 彡 responds to an ODT command By comparing the external code with the dll code, it is determined that the logic level of the DT enable signal is determined based on the comparison result when the "one logic level" is enabled to generate an ODT enable signal.
【實施方式】 下文中將參看隨附圖式詳細描述一種根據本發明之 控制一晶粒内建終端電阻（ODT)及控制電路的方法。 圖2為根據本發明之一實施例之晶粒内建終端電阻（〇dt) 控制電路的方塊圖。 ODT控制電路包括一計數單元1〇〇〇、一重設信號產生單 元2000及一比較控制單元3〇〇〇。計數單元1000接收一外部 時脈k號EXT—CLK及一延遲鎖定迴路（DLL)時脈信號 DLL_CLK，且自一預設值起計數每一時脈之一雙態觸發 114686.doc 1316720 數目。重設信號產生單元2000回應於一外部重設信號 RESET而輸出一用於初始化DLL時脈信號DLL_CLK之雙態 觸發數目的第一重設信號R1，且在一預定時間之後輸出一 用於初始化外部時脈信號EXT_CLK之雙態觸發數目的第 二重設信號R2。比較控制單元3000回應於一 ODT命令信號 ODT—CMD而比較外部時脈信號EXT—CLK的雙態觸發數目 與DLL時脈信號DLL_CLK的雙態觸發數目，以進而基於比 較結果而輸出一用於控制一 ODT電路之一運作的ODT啟用 信號ODTEN。 計數單元1000包括一外部時脈計數器1200及一DLL·時脈 計數器1400。外部時脈計數器1200回應於第二重設信號R2 而開始計數外部時脈信號EXT—CLK之雙態觸發數目’且 輸出雙態觸發數目作為一外部碼EX_CODE。DLL時脈計數 器1400回應於第一重設信號R1而開始計數DLL時脈信號 DLL_CLK之雙態觸發數目，且輸出雙態觸發數目作為一 DLL碼 DLL_CODE。[Embodiment] Hereinafter, a method of controlling a die built-in terminating resistor (ODT) and a control circuit according to the present invention will be described in detail with reference to the accompanying drawings. 2 is a block diagram of a die built-in termination resistor (〇dt) control circuit in accordance with an embodiment of the present invention. The ODT control circuit includes a counting unit 1A, a reset signal generating unit 2000, and a comparison control unit 3A. The counting unit 1000 receives an external clock k number EXT_CLK and a delay locked loop (DLL) clock signal DLL_CLK, and counts the number of one-state triggers 114686.doc 1316720 of each clock from a preset value. The reset signal generating unit 2000 outputs a first reset signal R1 for initializing the number of toggles of the DLL clock signal DLL_CLK in response to an external reset signal RESET, and outputs a one for initializing the external after a predetermined time. The binary signal of the clock signal EXT_CLK triggers a second reset signal R2. The comparison control unit 3000 compares the number of toggles of the external clock signal EXT_CLK with the number of toggles of the DLL clock signal DLL_CLK in response to an ODT command signal ODT_CMD, and further outputs a control for the control based on the comparison result. One of the ODT circuits operates an ODT enable signal ODTEN. The counting unit 1000 includes an external clock counter 1200 and a DLL·clock counter 1400. The external clock counter 1200 starts counting the number of toggles of the external clock signal EXT_CLK in response to the second reset signal R2 and outputs the number of toggles as an external code EX_CODE. The DLL clock counter 1400 starts counting the number of toggle triggers of the DLL clock signal DLL_CLK in response to the first reset signal R1, and outputs the number of toggles as a DLL code DLL_CODE.
比較控制單元3000包括一命令信號偵測單元3200、一碼 比較單元3400及一啟用信號產生單元3600。命令信號偵測 單元3200偵測ODT命令信號ODT—CMD之邊緣之一變化， 以輸出第一偵測信號P1及第二偵測信號P2。碼比較單元 3400回應於第一偵測信號P1及第二偵測信號P2而比較外部 石馬EX_CODE與DLL碼DLL_CODE，且基於比較結果而輸出 第一比較信號C1及第二比較信號C2。啟用信號產生單元 3600回應於第一比較信號C1及第二比較信號C2而確定ODT 114686.doc -9- 1316720 啟用信號ODTEN之一邏輯位準。 圖3為圖2中所示之0DT控制電路之重設信號產生單元 2 0 0 0的電路圖。 重設信號產生單元2000包括一 DLL重設信號產生單元 2200、一延遲複本模型單元2400及一外部重設信號產生單 元2600。DLL重設信號產生單元2200回應於外部重設信號 RESET，而藉由將一電源電壓VDD與DLL時脈信號 DLL·—CLK同步，來產生第一重設信號R1。延遲複本模型 單元2400藉由模型化DLL時脈信號DLL_CLK與外部時脈信 號EXT_CLK之間的一延遲時間而確定一預定時間，且將 第一重設信號R1延遲預定時間以輸出一延遲重設信號 EN。外部重設信號產生單元2600藉由將延遲重設信號EN 與外部時脈信號EXT—CLK同步而產生第二重設信號R2。 DLL重設信號產生單元2200包括一 D型正反器，該D型 正反器接收電源電壓VDD作為一資料輸入D，接收DLL時 脈信號DLL_CLK作為一時脈輸入CLK，並接收外部重設信 號RESET作為一重設輸入RST，確定第一重設信號R1之一 邏輯位準，且輸出第一重設信號R1。 同樣，外部重設信號產生單元2600包括一 D型正反器， 該D型正反器接收延遲重設信號EN作為一資料輸入D，並 接收外部時脈信號EXT—CLK作為一時脈輸入CLK，確定第 二重設信號R2之一邏輯位準，且輸出第二重設信號R2。 圖4為圖2中所示之比較控制單元3000之命令信號偵測單 3 2 0 0的電路圖。 114686.doc -10- 1316720 命令信號偵測單元3200包括一上升邊緣偵測單元3220及 一下降邊緣偵測單元3240。上升邊緣偵測單元3220偵測 ODT命令信號〇DT_CMD之一上升邊緣以雙態觸發第一偵 測信號P1。下降邊緣偵測單元3240偵測一反相ODT命令信 . 號之一下降邊緣以雙態觸發第二偵測信號P2。 _ 上升邊緣偵測單元3220包括一第一延遲單元3222、一第 一反及（NAND)閘NAND1及一第一反相器INV1。第一延遲 單元3222將ODT命令信號〇DT_CMD延遲外部時脈信號 • EXT一CLK之一個時脈週期。第一 NAND閘NAND1執行一 ODT命令信號ODT_CMD與第一延遲單元3222之一輸出信 號的NAND運算。第一反相器INV1將第一 NAND閘NAND1 之一輸出信號反相以輸出第一偵測信號P1。 下降邊緣偵測單元3240包括第二反相器INV2與第三反 相器INV3、一第二延遲單元3242及一第二NAND閘 NAND2。第二反相器INV2將ODT命令信號〇DT_CMD反 φ 相。第二延遲單元3242將第二反相器INV2之一輸出信號延 遲外部時脈信號EXT_CLK之一個時脈週期，第二NAND閘 NAND2執行一 ODT命令信號ODT—CMD與第二延遲單元 3242之一輸出信號的NAND運算。第三反相器INV3將第二 NAND閘NAND2之一輸出信號反相以輸出第二偵測信號 P2 〇 上述第一延遲單元3222及第二延遲單元3242可包括串聯 連接之複數個反相器，藉此反相並輸出所接收之信號。 圖5為圖2中所示之比較控制單元3〇〇〇之碼比較單元34〇〇 114686.doc •11- 1316720 的電路圖。 碼比較單元3400包括第一比較單元3420及第二比較單元 3440。第一比較單元3420基於第一偵測信號pi而比較外部 碼EX一CODE與DLL碼DLL_CODE，且判定是否雙態觸發第 ， 一比較信號c 1。第二比較單元3440基於第二偵測信號P2而 . 比較外部碼EX_C0DE與DLL碼DLL一CODE，且判定是否雙 態觸發第二比較信號C2。 | 在下文中，參看圖5詳細解釋碼比較單元3400之一運 作。 首先’碼比較單元3400之第一比較單元3420當轉變第一 偵測信號P1時開始比較外部碼EX_CODE與DLL碼 DLL—CODE，且當外部碼 EX C0DE與 DLL碼 DLL—CODE大 體上相同時雙態觸發第一比較信號c 1。 其次，碼比較單元3400之第二比較單元3440當轉變第二 偵測信號P2時開始比較外部碼EX_CODE與DLL碼 • DLL—CODE，且當外部碼 EX—CODE與 DLL碼 DLL_CODE大 體上相同時雙態觸發第二比較信號C2。 亦即，碼比較單元3400在ODT命令信號〇DT_CMD之上 升邊緣處雙態觸發第一比較信號C1，且在〇DT命令信號 ODT—CMD之下降邊緣處雙態觸發第二比較信號匸2。 詳言之’第一比較單元3420包括一第一儲存單元3422及 一第一邏輯單元3424。第一儲存單元3422回應於第一偵測 信號P1而儲存外部碼EX_CODE。第一邏輯單元3424比較 第一儲存單元3斗22中的所儲存之碼與DLL碼DLL_CODE， 114686.doc -12- 1316720 且判定是否雙態觸發第一比較信號ci。 第一儲存單元3422包括複數個第一暫存器，其能夠儲存 —個位元’進而以一個位元為單位順序地保存外部碼 EX CODE。 第一邏輯單元3424包括複數個第一互斥或（x〇r)閘及一 第三NAND閘NAND3。每一第一 XOR閘執行一 DLL碼 DLL—CODE之相應一個位元與保存於複數個第一暫存器中 的相應一者中之一個位元的X0R運算。第三NAND閘 NAND3執行複數個第一 X0R閘之輸出信號的一 NAND運算 且輸出第一比較信號C1。 第二比較單元3440包括一第二儲存單元3442及一第二邏 輯單元3444。第二儲存單元3442回應於第二偵測信號P2而 儲存外部碼EX_C0DE。第二邏輯單元3444比較第二儲存 單元3442中的所儲存之碼與DLL碼DLL_C0DE，且判定是 否雙態觸發第二比較信號C2。 第二儲存單元3442包括複數個第二暫存器，其能夠儲存 一個位元，進而以一個位元為單位順序地保存外部碼 EX_C0DE。 第二邏輯單元3444包括複數個第二互斥或（XOR)閘及一 第四NAND閘NAND4。每一第二X0R閘執行一 DLL碼 DLL_CODE之相應一個位元與保存於複數個第二暫存器中 的相應一者中之一個位元的X0R運算。第四NAND閘 NAND4執行複數個第二X0R閘之輸出信號的一NAND運算 且輸出第二比較信號C2。 114686.doc •13· 1316720 圖6為圖2中所示之比較控制單元3000之啟用信號產生單 元3600的電路圖。 啟用信號產生單元3600包括一同步單元3620、一上升驅 動單元3640、一下降驅動單元3 660及一鎖存器單元3680。 同步單元3620將ODT啟用信號ODTEN與DLL時脈信號 DLL—CLK同步。上升驅動單元3640回應於第一比較信號 C1而輸出電源電壓VDD作為ODT啟用信號ODTEN »下降 驅動單元3660回應於第二比較信號C2而輸出一接地電壓 VSS作為ODT啟用信號ODTEN。鎖存器單元3680防止ODT 啟用信號ODTEN浮動。 詳言之，同步單元3620包括一第四反相器INV4、一第 一 PMOS電晶體PM1及一第一 NMOS電晶體NM1 »第四反相 器INV4將DLL時脈信號DLL—CLK反相以輸出一經反相之 DLL時脈信號。第一 PMOS電晶體PM1具有一接收經反相 之DLL時脈信號的閘極及一在電源電壓（VDD)端子與一第 一節點NODE1之間的源極-汲極路徑。第一 NMOS電晶體 NM1具有一接收DLL時脈信號DLL_CLK的閘極及一在接地 電壓（VSS)端子與一第二節點NODE2之間的源極-汲極路 徑。因此，當用一自"低"至”高"之邏輯位準啟動ODT啟用 信號ODT_EN時，上述同步單元3620接通第一 PMOS電晶 體PM1及第一 NMOS電晶體NM1 ;且當用一自"低"至”高” 之邏輯位準撤銷ODT啟用信號ODT_EN時將其斷開。 上升驅動單元3640包括一第五反相器INV5及一第二 PMOS電晶體PM2。第五反相器INV5將第一比較信號C1反 114686.doc -14- 1316720 相》第二PMOS電晶體PM2具有一接收第五反相器INV5之 一輸出信號的閘極及一在第一節點NODE1與一第三節點 N0DE3之間的源極-汲極路徑。因此，上述上升驅動單元 3640回應於第一比較信號C1而用一"高”邏輯位準啟動0DT 啟用信號0DTEN。 下降驅動單元3660包括一第二NM0S電晶體NM2。第二 NM0S電晶體NM2具有一接收第二比較信號C2的閘極及一 在第二節點N0DE2與第三節點N0DE3之間的源極-汲極路 徑。因此，上述下降驅動單元3660回應於第二比較信號C2 而用一"低”邏輯位準撤銷0DT啟用信號0DTEN。 鎖存器單元3680包括一具有第六反相器INV6與第七反 相器INV7及一第八反相器INV8之反相器鎖存器。第六反 相器INV6在第三節點NODE3處將一信號反相，且第七反 相器INV7接收並反相第六反相器INV6之一輸出信號以將 經反相之信號輸出至第六反相器INV6。第八反相器INV8 將第六反相器INV6之輸出信號反相以輸出ODT啟用信號 ODTEN。 如上文所描述，當雙態觸發第一比較信號C1時啟動0DT 啟用信號ODTEN ;且當雙態觸發第二比較信號C2時撤銷 ODT啟用信號ODTEN。亦即，本發明之實施例基於外部時 脈信號EXT_CLK及DLL時脈信號DLL—CLK之雙態觸發數 目來確定ODT啟用信號ODTEN的啟動時序。因此，即使外 部時脈信號EXT_CLK及DLL時脈信號DLL—CLK在一高頻 率下運作，亦可能防止以非所要之時序啟動ODT啟用信號 114686.doc •15· 1316720 ODTEN。另外’一使用者可基於一初始設疋而在啟動〇DT 命令信號〇DT_CMD之後設定0DT啟用信號0DTEN之啟動 時序。 圖7為展示根據本發明之〇DT控制方法的波形圖。 首先，在一重設步驟中’ DLL重設信號產生單元2200回 應於外部重設信號RESET而啟動第一重設信號R1 ’且外部 重設信號產生單元2600在藉由模塑化DLL時脈信號 DLL_CLK與外部時脈信號EXT_CLK之間的一延遲時間而 • 確定之預定時間之後啟動第二重設信號R2(見①）。 其次，在一 DLL時脈計數步驟中，DLL時脈計數器1400 回應於第一重設信號R1而開始自一預設值（意即，0)起計 數DLL時脈信號DLL_CLK之雙態觸發數目’且輸出雙態觸 發數目作為DLL碼DLL—CODE(見②）。 第三，在一外部時脈計數步驟中，外部時脈計數器1200 回應於第二重設信號R2而開始自一預設值（意即，5)起計 $ 數外部時脈信號EXT_CLK之雙態觸發數目，且輸出雙態 觸發數目作為外部碼EX_CODE(見③）。 第四，在一比較步驟中，碼比較單元3400回應於ODT命 令信號ODT_CMD而比較外部碼EX_CODE與DLL碼 DLL—CODE (見④）’且啟用信號產生單元3600回應於比車交 結果而確定ODT啟用信號ODTEN之一邏輯位準（見⑤）。The comparison control unit 3000 includes a command signal detecting unit 3200, a code comparing unit 3400, and an enable signal generating unit 3600. The command signal detecting unit 3200 detects one of the edges of the ODT command signal ODT_CMD to output the first detecting signal P1 and the second detecting signal P2. The code comparison unit 3400 compares the external stone horse EX_CODE with the DLL code DLL_CODE in response to the first detection signal P1 and the second detection signal P2, and outputs the first comparison signal C1 and the second comparison signal C2 based on the comparison result. The enable signal generating unit 3600 determines one of the logic levels of the ODT 114686.doc -9- 1316720 enable signal ODTEN in response to the first comparison signal C1 and the second comparison signal C2. 3 is a circuit diagram of a reset signal generating unit 200 0 0 of the 0DT control circuit shown in FIG. 2. The reset signal generating unit 2000 includes a DLL reset signal generating unit 2200, a delayed replica model unit 2400, and an external reset signal generating unit 2600. The DLL reset signal generating unit 2200 generates a first reset signal R1 by synchronizing a power supply voltage VDD with the DLL clock signal DLL·-CLK in response to the external reset signal RESET. The delay replica model unit 2400 determines a predetermined time by modeling a delay time between the DLL clock signal DLL_CLK and the external clock signal EXT_CLK, and delays the first reset signal R1 by a predetermined time to output a delay reset signal. EN. The external reset signal generating unit 2600 generates the second reset signal R2 by synchronizing the delay reset signal EN with the external clock signal EXT_CLK. The DLL reset signal generating unit 2200 includes a D-type flip-flop that receives the power supply voltage VDD as a data input D, receives the DLL clock signal DLL_CLK as a clock input CLK, and receives an external reset signal RESET. As a reset input RST, a logic level of one of the first reset signals R1 is determined, and a first reset signal R1 is output. Similarly, the external reset signal generating unit 2600 includes a D-type flip-flop that receives the delayed reset signal EN as a data input D and receives the external clock signal EXT_CLK as a clock input CLK. A logic level of one of the second reset signals R2 is determined, and a second reset signal R2 is output. 4 is a circuit diagram of the command signal detection list 3 2 0 0 of the comparison control unit 3000 shown in FIG. 2. 114686.doc -10- 1316720 The command signal detecting unit 3200 includes a rising edge detecting unit 3220 and a falling edge detecting unit 3240. The rising edge detecting unit 3220 detects one rising edge of the ODT command signal 〇DT_CMD to trigger the first detecting signal P1 in a dual state. The falling edge detecting unit 3240 detects that one of the falling edges of the inverted ODT command signal triggers the second detecting signal P2 in a binary state. The rising edge detecting unit 3220 includes a first delay unit 3222, a first NAND gate NAND1, and a first inverter INV1. The first delay unit 3222 delays the ODT command signal 〇DT_CMD by one clock period of the external clock signal • EXT_CLK. The first NAND gate NAND1 performs an NAND operation of an ODT command signal ODT_CMD and an output signal of one of the first delay units 3222. The first inverter INV1 inverts an output signal of one of the first NAND gates NAND1 to output a first detection signal P1. The falling edge detecting unit 3240 includes a second inverter INV2 and a third inverter INV3, a second delay unit 3242, and a second NAND gate NAND2. The second inverter INV2 reverses the ODT command signal 〇DT_CMD. The second delay unit 3242 delays one of the output signals of the second inverter INV2 by one clock period of the external clock signal EXT_CLK, and the second NAND gate NAND2 performs an output of one of the ODT command signals ODT_CMD and the second delay unit 3242. The NAND operation of the signal. The third inverter INV3 inverts an output signal of one of the second NAND gates NAND2 to output a second detection signal P2. The first delay unit 3222 and the second delay unit 3242 may include a plurality of inverters connected in series, Thereby, the received signal is inverted and output. Figure 5 is a circuit diagram of the code comparison unit 34 〇〇 114686.doc • 11-1336720 of the comparison control unit 3 shown in Fig. 2. The code comparison unit 3400 includes a first comparison unit 3420 and a second comparison unit 3440. The first comparing unit 3420 compares the outer code EX_CODE and the DLL code DLL_CODE based on the first detection signal pi, and determines whether the two-state triggering and the comparison signal c1. The second comparison unit 3440 compares the outer code EX_C0DE with the DLL code DLL_CODE based on the second detection signal P2, and determines whether the second comparison signal C2 is toggled. In the following, an operation of the code comparison unit 3400 is explained in detail with reference to FIG. First, the first comparison unit 3420 of the 'code comparison unit 3400 starts comparing the external code EX_CODE with the DLL code DLL_CODE when the first detection signal P1 is changed, and when the external code EX C0DE is substantially the same as the DLL code DLL_CODE The state triggers the first comparison signal c 1 . Next, the second comparison unit 3440 of the code comparison unit 3400 starts comparing the external code EX_CODE with the DLL code DLL_CODE when the second detection signal P2 is changed, and when the external code EX_CODE is substantially the same as the DLL code DLL_CODE The state triggers the second comparison signal C2. That is, the code comparison unit 3400 toggles the first comparison signal C1 in the rising edge above the ODT command signal 〇 DT_CMD, and toggles the second comparison signal 双 2 in the falling edge of the 〇 DT command signal ODT_CMD. The first comparison unit 3420 includes a first storage unit 3422 and a first logic unit 3424. The first storage unit 3422 stores the external code EX_CODE in response to the first detection signal P1. The first logic unit 3424 compares the stored code in the bucket 22 of the first storage unit 3 with the DLL code DLL_CODE, 114686.doc -12-1316720 and determines whether the first comparison signal ci is toggled. The first storage unit 3422 includes a plurality of first registers, which are capable of storing one bit' and sequentially storing the external code EX CODE in units of one bit. The first logic unit 3424 includes a plurality of first mutually exclusive or (x〇r) gates and a third NAND gate NAND3. Each first XOR gate performs an X0R operation on a corresponding one of the DLL code DLL_CODE and one of the corresponding ones stored in the plurality of first registers. The third NAND gate NAND3 performs a NAND operation of the output signals of the plurality of first X0R gates and outputs a first comparison signal C1. The second comparison unit 3440 includes a second storage unit 3442 and a second logic unit 3444. The second storage unit 3442 stores the external code EX_C0DE in response to the second detection signal P2. The second logic unit 3444 compares the stored code in the second storage unit 3442 with the DLL code DLL_COMDE and determines whether the second comparison signal C2 is toggled. The second storage unit 3442 includes a plurality of second registers capable of storing one bit, thereby sequentially storing the external code EX_C0DE in units of one bit. The second logic unit 3444 includes a plurality of second mutually exclusive (XOR) gates and a fourth NAND gate NAND4. Each of the second X0R gates performs an X0R operation of a corresponding one of the DLL code DLL_CODE and one of the corresponding ones stored in the plurality of second registers. The fourth NAND gate NAND4 performs a NAND operation of the output signals of the plurality of second X0R gates and outputs a second comparison signal C2. 114686.doc • 13· 1316720 FIG. 6 is a circuit diagram of the enable signal generating unit 3600 of the comparison control unit 3000 shown in FIG. 2. The enable signal generating unit 3600 includes a sync unit 3620, a rising drive unit 3640, a down drive unit 3 660, and a latch unit 3680. Synchronization unit 3620 synchronizes ODT enable signal ODTEN with DLL clock signal DLL_CLK. The rising drive unit 3640 outputs the power supply voltage VDD as the ODT enable signal ODTEN »down in response to the first comparison signal C1. The drive unit 3660 outputs a ground voltage VSS as the ODT enable signal ODTEN in response to the second comparison signal C2. The latch unit 3680 prevents the ODT enable signal ODTEN from floating. In detail, the synchronization unit 3620 includes a fourth inverter INV4, a first PMOS transistor PM1, and a first NMOS transistor NM1. The fourth inverter INV4 inverts the DLL clock signal DLL_CLK to output. An inverted DLL clock signal. The first PMOS transistor PM1 has a gate that receives the inverted DLL clock signal and a source-drain path between the supply voltage (VDD) terminal and a first node NODE1. The first NMOS transistor NM1 has a gate receiving a DLL clock signal DLL_CLK and a source-drain path between a ground voltage (VSS) terminal and a second node NODE2. Therefore, when the ODT enable signal ODT_EN is activated by a logic level from "low" to "high", the synchronization unit 3620 turns on the first PMOS transistor PM1 and the first NMOS transistor NM1; The logic level of the "low" to "high" is turned off when the ODT enable signal ODT_EN is deactivated. The rising drive unit 3640 includes a fifth inverter INV5 and a second PMOS transistor PM2. The phase comparator INV5 has a first comparison signal C1 inverted 114686.doc -14-1316720 phase second PMOS transistor PM2 having a gate receiving an output signal of one of the fifth inverters INV5 and a first node NODE1 and one The source-drain path between the third node N0DE3. Therefore, the rising drive unit 3640 starts the 0DT enable signal 0DTEN with a "high" logic level in response to the first comparison signal C1. The drop drive unit 3660 includes a second NMOS transistor NM2. The second NMOS transistor NM2 has a gate receiving the second comparison signal C2 and a source-drain path between the second node NODE2 and the third node NDDE3. Therefore, the falling drive unit 3660 cancels the 0DT enable signal 0DTEN with a "low" logic level in response to the second comparison signal C2. The latch unit 3680 includes a sixth inverter INV6 and a seventh inverter. INV7 and an inverter latch of an eighth inverter INV8. The sixth inverter INV6 inverts a signal at the third node NODE3, and the seventh inverter INV7 receives and inverts the sixth inverted phase One of the outputs INV6 outputs a signal to output the inverted signal to the sixth inverter INV6. The eighth inverter INV8 inverts the output signal of the sixth inverter INV6 to output the ODT enable signal ODTEN. Describe that the 0DT enable signal ODTEN is enabled when the first comparison signal C1 is toggled; and the ODT enable signal ODTEN is revoked when the second comparison signal C2 is toggled. That is, embodiments of the present invention are based on the external clock signal EXT_CLK and The number of toggles of the DLL clock signal DLL_CLK determines the start timing of the ODT enable signal ODTEN. Therefore, even if the external clock signal EXT_CLK and the DLL clock signal DLL_CLK operate at a high frequency, it is possible to prevent The desired timing ODT enable signal 114686.doc •15· 1316720 ODTEN. In addition, 'a user can set the start timing of the 0DT enable signal 0DTEN after starting the 〇DT command signal 〇DT_CMD based on an initial setting. FIG. 7 is a diagram showing the start of the 0DT enable signal OFDM according to the present invention. Waveform diagram of the 〇DT control method. First, in a resetting step, the DLL reset signal generating unit 2200 activates the first reset signal R1' in response to the external reset signal RESET and the external reset signal generating unit 2600 is Molding a delay time between the DLL clock signal DLL_CLK and the external clock signal EXT_CLK. • After determining the predetermined time, the second reset signal R2 is started (see 1). Second, in a DLL clock counting step, The DLL clock counter 1400 starts counting the number of toggle triggers of the DLL clock signal DLL_CLK from a preset value (ie, 0) in response to the first reset signal R1 and outputs the number of toggles as the DLL code DLL. CODE (see 2). Third, in an external clock counting step, the external clock counter 1200 starts to count from the preset value (ie, 5) in response to the second reset signal R2. The number of toggles of the pulse signal EXT_CLK is two, and the number of toggles is output as the external code EX_CODE (see 3). Fourth, in a comparison step, the code comparison unit 3400 compares the external code EX_CODE with the DLL in response to the ODT command signal ODT_CMD. The code DLL_CODE (see 4)' and the enable signal generation unit 3600 determines a logical level of one of the ODT enable signals ODTEN in response to the result of the handover (see 5).
詳言之，碼比較單元3400當轉變ODT命令信號 ODT_CMD時將外部碼EX_CODE儲存於暫存器處，且接著 當儲存碼與DLL碼DLL_CODE大體上相同時雙態觸發〇DT 114686.doc •16- 1316720 啟用信號ODTEN。 在比較步驟中，ODT啟用信號ODTEN與ODT命令信號 ODT一CMD之上升邊緣同步而轉變為一"高"邏輯位準，且 與ODT命令信號〇DT_CMD之下降邊緣同步而轉變為一"低" 邏輯位準。 如上文所描述’本發明之晶粒内建終端電阻（〇DT)控制 裝置基於外部時脈信號及DLL時脈信號之雙態觸發數目來 確疋ODT啟用k號之啟動時序。因此，即使外部時脈信號 及DLL時脈彳έ號在一高頻率下運作，亦可能防止以非所要 之時序啟動ODT啟用信號。另外，使用者可基於一初始設 定而在啟動ODT命令信號之後設定〇DT啟用信號之啟動時 序。 本申請案含有與2005年9月29曰及2006年5月30曰在韓國 專利局申請之韓國專利申請案第2005-90953號及第2006-49027號有關的主題，其全部内容以引用的方式倂入本文 中。 雖然已關於特定實施例描述了本發8月，但熟習此項技術 者將易瞭解，在不脫離如下文之申請專利範圍中所界定的 本發明之精神及範疇的情況下，可進行各種改變及修改。 【圖式簡單說明】 圖1A為展示在一低頻率運作下之習知晶粒内建終端電阻 (ODT)控制方法的波形圖； 圖1B為展示在-高頻率運作下之習知〇dt控制方法的波 形圖； 114686.doc •17· 1316720 圖2為根據本發明之一實施例之〇Dt控制電路的方塊 圖； 圖3為圊2中所示之〇DT控制電路之重設信號產生單元的 電路圖； 圖4為圖2中所示之比較控制單元之命令信號偵測單元的 電路圖； 圖5為圖2中所示之比較控制單元之碼比較單元的電路 圖； 圖6為圖2中所示之比較控制單元之啟用信號產生單元的 電路圖；及 圖7為展示根據本發明之〇DT控制方法的波形圖。 【主要元件符號說明】 1000 1200 1400 2000 2200 2400 2600 3000 3200 3220 3222 3240 計算單元 外部時脈計數器 DLL時脈計數器 重設信號產生單元 DLL重設信號產生單元 延遲複本模型單元 外部重設信號產生單元 比較控制單元 命令信號偵測單元 上升邊緣偵測單元 第一延遲單元 下降邊緣偵測單元 114686.doc 1316720 3242 第二延遲單元 3400 碼比較單元 3420 第一比較單元 3422 第一儲存單元 3424 第一邏輯單元 3440 第二比較單元 3442 第二儲存單元 3444 第二邏輯單元 3600 啟用信號產生單元 3620 同步單元 3640 上升驅動單元 3660 下降驅動單元 3680 鎖存器單元 IN VI 第一反相器 INV2 第二反相器 INV3 第三反相器 INV4 第四反相器 INV5 第五反相器 INV6 第六反相器 INV7 第七反相器 INV8 第八反相器 NANDI 第一反及（NAND)閘 NAND2 第二NAND閘 NAND3 第三NAND閘 114686.doc -19- 1316720 NAND4 第四NAND閘 NM1 第一 NMOS電晶體 NM2 第二NMOS電晶體 NODE1 第一節點 NODE2 第二節點 NODE3 第三節點 PM1 第一 PMOS電晶體 PM2 第二PM0S電晶體 114686.doc •20-In detail, the code comparison unit 3400 stores the outer code EX_CODE at the temporary register when the ODT command signal ODT_CMD is converted, and then triggers the 〇DT 114686.doc •16- when the storage code is substantially the same as the DLL code DLL_CODE. 1316720 Enable signal ODTEN. In the comparing step, the ODT enable signal ODTEN is converted to a "high" logic level in synchronization with the rising edge of the ODT command signal ODT-CMD, and is converted to a " in synchronization with the falling edge of the ODT command signal 〇DT_CMD. Low " logic level. As described above, the die built-in terminating resistor (〇DT) control device of the present invention determines the start timing of the ODT enable k based on the number of toggles of the external clock signal and the DLL clock signal. Therefore, even if the external clock signal and the DLL clock signal operate at a high frequency, it is possible to prevent the ODT enable signal from being started at an undesired timing. In addition, the user can set the start timing of the DT enable signal after the ODT command signal is activated based on an initial setting. The present application contains the subject matter related to Korean Patent Application No. 2005-90953 and No. 2006-49027, filed on Sep. 29, 2005, and May 30, 2006, in the Korean Patent Office, the entire contents of which are incorporated by reference. Break into this article. Although the present invention has been described in connection with the specific embodiments, it will be apparent to those skilled in the art that various changes can be made without departing from the spirit and scope of the invention as defined in the following claims. And modify. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a waveform diagram showing a conventional grain built-in terminating resistance (ODT) control method under a low frequency operation; FIG. 1B is a conventional 〇dt control method showing a high frequency operation. Waveform diagram; 114686.doc • 17· 1316720 FIG. 2 is a block diagram of a 〇Dt control circuit according to an embodiment of the present invention; FIG. 3 is a circuit diagram of a reset signal generation unit of the 〇DT control circuit shown in FIG. Figure 4 is a circuit diagram of the command signal detecting unit of the comparison control unit shown in Figure 2; Figure 5 is a circuit diagram of the code comparison unit of the comparison control unit shown in Figure 2; Figure 6 is the circuit shown in Figure 2. A circuit diagram of the enable signal generating unit of the comparison control unit; and FIG. 7 is a waveform diagram showing the DT control method according to the present invention. [Main component symbol description] 1000 1200 1400 2000 2200 2400 2600 3000 3200 3220 3222 3240 Calculation unit external clock counter DLL clock counter reset signal generation unit DLL reset signal generation unit delay replica model unit external reset signal generation unit comparison Control unit command signal detection unit rising edge detection unit first delay unit falling edge detection unit 114686.doc 1316720 3242 second delay unit 3400 code comparison unit 3420 first comparison unit 3422 first storage unit 3424 first logic unit 3440 Second comparison unit 3442 Second storage unit 3444 Second logic unit 3600 Enable signal generation unit 3620 Synchronization unit 3640 Upward drive unit 3660 Drop drive unit 3680 Latch unit IN VI First inverter INV2 Second inverter INV3 Three inverter INV4 Fourth inverter INV5 Fifth inverter INV6 Sixth inverter INV7 Seventh inverter INV8 Eight inverter NANDI First NAND gate NAND2 Second NAND gate NAND3 Three NAND gate 114686.doc -19- 1316720 NAND4 fourth NAND gate NM1 first NMOS transistor NM2 second NMOS transistor NODE1 first node NODE2 second node NODE3 third node PM1 first PMOS transistor PM2 second PM0S transistor 114686.doc •20-