TW200721195A - Apparatus and method for controlling on die termination - Google Patents

Apparatus and method for controlling on die termination

Info

Publication number
TW200721195A
TW200721195A TW095136280A TW95136280A TW200721195A TW 200721195 A TW200721195 A TW 200721195A TW 095136280 A TW095136280 A TW 095136280A TW 95136280 A TW95136280 A TW 95136280A TW 200721195 A TW200721195 A TW 200721195A
Authority
TW
Taiwan
Prior art keywords
clock signal
controlling
odt
dll
die termination
Prior art date
Application number
TW095136280A
Other languages
Chinese (zh)
Other versions
TWI316720B (en
Inventor
Kyung-Hoon Kim
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200721195A publication Critical patent/TW200721195A/en
Application granted granted Critical
Publication of TWI316720B publication Critical patent/TWI316720B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Dram (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

An apparatus for controlling an on die termination (ODT) includes a counting unit for receiving an external clock signal and a delay locked loop (DLL) clock signal, and counting the toggle number of each of external clock signal and the DLL clock signal from a preset number; a comparing control unit for comparing the counted toggle number of the external clock signal with that of the DLL clock signal in response to an ODT command signal, and outputting an ODT enable signal for controlling the ODT based on the compared result.
TW095136280A 2005-09-29 2006-09-29 Apparatus and method for controlling on die termination TWI316720B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20050090953 2005-09-29
KR1020060049027A KR100761359B1 (en) 2005-09-29 2006-05-30 On-die termination control circuit and method

Publications (2)

Publication Number Publication Date
TW200721195A true TW200721195A (en) 2007-06-01
TWI316720B TWI316720B (en) 2009-11-01

Family

ID=37959477

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095136280A TWI316720B (en) 2005-09-29 2006-09-29 Apparatus and method for controlling on die termination

Country Status (3)

Country Link
KR (1) KR100761359B1 (en)
CN (1) CN1941629B (en)
TW (1) TWI316720B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100929846B1 (en) 2007-10-23 2009-12-04 주식회사 하이닉스반도체 On Die Termination Control Circuit
KR100921832B1 (en) * 2008-03-03 2009-10-16 주식회사 하이닉스반도체 On Die Termination controlling circuit of semiconductor memory device
KR100929833B1 (en) 2008-04-02 2009-12-07 주식회사 하이닉스반도체 Output Enable Signal Generation Circuit and Generation Method
KR100949276B1 (en) * 2008-09-08 2010-03-25 주식회사 하이닉스반도체 Termination tuning circuit and semiconductor memory device including the same
KR101043722B1 (en) 2010-02-04 2011-06-27 주식회사 하이닉스반도체 Latency control circuit and semiconductor memory device including the same
US10153014B1 (en) * 2017-08-17 2018-12-11 Micron Technology, Inc. DQS-offset and read-RTT-disable edge control
CN113808634B (en) * 2020-06-11 2024-02-27 华邦电子股份有限公司 Delay phase-locked loop device and updating method thereof
CN115599196A (en) * 2021-07-09 2023-01-13 长鑫存储技术有限公司（Cn） Enable control circuit and semiconductor memory

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100468728B1 (en) * 2002-04-19 2005-01-29 삼성전자주식회사 On-chip terminator, Control circuit there-of and Control method there-of in semiconductor integrated circuit
KR100502408B1 (en) * 2002-06-21 2005-07-19 삼성전자주식회사 Memory system for controlling power-up sequence of memory device embedding active termination and the method of power-up and initialization thereof
KR100464437B1 (en) * 2002-11-20 2004-12-31 삼성전자주식회사 On-Die Termination circuit and method for reducing on-chip DC current and memory system including memory device having the same
KR100506976B1 (en) * 2003-01-03 2005-08-09 삼성전자주식회사 synchronous semiconductor memory device having on die termination circuit
KR100528164B1 (en) * 2004-02-13 2005-11-15 주식회사 하이닉스반도체 On die termination mode transfer circuit in semiconductor memory device and its method
KR100670674B1 (en) * 2005-06-30 2007-01-17 주식회사 하이닉스반도체 Semiconductor memory deivce

Also Published As

Publication number Publication date
TWI316720B (en) 2009-11-01
CN1941629B (en) 2010-05-12
KR20070036635A (en) 2007-04-03
KR100761359B1 (en) 2007-09-27
CN1941629A (en) 2007-04-04

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees