CN108089631B - Clock detection circuit for micro-controller chip - Google Patents
Clock detection circuit for micro-controller chip Download PDFInfo
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- CN108089631B CN108089631B CN201711310686.4A CN201711310686A CN108089631B CN 108089631 B CN108089631 B CN 108089631B CN 201711310686 A CN201711310686 A CN 201711310686A CN 108089631 B CN108089631 B CN 108089631B
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- 238000001514 detection method Methods 0.000 title claims abstract description 66
- 239000013078 crystal Substances 0.000 claims abstract description 17
- 239000000872 buffer Substances 0.000 claims description 18
- 230000002159 abnormal effect Effects 0.000 claims description 17
- 230000001360 synchronised effect Effects 0.000 claims description 16
- 230000010355 oscillation Effects 0.000 claims description 9
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
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Abstract
The invention discloses a clock detection circuit for a microcontroller chip, which comprises the microcontroller chip and a crystal oscillator, wherein the crystal oscillator is connected to the outside of the microcontroller chip, the microcontroller comprises a clock detection module, an internal clock module, a clock selection module and a microcontroller core, the clock detection module is respectively connected with the crystal oscillator, the clock selection module and the microcontroller core, and the clock selection module is also respectively connected with the internal clock module and the microcontroller core. The invention adopts a simpler structure, and the internal clock adopted by the clock detection circuit can be a clock circuit with lower frequency, so that the corresponding protection function of the microcontroller chip can be realized only at the cost of lower power consumption.
Description
Technical Field
The present invention relates to a clock detection circuit, and more particularly, to a clock detection circuit for a micro-controller chip.
Background
Microcontroller chips are widely used in electronic products as control units within electronic circuits. After application development is performed by an application developer of the microcontroller chip aiming at a specific application field and a developed program is burnt into a program memory in the microcontroller chip, the microcontroller is endowed with different functions and can be applied to various application fields. The application occasions of the micro-controller chip are various, and the application conditions are different. Further improvement of the reliability of a microcontroller chip in various application conditions has been an important consideration in the development of microcontroller chips. Particularly, when the micro-controller chip needs to be used in application occasions with relatively severe application conditions, the development stage needs to pay more attention to improving the reliability of the micro-controller chip and take necessary detection means as much as possible, so that the micro-controller chip can detect that the working conditions have certain abnormal states and actively start necessary self-protection mechanisms when the micro-controller chip is applied to the work of the presence application system, so that the application system is prevented from serious presence application abnormality.
One type of anomaly that requires care when the microcontroller chip is in a field application is an anomaly in the external clock of the microcontroller. If the external clock is abnormal to stop oscillation, the microcontroller core may be in a deadlock state due to the loss of the working master clock, so that the microcontroller application system is seriously abnormal in field application. The invention provides a clock detection circuit suitable for a microcontroller chip, which can detect abnormal states such as stopping oscillation of an external clock of the microcontroller chip through the clock detection circuit in the microcontroller chip, and can timely switch a working master clock of a microcontroller core from the external clock to an internal clock when the external clock is abnormal, thereby avoiding deadlock state of the microcontroller core caused by abnormal stopping oscillation of the external clock and further causing serious consequences of an application system.
Disclosure of Invention
The present invention is directed to a clock detection circuit for a micro-controller chip, which solves the above-mentioned problems.
In order to achieve the above purpose, the present invention provides the following technical solutions:
the clock detection circuit comprises a microcontroller chip and a crystal oscillator, wherein the crystal oscillator is connected to the outside of the microcontroller chip, the microcontroller comprises a clock detection module, an internal clock module, a clock selection module and a microcontroller core, the clock detection module is respectively connected with the crystal oscillator, the clock selection module and the microcontroller core, and the clock selection module is also respectively connected with the internal clock module and the microcontroller core.
As a preferred embodiment of the present invention: the clock detection module comprises a clock counter, a synchronous buffer, a buffer II, a comparator C1, a synchronous count value B1 and a register, wherein the clock counter is connected with the synchronous buffer, the synchronous buffer is also respectively connected with the input end of the buffer II and one input end of the comparator C1, the other input end of the comparator C1 is connected with the output end of the buffer II, the output end of the comparator C1 is connected with the synchronous count value B1, and the synchronous count value B1 is also connected with the register.
Compared with the prior art, the invention has the beneficial effects that: according to the invention, the abnormal states such as stopping oscillation and the like of the external clock of the microcontroller chip can be detected by the clock detection circuit in the microcontroller chip, and the working master clock of the microcontroller core can be timely switched from the external clock to the internal clock when the external clock is abnormal, so that the condition that the microcontroller core is in a deadlock state due to the abnormal stopping oscillation of the external clock is avoided, and further, the serious on-site application abnormality of an application system is caused. In addition, the clock detection circuit can generate a corresponding interrupt request signal when abnormality occurs, so that the microcontroller kernel can timely start a corresponding interrupt protection program, and the reliability of the microcontroller chip in-situ application is further improved. Finally, the invention also has the advantage of low power consumption. The invention adopts a simpler structure, and the internal clock adopted by the clock detection circuit can be a clock circuit with lower frequency, so that the corresponding protection function of the microcontroller chip can be realized only at the cost of lower power consumption.
Drawings
Fig. 1 is a functional block diagram of a clock detection scheme of a microcontroller chip.
Fig. 2 is a schematic diagram of the clock detection module.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1 and 2, a clock detection circuit for a micro-controller chip is composed of a clock detection module (ck_det), an internal clock module (int_osc), a clock selection module (ck_sel), and a micro-controller CORE (CORE). When the micro-controller chip is in the field application, its core works as a main clock by a crystal oscillator outside the chip
(EXT_OSC) is provided. The clock (eck) output by the crystal oscillator (ext_osc) outside the chip is input to the clock detection module (ck_det) inside the microcontroller chip, which is responsible for detecting the external clock (eck). The clock detection module is a dual-clock logic module, that is, the clock detection module needs to use an external clock (eck) generated by the external clock module and an internal clock (ick) generated by the internal clock module at the same time when working. The clock detection alarm signal (invld_rpt) output by the clock detection module is connected to the clock selection module (ck_sel). When the clock detection module (CK_DET) detects that the crystal oscillator outside the chip is in a normal state, the clock detection alarm signal (invld_rpt) is set to be in a low level state. When the clock detection module (CK_DET) detects that the crystal oscillator outside the chip has abnormal state of stopping oscillation, the clock detection alarm signal (invld_rpt) is set to be in an active high state. The clock detection alarm signal (invld_rpt) output by the clock detection module is connected to the clock selection module (ck_sel). The clock selection module (ck_sel) is responsible for selecting the normal external clock (eck) as the core operation clock or the internal clock (ick) as the core operation clock (clk_core) according to different states of the clock detection alarm signal (invld_rpt). The clock selection module (CK_SEL) continuously monitors the clock detection alarm signal (invld_rpt) sent by the clock detection module (CK_DET), and when the clock detection alarm signal is monitored to be in a low level state, the clock selection module (CK_SEL) selects a normal external clock (eck) as a kernel working clock (clk_core) to be sent to the microcontroller kernel (CORE); when it detects that the clock detection alarm signal is in a high level state, the clock selection module (ck_sel) immediately transmits the internal clock (ick) generated by the internal clock module as a CORE working clock (clk_core) to the microcontroller CORE (CORE). In addition, when the Zhong Zhen detection module (ck_det) detects that the crystal oscillator outside the chip has an abnormal state of stopping oscillation, it also generates an interrupt request signal (inr_req) to report the abnormality to the microcontroller core, and when the microcontroller core receives the interrupt request signal, it can enter a corresponding interrupt service routine after the working master clock finishes switching, and perform a series of clock abnormality protection operations to avoid the occurrence of a corresponding abnormality in the application system.
The internal operation principle of the clock detection module (ck_det) is shown in fig. 2. Inside the clock detection module (ck_det), the clock counter (ck_cnt) takes an external clock (eck) as its working clock, and the clock counter counts up by 1 at the rising edge of each eck. The count value (cnto) of the clock counter is supplied to a Synchronous Buffer (SBUF), and the operation clock of the Synchronous Buffer (SBUF) is an internal clock (ick). The clock frequency of the internal clock (ick) output is much lower than the clock frequency of the external clock (ck). This is advantageous in saving power consumption of the microcontroller chip. The Synchronization Buffer (SBUF) continuously samples the count value (cnto) of the clock counter, and a synchronization count value 1 (cnto_s1) synchronized to the internal clock domain is obtained through the Synchronization Buffer (SBUF). The buffer 2 (BUF 2) simultaneously uses the internal clock as the operation clock, and the buffer 2 buffers the synchronization count value 1 (cnto_s1) to obtain the synchronization count value 2 (cnto_s2). The synchronization count value 1 (cnto_s1) and the synchronization count value 2 (cnto_s2) are sent to the comparator C1. In the case where the external clock is normal, the synchronization count value 1 (cnto_s1) is not equal to the synchronization count value 2 (cnto_s2), because the value of the synchronization count value 2 (cnto_s2) has a delay of 1 internal clock cycle with respect to the synchronization count value 1 (cnto_s1). When the external clock is normal, the value of the synchronization count value 2 (cnto_s2) is not equal to the value of the synchronization count value 1 (cnto_s1), which drives the comparison signal (cmps) output by the comparator C1 to be in a low state, and drives the clock detection alarm signal (invld_rpt) output by the register DFF1 to be in a low invalid state. When the external clock is abnormal in stopping oscillation, the value of the synchronous count value 2 (cnto_s2) is equal to the value of the synchronous count value 1 (cnto_s1), which drives the comparison signal (cmps) output by the comparator C1 to be in a high state, and drives the clock detection alarm signal (invld_rpt) output by the register DFF1 to be in an active high state.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (1)
1. A clock detection circuit for a micro-controller chip is characterized by comprising a clock detection module (CK_DET), an internal clock module (INT_OSC), a clock selection module (CK_SEL) and a micro-controller CORE (CORE), wherein when the micro-controller chip is in a field application, the CORE work master clock is provided by a crystal oscillator (EXT_OSC) outside the chip, the Clock (CK) output by the crystal oscillator (EXT_OSC) outside the chip is input to the clock detection module (CK_DET) inside the micro-controller chip, the clock detection module (CK_DET) is responsible for detecting an external clock (eck), the clock detection module is a dual-clock logic module, namely, the clock detection module is required to use the external clock (eck) generated by the external clock module and the internal clock (ick) generated by the internal clock module at the same time when working, a clock detection signal (invld_t) output by the clock detection module (CK_DET) is connected to the clock selection module (CK_DET), a clock detection signal (in which is output by the crystal oscillator (in a high state) is detected when the crystal oscillator (in a low state (rpp) of the chip), the clock detection module (CK_DET) is detected as an abnormal state when the crystal oscillator (rpp) is detected by the external clock detection module (37) and the clock detection module (in a normal state) is detected when the clock detection module (rpp) is in a low state, the clock detection alarm signal (invld_rpt) output by the clock detection module is connected to the clock selection module (CK_SEL), the clock selection module (CK_SEL) is responsible for selecting a normal external clock (eck) as a kernel working clock according to different states of the clock detection alarm signal (invld_rpt), or an internal clock (ick) is used as the kernel working clock (clk_core), the clock selection module (CK_SEL) continuously monitors the clock detection alarm signal (invld_rpt) sent by the clock detection module (CK_DET), and when the clock detection alarm signal is monitored to be in a low level state, the clock selection module (CK_SEL) selects the normal external clock (eck) as the kernel working clock (clk_core) to be transmitted to the microcontroller CORE (CORE); when the clock detection alarm signal is monitored to be in a high level state, the clock selection module (CK_SEL) immediately transmits an internal clock (ick) generated by the internal clock module as a kernel working clock (clk_core) to the microcontroller kernel (CORE), when the Zhong Zhen detection module (CK_DET) detects that an abnormal state of stopping oscillation occurs in a crystal oscillator outside the chip, the clock selection module also generates an interrupt request signal (inr_req) to report the abnormal state to the microcontroller kernel, and when the microcontroller kernel receives the interrupt request signal, the microcontroller kernel enters a corresponding interrupt service routine after the switching of a working master clock is completed, and a series of clock abnormal protection operations are performed so as to prevent the application system from generating corresponding abnormal states;
the clock detection module (CK_DET) comprises a clock counter, a synchronous buffer, a buffer II, a comparator C1, a synchronous count value B1 and a register, wherein the clock counter is connected with the synchronous buffer which is also respectively connected with the buffer
The input end of the second comparator and one input end of the comparator C1, the other input end of the comparator C1 is connected with the output end of the second buffer,
the output end of the comparator C1 is connected with a synchronous count value B1, and the synchronous count value B1 is also connected with a register.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711310686.4A CN108089631B (en) | 2017-12-11 | 2017-12-11 | Clock detection circuit for micro-controller chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201711310686.4A CN108089631B (en) | 2017-12-11 | 2017-12-11 | Clock detection circuit for micro-controller chip |
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| CN108089631A CN108089631A (en) | 2018-05-29 |
| CN108089631B true CN108089631B (en) | 2023-10-27 |
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| CN113805689A (en) * | 2020-06-12 | 2021-12-17 | 华为技术有限公司 | Processing system, processing method, signal generator, and signal generating method |
| CN112114616B (en) * | 2020-08-04 | 2022-10-25 | 深圳市宏电技术股份有限公司 | Switching method of real-time clock, electronic equipment and computer storage medium |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001044825A (en) * | 1999-07-28 | 2001-02-16 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit |
| CN104834581A (en) * | 2015-05-11 | 2015-08-12 | 江苏宏云技术有限公司 | Oscillation stop monitoring circuit of crystal oscillator |
| CN106066817A (en) * | 2016-05-30 | 2016-11-02 | 珠海市微半导体有限公司 | clock monitoring circuit and method thereof |
| CN106533399A (en) * | 2015-09-09 | 2017-03-22 | 想象技术有限公司 | Synchronising devices |
| CN207867388U (en) * | 2017-12-11 | 2018-09-14 | 深圳市博巨兴实业发展有限公司 | A kind of clock circuit for detecting for microcontroller chip |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4672194B2 (en) * | 2001-06-22 | 2011-04-20 | 富士通株式会社 | Receiver circuit |
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- 2017-12-11 CN CN201711310686.4A patent/CN108089631B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001044825A (en) * | 1999-07-28 | 2001-02-16 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit |
| CN104834581A (en) * | 2015-05-11 | 2015-08-12 | 江苏宏云技术有限公司 | Oscillation stop monitoring circuit of crystal oscillator |
| CN106533399A (en) * | 2015-09-09 | 2017-03-22 | 想象技术有限公司 | Synchronising devices |
| CN106066817A (en) * | 2016-05-30 | 2016-11-02 | 珠海市微半导体有限公司 | clock monitoring circuit and method thereof |
| CN207867388U (en) * | 2017-12-11 | 2018-09-14 | 深圳市博巨兴实业发展有限公司 | A kind of clock circuit for detecting for microcontroller chip |
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