CN108491286B

CN108491286B - MCU chip protection method

Info

Publication number: CN108491286B
Application number: CN201810038017.4A
Authority: CN
Inventors: 万上宏; 叶媲舟; 涂柏生
Original assignee: Shenzhen Bojuxing Microelectronics Technology Co ltd
Current assignee: Shenzhen Bojuxing Microelectronics Technology Co ltd
Priority date: 2018-01-16
Filing date: 2018-01-16
Publication date: 2023-04-11
Anticipated expiration: 2038-01-16
Also published as: CN108491286A

Abstract

The invention discloses a MCU chip protection method, which is characterized in that through a clock protection circuit in the MCU chip, when the chip is applied in the field, the clock protection circuit in the MCU chip can self-check the abnormal state of an application system, such as the stop oscillation of an external high-frequency clock, and timely switch a working main clock of an MCU kernel from the external high-frequency clock to an internal low-frequency clock, so that the MCU kernel is prevented from being in a deadlock state and serious system abnormality caused by the deadlock state. The clock protection circuit can also generate a corresponding interrupt request signal when an exception occurs, so that the MCU kernel can start a corresponding interrupt protection program in time, and the reliability of the MCU chip in-field application is further improved. The invention improves the reliability of the MCU chip, so that the MCU chip can be used in some application occasions with relatively severe electrical environments.

Description

MCU chip protection method

Technical Field

The invention relates to a protection method, in particular to a protection method of an MCU chip.

Background

MCU chips are widely used in electronic products as control units inside electronic circuits. MCU chip's application scenario is various, and application condition is also diverse. When the MCU chip needs to be used in some applications with relatively harsh electrical environments, it is very important to advance the reliability of the MCU chip. When the MCU chip is in a field application, one of the exceptions needing to be handled carefully is that an external high-frequency clock of the MCU is abnormal. If the external high-frequency clock has an abnormal oscillation stopping state, the MCU core may be in a deadlock state due to the loss of the working master clock, and further, the MCU application system has a serious abnormal field application. The invention provides a clock protection circuit for an MCU chip, which can self-check abnormal states of an application system, such as stop oscillation and the like of an external high-frequency clock when the chip is applied in the field, and timely switch a working main clock of an MCU kernel from the external high-frequency clock to an internal low-frequency clock, so that the MCU kernel is prevented from being in a deadlock state and serious system abnormality caused by the deadlock state. The clock protection circuit can also generate a corresponding interrupt request signal when an exception occurs, so that the MCU kernel can start a corresponding interrupt protection program in time, and the reliability of the MCU chip in-field application is further improved.

Disclosure of Invention

The present invention aims to provide a method for protecting an MCU chip to solve the problems set forth in the above background art.

In order to achieve the purpose, the invention provides the following technical scheme:

a MCU chip protection method, when the MCU chip is in the application of the scene, its kernel job master clock is offered by high-frequency oscillator HOSC outside the chip, the clock hck that the high-frequency oscillator HOSC outside the chip outputs is input to the clock monitoring protection module PRT _ MON inside the MCU chip, the clock monitoring protection module PRT _ MON is responsible for carrying on the self-checking to the external high-frequency clock hck, the clock protection starting signal PRT _ st that the clock monitoring protection module outputs is connected to clock management module CKM, when the clock monitoring protection module PRT _ MON detects the high-frequency oscillator outside the chip to be the normal condition, the clock protection starting signal PRT _ st will be set to the low level state, when the clock monitoring protection module PRT _ MON self-checks to the high-frequency oscillator outside the chip to appear the abnormal condition of stopping oscillation, the clock protection starting signal PRT _ st will be set to the high level valid condition, the clock protection starting signal PRT _ st that the clock monitoring protection module PRT _ MON outputs is connected to clock management module CKM; the clock management module CKM is responsible for selecting a normal external high-frequency clock hck as a CORE working clock according to different states of a clock protection starting signal PRT _ st, or taking an internal low-frequency clock lck as the CORE working clock clk _ MCU, continuously monitoring the clock protection starting signal PRT _ st sent by the clock monitoring protection module PRT _ MON, and when monitoring that the clock protection starting signal is in a low level state, selecting the normal external high-frequency clock hck as the CORE working clock clk _ MCU to be transmitted to the MCU CORE MCU _ CORE by the clock management module CKM; when monitoring that the clock protection starting signal is in a high level state, the clock management module CKM immediately transmits an internal low-frequency clock lck generated by the internal low-frequency clock module to an MCU (microprogrammed control Unit) kernel MCU _ CORE as a kernel working clock clk _ MCU; when the clock monitoring protection module PRT _ MON detects that the high-frequency oscillator outside the chip has an abnormal state of stopping oscillation, an interrupt request signal intr is also generated and reported to the MCU kernel, and when the MCU kernel receives the interrupt request signal, the MCU kernel can enter a corresponding interrupt service program after the work master clock finishes switching, and a series of clock abnormal protection operations are carried out.

As a further scheme of the invention: the clock monitoring protection module PRT _ MON is a double-clock logic module.

As a still further scheme of the invention: in the clock monitoring protection module PRT _ MON, the clock monitoring counter DCNT uses the external high frequency clock hck as its working clock, every rising edge of hck, the clock monitoring counter adds 1 and accumulates, the clock monitoring protection module PRT _ MON includes 3 buffers using the internal low frequency clock lck as the working clock, which are buffer 1BUF1, buffer 2BUF2, buffer 3BUF3,3 buffers are connected in series, the counting value cnt _ p0 of the clock monitoring counter is transmitted to buffer 1BUF1, buffer 1BUF1 continuously samples the counting value cnto the clock monitoring counter, buffer 1BUF1 outputs the sampling value cnt _ p1 of the clock monitoring counter, buffer 2BUF2 uses the internal low frequency clock as the working clock at the same time, buffer 2BUF2 buffers the sampling value cnt _ p1 of the clock monitoring counter output by buffer 1 to obtain the sampling value cnt _ p2 of the clock monitoring counter, the buffer 3BUF3 buffers the clock monitor counter sample value cnt _ p2 outputted from the buffer 2 to obtain a clock monitor counter sample value cnt _ p3, the clock monitor counter sample value cnt _ p2 outputted from the buffer 2 and the clock monitor counter sample value cnt _ p3 outputted from the buffer 3 are sent to the input terminal of the comparator C1, under the condition that the external high frequency clock is normal, the clock monitor counter sample value cnt _ p2 is not equal to the clock monitor counter sample value cnt _ p3, because the value of the clock monitor counter sample value cnt _ p3 has a delay of 1 internal low frequency clock period relative to the clock monitor counter sample value cnt _ p2, when the external high frequency clock is normal, the value of the clock monitor counter sample value cnt _ p3 is not equal to the value of the clock monitor counter sample value cnt _ p2, which will drive the comparison signal outputted from the comparator C1 to be in a low level state, and the clock protection enable signal prt _ st output by the latch LAT1 is driven to be set to a low-level inactive state, when the external high-frequency clock has a shutdown anomaly, the value of the clock monitor counter sampled value cnt _ p3 is equal to the value of the clock monitor counter sampled value cnt _ p2, which drives the comparison signal output by the comparator C1 to be a high-level state, and drives the clock protection enable signal prt _ st output by the latch LAT1 to be set to be a high-level active state.

Compared with the prior art, the method has the advantages that, the beneficial effects of the invention are: according to the invention, through the clock protection circuit in the MCU chip, when the chip is applied in the field, the clock protection circuit in the MCU chip can self-check that the application system has abnormal states such as oscillation stop and the like due to the external high-frequency clock, and timely switch the working master clock of the MCU core from the external high-frequency clock to the internal low-frequency clock, so that the MCU core is prevented from having a deadlock state and serious system abnormality caused by the deadlock state. The clock protection circuit can also generate a corresponding interrupt request signal when an exception occurs, so that the MCU kernel can start a corresponding interrupt protection program in time, the reliability of field application of the MCU chip is further improved, and the MCU chip can be used in some application occasions with relatively severe electrical environments.

Drawings

Fig. 1 is a working principle block diagram of the MCU chip protection method.

Fig. 2 is a working schematic diagram of a clock monitoring protection module in the MCU chip protection method.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1-2, in an embodiment of the present invention, in the case that an MCU chip is in a field application, if an external high-frequency clock is abnormal to stop oscillation, an MCU core may be in a deadlock state due to losing a working master clock, which may cause a serious field application abnormality of an MCU application system. The invention provides a clock protection circuit suitable for an MCU chip, which can self-check abnormal states such as oscillation stop and the like of an external high-frequency clock of the MCU chip through the clock protection circuit in the MCU chip, and can timely switch a working master clock of an MCU kernel from the external high-frequency clock into an internal low-frequency clock when the external high-frequency clock is abnormal, thereby avoiding the MCU kernel from generating a deadlock state due to the oscillation stop abnormality of the external high-frequency clock and further avoiding serious consequences of an application system.

The clock protection circuit principle for the MCU chip is shown in fig. 1. The MCU chip comprises a clock monitoring protection module PRT _ MON, an internal low-frequency clock module LPOSC, a clock management module CKM, an MCU CORE MCU _ CORE and the like. When the MCU chip is in a field application, its core operating master clock is provided by a high frequency oscillator HOSC external to the chip. The clock hck output by the high-frequency oscillator HOSC outside the chip is input to the clock monitoring protection module PRT _ MON inside the MCU chip, and the clock monitoring protection module PRT _ MON is responsible for self-checking the external high-frequency clock hck. The clock monitoring protection module is a double-clock logic module, namely an external high-frequency clock hck generated by an external high-frequency clock module and an internal low-frequency clock lck generated by an internal low-frequency clock module are required to be used simultaneously when the clock monitoring protection module works. The clock protection start signal prt _ st output by the clock monitoring protection module is connected to the clock management module CKM. When the clock monitoring protection module PRT _ MON detects that the high-frequency oscillator outside the chip is in a normal state, the clock protection start signal PRT _ st is set to a low level state. When the clock monitoring protection module PRT _ MON detects the abnormal state of stopping oscillation of the high-frequency oscillator outside the chip, the clock protection start signal PRT _ st is set to be in an active high level state. The clock protection start signal prt _ st output by the clock monitoring protection module is connected to the clock management module CKM. The clock management module CKM is responsible for selecting the normal external high-frequency clock hck as the core working clock or the internal low-frequency clock lck as the core working clock clk _ mcu according to different states of the clock protection start signal prt _ st. The clock management module CKM continuously monitors a clock protection starting signal PRT _ st sent by the clock monitoring protection module PRT _ MON, and when the clock management module CKM monitors that the clock protection starting signal is in a low level state, the clock management module CKM selects a normal external high-frequency clock hck as a CORE working clock clk _ MCU and transmits the clock to the MCU CORE MCU _ CORE; when monitoring that the clock protection starting signal is in a high level state, the clock management module CKM immediately transmits the internal low-frequency clock lck generated by the internal low-frequency clock module to the MCU CORE MCU _ CORE as the CORE working clock clk _ MCU. In addition, when the clock monitoring protection module PRT _ MON self-detects that the high-frequency oscillator outside the chip has an abnormal state of stopping oscillation, it will also generate an interrupt request signal intr, report the abnormality to the MCU core, and when the MCU core receives the interrupt request signal, the MCU core can enter the corresponding interrupt service program after the switching of the working master clock is completed, and perform a series of clock abnormality protection operations to avoid the occurrence of corresponding abnormality in the application system.

The internal operation of the clock monitoring protection module PRT _ MON is shown in fig. 2. In the clock monitoring protection module PRT _ MON, the clock monitoring counter DCNT uses the external high-frequency clock hck as its working clock, and the clock monitoring counter increments by 1 for each rising edge of hck. The clock monitoring protection module PRT _ MON includes 3 buffers with internal low frequency clock lck as working clock, which are buffer 1BUF1, buffer 2BUF2, and buffer 3BUF3, respectively. The 3 buffers are connected in a serial manner. The count value cnt _ p0 of the clock monitor counter is supplied to the buffer 1BUF1. The buffer 1BUF1 continuously samples the count value cnto of the clock monitor counter, and the buffer 1BUF1 outputs a clock monitor counter sample value cnt _ p1. The buffer 2BUF2 simultaneously uses an internal low-frequency clock as a working clock, and the buffer 2BUF2 buffers the clock monitoring counter sample value cnt _ p1 output by the buffer 1 to obtain the clock monitoring counter sample value cnt _ p2. The buffer 3BUF3 buffers the clock monitor counter sample value cnt _ p2 output by the buffer 2 to obtain a clock monitor counter sample value cnt _ p3. The sampled values cnt _ p2 of the clock monitor counter output from the buffer 2 and cnt _ p3 of the clock monitor counter output from the buffer 3 are supplied to the input terminal of the comparator C1. In the case of a normal external high frequency clock, the clock monitor counter sample value cnt _ p2 is not equal to the clock monitor counter sample value cnt _ p3 because the value of the clock monitor counter sample value cnt _ p3 is delayed by 1 internal low frequency clock cycle with respect to the clock monitor counter sample value cnt _ p2. When the external high frequency clock is normal, the value of the clock monitor counter sample value cnt _ p3 is not equal to the value of the clock monitor counter sample value cnt _ p2, which will drive the comparison signal output by the comparator C1 to be in a low state and drive the clock protection start signal prt _ st output by the latch LAT1 to be in a low inactive state. When the external high frequency clock has a shutdown anomaly, the value of the sampling value cnt _ p3 of the clock monitor counter is equal to the value of the sampling value cnt _ p2 of the clock monitor counter, which drives the comparison signal output by the comparator C1 to be in a high level state, and drives the clock protection start signal prt _ st output by the latch LAT1 to be in a high level active state.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. A MCU chip protection method is characterized in that when an MCU chip is in a field application, a kernel working master clock is provided by a high-frequency oscillator HOSC outside the chip, a clock hck output by the high-frequency oscillator HOSC outside the chip is input to a clock monitoring protection module PRT _ MON inside the MCU chip, the clock monitoring protection module PRT _ MON is responsible for self-checking an external high-frequency clock hck, a clock protection starting signal PRT _ st output by the clock monitoring protection module is connected to a clock management module CKM, when the clock monitoring protection module PRT _ MON detects that the high-frequency oscillator outside the chip is in a normal state, the clock protection starting signal PRT _ st is set to be in a low-level state, when the clock monitoring protection module PRT _ MON self-checks that the high-frequency oscillator outside the chip is in an abnormal state of stopping oscillation, the clock protection starting signal PRT _ st is set to be in a high-level effective state, and the clock protection starting signal PRT _ st output by the clock monitoring protection module PRT _ MON is connected to the clock management module CKM; the clock management module CKM is responsible for selecting a normal external high-frequency clock hck as a CORE working clock according to different states of a clock protection starting signal PRT _ st, or taking an internal low-frequency clock lck as the CORE working clock clk _ MCU, continuously monitoring the clock protection starting signal PRT _ st sent by the clock monitoring protection module PRT _ MON, and when monitoring that the clock protection starting signal is in a low level state, selecting the normal external high-frequency clock hck as the CORE working clock clk _ MCU to be transmitted to the MCU CORE MCU _ CORE by the clock management module CKM; when monitoring that the clock protection starting signal is in a high level state, the clock management module CKM immediately transmits an internal low-frequency clock lck generated by the internal low-frequency clock module to an MCU (microprogrammed control Unit) kernel MCU _ CORE as a kernel working clock clk _ MCU; when the clock monitoring protection module PRT _ MON detects that the high-frequency oscillator outside the chip has an abnormal state of stopping oscillation, an interrupt request signal intr is also generated and reported to the MCU kernel, and when the MCU kernel receives the interrupt request signal, the MCU kernel can enter a corresponding interrupt service program after the work master clock finishes switching, and a series of clock abnormal protection operations are carried out.

2. The MCU chip protection method according to claim 1, wherein the clock monitoring protection module PRT _ MON is a dual-clock logic module.

3. The MCU chip protection method according to claim 1, wherein inside the clock monitor protection module PRT _ MON, the clock monitor counter DCNT uses an external high frequency clock hck as its working clock, the clock monitor counter increments by 1 for each rising edge of hck, the clock monitor protection module PRT _ MON includes 3 buffers using an internal low frequency clock lck as its working clock, which are buffer 1BUF1, buffer 2BUF2, buffer 3BUF3,3 buffers connected in series, the count value cnt _ p0 of the clock monitor counter is transmitted to buffer 1BUF1, buffer 1BUF1 continuously samples the count value cnto the clock monitor counter, buffer 1BUF1 outputs the clock monitor counter sample value cnt _ p1, buffer 2BUF2 uses the internal low frequency clock as its working clock at the same time, the buffer 2BUF2 buffers the clock monitor counter sample value cnt _ p1 output by the buffer 1 to obtain a clock monitor counter sample value cnt _ p2, the buffer 3BUF3 buffers the clock monitor counter sample value cnt _ p2 output by the buffer 2 to obtain a clock monitor counter sample value cnt _ p3, the clock monitor counter sample value cnt _ p2 output by the buffer 2 and the clock monitor counter sample value cnt _ p3 output by the buffer 3 are sent to the input end of the comparator C1, under the condition of normal external high-frequency clock, the clock monitor counter sample value cnt _ p2 and the clock monitor counter sample value cnt _ p3 are not equal, because the value of the clock monitor counter sample value cnt _ p3 has a delay of 1 internal low-frequency clock period relative to the clock monitor counter sample value cnt _ p2, when the external high-frequency clock is normal, the value of the clock monitor counter sample value cnt _ p3 is not equal to the value of the clock monitor counter sample value cnt _ p2, this drives the comparison signal output by the comparator C1 to a low state and drives the clock protection enable signal prt _ st output by the latch LAT1 to a low inactive state, and when a stall anomaly occurs in the external high frequency clock, the value of the clock monitor counter sample value cnt _ p3 is equal to the value of the clock monitor counter sample value cnt _ p2, which drives the comparison signal output by the comparator C1 to a high state and drives the clock protection enable signal prt _ st output by the latch LAT1 to a high active state.