CN102811054A - Relaxation oscillator with low power consumption - Google Patents
Relaxation oscillator with low power consumption Download PDFInfo
- Publication number
- CN102811054A CN102811054A CN 201110143263 CN201110143263A CN102811054A CN 102811054 A CN102811054 A CN 102811054A CN 201110143263 CN201110143263 CN 201110143263 CN 201110143263 A CN201110143263 A CN 201110143263A CN 102811054 A CN102811054 A CN 102811054A
- Authority
- CN
- China
- Prior art keywords
- subordinate
- delay
- signal
- time
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Pulse Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a relaxation oscillator with low power consumption. In order to overcome the shortcomings of uncertain transmission delay, low precision of the oscillating frequency, and poor temperature stability in the relaxation oscillator, the invention provides a method of a feedback control; by detecting the output frequency of the relaxation oscillator or the change of a signal value when the charging period of a regular capacitor is ended, a negative feedback loop is structured to accurately control the delay of a comparator so as to replace the traditional method of reducing the delay by increasing the power consumption, therefore, the power consumption is reduced; and meanwhile, the precision of the oscillating frequency and the temperature stability are improved.
Description
Affiliated technical field:
The present invention relates to a kind of electronic circuit, relate to a kind of relaxation oscillator emphatically.
Prior art and background technology:
Low power design technique is most important for the radio sensing network that need not the frequent change battery.Because the data interaction between the wireless sensing node is rare, can in the very short time interval, accomplish, therefore can be through periodically waking sensing node up, and reach the purpose that reduces power consumption in the mode that is letting node get into resting state At All Other Times.Because average power consumption is proportional to and wakes up-relative scale of dormancy time, in order to reduce average power consumption, need dwindle the stand-by period of flower in clock synchronization and communication channel detection, this just is converted into the required precision of the clock (time reference) to each node.
Though active temperature compensated quartz crystal oscillator can reach the precision of several ppm, because its volume power consumption is bigger, cost is higher and be not suitable for the application of wireless sense network.Therefore, need on the sheet fully integrated, precision is higher relatively and oscillator that power consumption is lower as time reference.
Integrated LC oscillator can reach the precision of ppm more than 100 on the sheet, presents splendid temperature stability [1].Yet because their scheme needs the vibration of high frequency, so power consumption is usually in the magnitude of tens mW, and this is the power consumption budget of wireless sensing node head and shoulders above.Ring oscillator is operated in sub-threshold region can reach extremely low power dissipation (several uW), however precision only can be controlled at ± 5% [2].The power consumption and the ring oscillator of relaxation oscillator are similar, and precision is but better relatively, usually less than 1% [3], therefore use ideal to wireless sense network.
Fig. 1 is a kind of circuit theory diagrams of traditional relaxation oscillator [4], and it provides periodic oscillator signal through staggered the discharging and recharging to two timing capacitors 55,60.The complementary switch controlling signal of RS latch output, when making a timing capacitor charging, another timing capacitor discharge.Whether the signal 54,59 that comparator 15,20 detects on the timing capacitor surpasses timing reference signal 5,10, if surpass, the output of comparator makes the RS latch overturn, thus the state that two timing capacitors exchanges are discharged and recharged.Each node signal waveform is as shown in Figure 2.
Signal on timing capacitor arrive at timing reference signal the time be carved into the RS latch output change state, have transmission delay, as shown in Figure 2.This transmission delay is mainly determined by the time-delay of comparator; Receive the influence that technology, supply power voltage, temperature and input voltage change factors such as speed; Be difficult to accurately control; This makes signal value and preset timing reference 5 and 10 existence of the charge cycle finish time on timing capacitor 55 and 60 than big-difference, thereby causes the variation of frequency of oscillation.
In order to improve the frequency change that the transmission delay uncertainty causes; Traditional method is to improve the speed of comparator Digital Logical Circuits follow-up with it; Thereby dwindle the proportion that transmission delay accounts for the whole cycle; It is very big that but the shortcoming of this method is a power consumption, and power consumption has caused the impassable bottleneck of frequency accuracy along with dwindling of time-delay is exponential increase.
The purpose of invention: the objective of the invention is to overcome that transmission delay is uncertain in the relaxation oscillator, the frequency of oscillation precision is low, the shortcoming of temperature stability difference; Method with FEEDBACK CONTROL; The accurately time-delay of control comparator; Substituting increases the conventional method of power consumption to reduce to delay time, and when reducing power consumption, improves the precision and the temperature stability of frequency of oscillation.
The technical scheme of invention:
The object of the invention reaches through following measure:
Transmission delay is mainly determined by the time-delay of comparator.Because the signal value of the output frequency of relaxation oscillator and the charge cycle finish time on the timing capacitor is the function of transmission delay; Therefore can comparator design be the time-delay comparator with adjustable; The variation of output frequency through detecting relaxation oscillator and the signal value of the charge cycle finish time on the timing capacitor then, the structure negative feedback loop is regulated the time-delay of comparator automatically, thus the stable transfer time-delay; And then the output frequency of stable relaxation oscillator, as shown in Figure 3.Adjustable delay comparator 115,120 among Fig. 3 can be realized that it comes continuous its time-delay of adjusting through regulating the control voltage 65 of tail current transistor by circuit shown in Figure 4.
Come the principle of the method for feedback regulation time-delay through the output frequency that detects relaxation oscillator based on phase-locked loop, as shown in Figure 5.This time-delay feedback circuit comprises a subordinate oscillator 134 and a phase feedback circuit 140.The subordinate oscillator has frequency adjustment input 153 and regulates its output frequency.The phase feedback circuit comprises phase comparator 150 and filter circuit 160.The output 130 of phase feedback circuit feeds back to the frequency adjustment input 153 of subordinate oscillator; Form negative feedback; The output frequency of subordinate oscillator is locked onto on the output frequency of original relaxation oscillator; That is to say that the output frequency that makes the output frequency of subordinate oscillator 134 equal original relaxation oscillator multiply by a constant.Be that the output 130 of phase feedback circuit also feeds back to the time-delay of comparator in the relaxation oscillator and regulates input 65 with the inconsistent place of traditional phase-locked loop.If some environmental variance E (like temperature, supply power voltage) changes delta E, output 130 corresponding the making adjustment of phase feedback circuit, changes delta Vc makes the frequency change Δ f of subordinate oscillator
SThe frequency change Δ f of locking relaxation oscillator
MThe frequency change of subordinate oscillator can be expressed as:
Δf
S＝K
ESΔE+K
CSΔV
C (1)
Here KES is the sensitivity of subordinate oscillator output frequency to environmental variance Δ E, K
CSBe the sensitivity of subordinate oscillator output frequency to frequency control signal Δ Vc; Equally, the frequency change of relaxation oscillator can be expressed as
Δf
M＝K
EMΔE+K
CMΔV
C (2)
Here K
EMBe the sensitivity of relaxation oscillator output frequency to environmental variance Δ E, K
CMBe the sensitivity of relaxation oscillator output frequency to frequency control signal Δ Vc; Since behind the pll lock, Δ f
S=Δ f
M, can release by (1) and (2)
Design suitable subordinate oscillator parameter, the output frequency of feasible
such relaxation oscillator just greatly reduces the susceptibility of environmental variance.
Can further prove,
Prerequisite under,
The subordinate oscillator design can be satisfied this requirement for the relaxation oscillator type, as shown in Figure 6.If the comparator of use and original relaxation oscillator same design in this subordinate oscillator, thereby make that their time-delay is close.Through increasing the current source 225,230 in the subordinate oscillator, perhaps reduce timing reference signal 205,210, make the frequency of oscillation of subordinate oscillator increase n times for original relaxation oscillator.The output frequency of subordinate oscillator passes through after the n frequency division so, the condition that has just satisfied
.
The subordinate oscillator can also be designed to the ring oscillator type, and is as shown in Figure 7.The inverter 170 adjustable with some time-delays connects into annular, and the input of each inverter is coupled to the output of last inverter on the ring.Regulate the time-delay of inverter through the size of regulating the electric current that flows through on the tail current transistor 175, thus the frequency of regulating ring oscillator.Because the variation of temperature and supply power voltage is obeyed same trend to the inverter time-delay and to the influence of comparator time-delay, this feedback control circuit also can be realized certain FREQUENCY CONTROL precision.
The variation that detects the signal value of charge cycle on timing capacitor finish time needs the conversion of level with the method for regulating time-delay, and the conversion of signals that in one-period, constantly changes on the timing capacitor is direct current signal, and is as shown in Figure 8.Convert the signal on the timing capacitor 54,59 into transition signal 305,310 through change-over circuit 325,330.Design of switching circuit should guarantee that transition signal is the monotropic function (promptly for certain known time-delay size, the transition signal of unique correspondence being arranged) of time-delay.Detected transition signal is sent into regulating circuit 335,340 compares with predefined time-delay reference signal 315,320; Generation control signal 130a, 130b feed back to the time-delay adjustable side 65 of comparator 115,120 in the relaxation circuit respectively; Form negative feedback; Thereby make the detected transition signal 305 and the error (and error of transition signal 310 and time-delay reference signal 320) of time-delay reference signal 315 be reduced to minimum with stable time-delay, come accurately to control the time-delay of comparator thus.
A kind of simple change-over circuit can be realized through the signal value of charge cycle finish time on the timing capacitor is sampled, and is as shown in Figure 9.With change-over circuit 325 is example, and it comprises sampling capacitance 405, the sampling switch 415 of connection 405 and timing capacitor 55, the sampling clock generator 401 of generation sampling clock 83.Sampling switch 415 is by sampling clock 83 controls.The clock signal 84,85 of clock generator 400 outputs makes to be disconnected to 45 closures from switch 35, has time-delay significantly.Between time delay, no longer include electric charge on the charging capacitor 55 and inject, voltage remains unchanged, shown in Figure 10 signal waveform.Sampling clock 83 switch 35 and 45 all break off during closed sampling switch 415, sample with the signal on 405 pairs of timing capacitors 55 of sampling capacitance.Signal on the sampling capacitance 405 is a transition signal 305, and it has reflected that accurately timing capacitor 55 is at the charge cycle signal value of the finish time.Regulating circuit 335 comprises trsanscondutance amplifier 425 and integrating capacitor 435; Convert the difference of transition signal 305 and time-delay reference signal 315 into frequency adjustment signal 130a; Input 65 is regulated in the time-delay that offers comparator 115 in (master) relaxation oscillator; Be used for regulating its time-delay automatically, make the poor of transition signal 305 and time-delay reference signal 315, just timing capacitor 55 is reduced to minimum at the signal value of charge cycle finish time with 315 difference.Realize the accurate control of the time-delay of comparator 115 thus, change-over circuit 330 and 325 operation principle are similar.
List of references:
[1]M.McCorquodale，et.al，“A?25-Mhz?self-referenced?solid-state?frequency?source?suitable?for?xo-replacement，”IEEE?Trans.Circuits?Syst.I，vol.56，no.5，pp.943-956，May?2009.
[2]K.Sundaresan，P.Allen，and?F.Ayazi，“Process?and?temperature?compensation?in?a?7-mhz?cmos?clock?oscillator，”IEEE?J.Solid-State?Circuits，vol.41，no.2，pp.433-442，2006.
[3]K.Choe，O.Bernal，D.Nuttman，and?M.Je，“A?precision?relaxation?oscillator?with?a?self-clocked?offset-cancellation?scheme?for?implantable?biomedical?socs，”in?IEEE?ISSCC?Dig.Tech.Papers，2009，pp.402-403.
[4]S.Y.?Sun，“An?Analog?PLL-Based?Clock?and?Data?Recovery?Circuit?with?High?Input?Jitter?Tolerance，”IEEE?J.Solid-State?Circuits，vol.24，no.2，pp.325-330，Apr.，1989.
Advantage, characteristics or good effect that invention compared with prior art has:
Compare traditional method; It is uncertain that the present invention has eliminated the output frequency that is caused by transmission delay uncertainty in the relaxation oscillator, when reducing power consumption, improved the precision of frequency of oscillation; Reduced frequency of oscillation to temperature, the sensitivity of environmental variances such as supply power voltage.
Description of drawings:
The relaxation oscillator schematic diagram that Fig. 1 is traditional
The signal waveform of each node among Fig. 2 Fig. 1
Fig. 3 regulates the schematic diagram of comparator time-delay automatically through negative feedback
The comparator circuit schematic diagram of Fig. 4 adjustable delay
Fig. 5 is based on the time-delay feedback circuit schematic diagram of phase-locked loop
Fig. 6 is based on the time-delay feedback circuit schematic diagram of phase-locked loop, and wherein the subordinate oscillator is the relaxation oscillator type
Fig. 7 is based on the time-delay feedback circuit schematic diagram of phase-locked loop, and wherein the subordinate oscillator is the ring oscillator type
Fig. 8 is based on the time-delay feedback circuit schematic diagram that detects signal on the timing capacitor
Fig. 9 is based on the time-delay feedback circuit schematic diagram of charge cycle signal value finish time sampling on the timing capacitor
The signal waveform of each node among Figure 10 Fig. 9
Embodiment:
Embodiment 1: as shown in Figure 6, (master) relaxation oscillator comprises timing capacitor 55,60, contains the charging circuit of constant current source 25 24 from node 54 to power supply; The charging circuit that contains constant current source 30 from node 59 to power supply 24; Pass through the discharge circuit of switch 45 from node 54 to earth potential 44, pass through the discharge circuit of switch 50 44 from node 59 to earth potential, switching device 38,43; Comparator 115,120, timing reference generator 1 and clock generator 0.Discharging and recharging of switching device 38 control timing capacitors 55, it comprises switch 35 and 45, at its first state, switch 35 closures, switch 45 breaks off, and timing capacitor 55 is carried out charging at the uniform velocity through the charging circuit that contains constant current source 25; At its second state, switch 35 breaks off, switch 45 closures, and timing capacitor 55 is through the discharge circuit 44 discharges from node 54 to ground.Discharging and recharging of switching device 43 control timing capacitors 60 is with 38 similar.Timing reference generator 1 produces timing reference signal 5,10.Clock generator 0 adopts the design of RS latch.Comparator 115,120 adopts the design of Fig. 4, and it has time-delay adjusting input 65 and regulates its time-delay.Whether the signal 54,59 that comparator is used for detecting on the timing capacitor surpasses timing reference signal 5,10.If surpass; Comparator output signal is given clock generator 0, is used for changing the state of RS latch, thereby changes the state of switching device; Make the timing capacitor that surpasses timing reference signal switch to discharge condition, and another timing capacitor switch to charged state from discharge from charging.This process is gone round and begun again, and produces periodically vibration.
The time-delay feedback circuit comprises subordinate oscillator 203, phase comparator 150, the filter 160 of charge pump type, frequency divider 202.Wherein the filter 160 of phase comparator 150, charge pump type and frequency divider 202 constitute the phase feedback circuit.The implementation of phase comparator 150 is common phase frequency detector.203 output is carried out bit comparison mutually through inputing to 150 together with the output of (master) relaxation oscillator after 202 frequency divisions.150 output is used to control the switch of 160 charge pump.160 output frequency conditioning signals 130 are given the frequency adjustment input of subordinate oscillator, and promptly input 65 is regulated in the time-delay of adjustable delay comparator 215,220 in the subordinate oscillator.Frequency adjustment signal 130 also is input to the time-delay of comparator 115,120 in (master) relaxation oscillator and regulates input 65.The phase feedback circuit makes the frequency lock of subordinate oscillator arrive on the frequency of (master) relaxation oscillator, that is to say that the output frequency of subordinate oscillator equates with the output frequency of (master) relaxation oscillator later through the n frequency division.Subordinate oscillator 203 comprises subordinate timing capacitor 255,260; The subordinate charging circuit that contains constant current source 225 from node 254 to power supply 24; The subordinate charging circuit that contains constant current source 230 from node 259 to power supply 24; Pass through the subordinate discharge circuit of switch 245 from node 254 to earth potential 44, pass through the subordinate discharge circuit of switch 250 44 from node 259 to earth potential, subordinate switching device 238,243; Subordinate comparator 215,220, subordinate timing reference generator 201 and slave clock generator 200.
Embodiment 2:
As shown in Figure 7, except the design of the design of subordinate oscillator 103 and the subordinate oscillator 203 among Fig. 6 was inconsistent, all the other were all identical with embodiment 1.Subordinate oscillator 103 is the ring oscillator type in this example, and the inverter 170 adjustable with some time-delays connects into annular, and the input of each inverter is coupled to the output of last inverter on the ring.The time-delay of inverter 170 can be regulated through the size of regulating the electric current that flows through on the tail current transistor 175.The output that the output of any inverter is sent into phase comparator 150,150 later on through frequency divider 202 frequency divisions is used to control the switch of 160 charge pump.The electric current that 160 output frequency conditioning signals 130 come control flows to cross for the grid of tail current transistor 175, thereby the frequency of oscillation of regulating subordinate oscillator 103.Frequency adjustment signal 130 also is input to the time-delay of comparator 115,120 in (master) relaxation oscillator and regulates input 65.
Embodiment 3:
As shown in Figure 9, (master) relaxation oscillator comprises timing capacitor 55,60, contains the charging circuit of constant current source 25 24 from node 54 to power supply; The charging circuit that contains constant current source 30 from node 59 to power supply 24; Pass through the discharge circuit of switch 45 from node 54 to earth potential 44, pass through the discharge circuit of switch 50 44 from node 59 to earth potential, switching device 38,43; Comparator 115,120, timing reference generator 1 and clock generator 400.Discharging and recharging of switching device 38 control timing capacitors 55, it comprises switch 35 and 45, at its first state, switch 35 closures, switch 45 breaks off, and timing capacitor 55 is carried out charging at the uniform velocity through the charging circuit that contains constant current source 25; At its second state, switch 35 breaks off, switch 45 closures, and timing capacitor 55 is through the discharge circuit 44 discharges from node 54 to ground.Discharging and recharging of switching device 43 control timing capacitors 60 is with 38 similar.Timing reference generator 1 produces timing reference signal 5,10.Comparator 115,120 adopts the design of Fig. 4, and it has time-delay adjusting input 65 and regulates its time-delay.
Change-over circuit 325 comprises sampling capacitance 405, the sampling switch 415 of connection 405 and timing capacitor 55, the sampling clock generator 401 of generation sampling clock 83.Sampling switch 415 is by sampling clock 83 controls.Clock generator 400 in this example has been revised the design of the clock generator 0 in the example 1, and its clock signal 84,85 makes to be disconnected to 45 closures from switch 35, has time-delay significantly.Between time delay, the electric charge on the charging capacitor 55 remains unchanged, shown in Figure 10 signal waveform.Sampling clock 83 switch 35 and 45 all break off during closed sampling switch 415, sample with the electric charge on 405 pairs of timing capacitors 55 of sampling capacitance.Signal on the sampling capacitance 405 is transition signal 305, and it has reflected the timing capacitor signal value of 55 charge cycle finish times accurately.Regulating circuit 335 comprises trsanscondutance amplifier 425 and integrating capacitor 435; Convert the difference of transition signal 305 and time-delay reference signal 315 into frequency adjustment signal 130a; Input 65 is regulated in the time-delay that offers comparator 115 in (master) relaxation oscillator; Be used for regulating its time-delay automatically, make the poor of transition signal 305 and time-delay reference signal 315, just the signal value of 55 charge cycle finish times of timing capacitor is reduced to minimum with 315 difference.
Change-over circuit 330 and 325 operation principle are similar.
Regulating circuit 335 comprises trsanscondutance amplifier 425 and integrating capacitor 435; Convert the difference of transition signal 305 and time-delay reference signal 315 into frequency adjustment signal 130a; Input 65 is regulated in the time-delay that offers comparator 115 in (master) relaxation oscillator; Be used for regulating its time-delay automatically, make the poor of transition signal 305 and time-delay reference signal 315, just the signal value of 55 charge cycle finish times of timing capacitor is reduced to minimum with 315 difference.Regulating circuit 340 and 335 operation principle are similar.
Claims (8)
1. relaxation oscillator; Comprise at least one timing capacitor, at least one charging circuit, at least one discharge circuit; At least one cover has first and second state of switch device; A timing reference generator that is used for producing at least one timing reference signal, at least one comparator, a clock generator that is used for clocking;
First state of said switching device charges to said timing capacitor through said charging circuit, and second state of said switching device discharges to said timing capacitor through said discharge circuit;
Signal on the more said timing capacitor of said comparator and said timing reference signal;
The output signal of said comparator is coupled to the input of said clock generator;
Said clock signal is selected the state of said switching device;
It is characterized in that:
Also comprise a time-delay feedback circuit;
In the said comparator at least one has time-delay adjusting input and brings in its time-delay of adjusting;
At least one input of said time-delay feedback circuit is coupled to the signal on the said timing capacitor, or the output signal of said comparator, or
Said clock signal;
The output of said time-delay feedback circuit is coupled to said time-delay regulates input, the time-delay that comes the said comparator of automatic stabilisation.
2. relaxation oscillator according to claim 1; It is characterized in that: said clock generator is provided with latch (RS Latch) for resetting; The input of said clock generator is that said resetting is provided with the reset terminal of latch or end is set, and the output of said clock generator is said positive output end or the reversed-phase output that resets latch is set.
3. relaxation oscillator according to claim 1 is characterized in that: said time-delay feedback circuit comprises one and has the subordinate oscillator that its output frequency of adjusting is brought in the frequency adjustment input, a phase feedback circuit; Said phase feedback circuit provides the frequency adjustment signal to said frequency adjustment input, and the signal frequency that the input that makes the output frequency of said subordinate oscillator equal said time-delay feedback circuit receives multiply by a constant; The input of said time-delay feedback circuit is coupled to the output signal of said clock signal or said comparator; Said frequency adjustment signal is coupled to the output of said time-delay feedback circuit.
4. relaxation oscillator according to claim 3; It is characterized in that: said subordinate oscillator comprises at least one subordinate timing capacitor, at least one subordinate charging circuit, at least one subordinate discharge circuit; At least one cover has the subordinate switching device of first and second state; A subordinate timing reference generator that is used for producing at least one subordinate timing reference signal, at least one subordinate comparator, a slave clock generator that is used for producing the slave clock signal;
First state of said subordinate switching device charges to said subordinate timing capacitor through said subordinate charging circuit, and second state of said subordinate switching device discharges to said subordinate timing capacitor through said subordinate discharge circuit;
Voltage on the more said subordinate timing capacitor of said subordinate comparator and said subordinate timing reference signal;
The output signal of said subordinate comparator is coupled to the input of said slave clock generator;
Said slave clock signal is selected the state of said subordinate switching device;
In the said subordinate comparator at least one has subordinate time-delay adjusting input and brings in its time-delay of adjusting;
It is the frequency adjustment input of said subordinate oscillator that input is regulated in said subordinate time-delay.
5. relaxation oscillator according to claim 3; It is characterized in that: said subordinate oscillator comprises some inverters; Each said inverter has output and input; Said some inverters constitute an inverter ring, and the input of each inverter is coupled to the output of last inverter on the said inverter ring, and one output is coupled to the output of said subordinate oscillator in said some inverters;
The frequency adjustment input of said subordinate oscillator is regulated the time-delay of said some inverters, thereby regulates the output frequency of said subordinate oscillator.
6. relaxation oscillator according to claim 3 is characterized in that: said phase feedback loop comprises a phase comparator with first and second input, a filter, a frequency divider; The signal that phase difference between signals that receives with its first input end and second input of said phase comparator output is directly proportional; Be coupled to the first input end of said phase comparator behind the output frequency process frequency divider frequency division of said subordinate oscillator, the input of said time-delay feedback circuit is coupled to second input of said phase comparator; The output signal of said phase comparator is coupled to the input of said filter; The output signal of said filter is the output signal in said phase feedback loop.
7. relaxation oscillator according to claim 1 is characterized in that: the signal on the said timing capacitor is coupled to the input of said time-delay feedback circuit; Said time-delay feedback circuit comprises a time-delay that is used for producing at least one time-delay reference signal with reference to generator, and one is the change-over circuit of transition signal with the conversion of signals on the said timing capacitor, the regulating circuit with first and second input; Said time-delay reference signal and said transition signal are coupled to first and second input of said regulating circuit respectively; The output signal of said regulating circuit is coupled to the output of said time-delay feedback circuit, adjusts the time-delay of said comparator, makes the difference of said time-delay reference signal and said transition signal reduce.
8. relaxation oscillator according to claim 7 is characterized in that: said switching device also has neither and through said charging circuit said timing capacitor is charged, also not through the third state of said discharge circuit to said timing capacitor discharge;
Said change-over circuit comprises a sampling capacitance, a sampling clock generator that produces sampled clock signal, and one by the sampling switch of said sampled clock signal control;
Said sampling switch connects said timing capacitor and said sampling capacitance;
The input of said sampling clock generator is coupled to the output signal or the said clock signal of said comparator;
Before said clock signal made that said switching device finishes at first state, second state begins, perhaps second state finished, first state gets into the third state before beginning;
Said sampled clock signal during said switching device gets into the third state, closed said sampling switch.
Signal on the said sampling capacitance is said transition signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110143263 CN102811054A (en) | 2011-05-30 | 2011-05-30 | Relaxation oscillator with low power consumption |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110143263 CN102811054A (en) | 2011-05-30 | 2011-05-30 | Relaxation oscillator with low power consumption |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102811054A true CN102811054A (en) | 2012-12-05 |
Family
ID=47234651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110143263 Pending CN102811054A (en) | 2011-05-30 | 2011-05-30 | Relaxation oscillator with low power consumption |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102811054A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103441749A (en) * | 2013-07-24 | 2013-12-11 | 国家电网公司 | Hysteresis-controllable synchronous comparator |
| CN105429611A (en) * | 2015-12-24 | 2016-03-23 | 深圳市汇春科技股份有限公司 | High-precision clock generator irrelevant to power and temperature |
| CN106664079A (en) * | 2014-07-12 | 2017-05-10 | 德州仪器公司 | Relaxation oscillator with current and voltage offset cancellation |
| CN107681994A (en) * | 2017-09-23 | 2018-02-09 | 深圳大学 | A kind of pierce circuit |
| CN107919855A (en) * | 2017-11-22 | 2018-04-17 | 武汉新芯集成电路制造有限公司 | A kind of PVT self compensations oscillator |
| EP3316482A1 (en) * | 2016-10-28 | 2018-05-02 | ams AG | Oscillator circuit and method for generating a clock signal |
| CN108001047A (en) * | 2017-12-29 | 2018-05-08 | 重庆辰罡科技有限公司 | A kind of metal derby coding assembly line |
| CN108512532A (en) * | 2018-06-29 | 2018-09-07 | 长江存储科技有限责任公司 | Relaxor |
| TWI673952B (en) * | 2018-12-28 | 2019-10-01 | 大陸商北京集創北方科技股份有限公司 | RC oscillator |
| CN111181552A (en) * | 2020-01-08 | 2020-05-19 | 电子科技大学 | Bidirectional frequency synchronous oscillator circuit |
| US10873292B2 (en) | 2018-12-11 | 2020-12-22 | Analog Devices International Unlimited Company | Relaxation oscillators with delay compensation |
| CN114144954A (en) * | 2020-02-04 | 2022-03-04 | 富士电机株式会社 | Detection circuit, switch control circuit, and power supply circuit |
-
2011
- 2011-05-30 CN CN 201110143263 patent/CN102811054A/en active Pending
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103441749B (en) * | 2013-07-24 | 2016-09-21 | 国家电网公司 | The sync comparator that a kind of sluggishness is controlled |
| CN103441749A (en) * | 2013-07-24 | 2013-12-11 | 国家电网公司 | Hysteresis-controllable synchronous comparator |
| CN106664079B (en) * | 2014-07-12 | 2020-04-24 | 德州仪器公司 | Relaxation oscillator with current and voltage offset cancellation |
| CN106664079A (en) * | 2014-07-12 | 2017-05-10 | 德州仪器公司 | Relaxation oscillator with current and voltage offset cancellation |
| CN105429611A (en) * | 2015-12-24 | 2016-03-23 | 深圳市汇春科技股份有限公司 | High-precision clock generator irrelevant to power and temperature |
| CN105429611B (en) * | 2015-12-24 | 2019-05-03 | 深圳市汇春科技股份有限公司 | A kind of high precision clock generator unrelated with power supply and temperature |
| EP3316482A1 (en) * | 2016-10-28 | 2018-05-02 | ams AG | Oscillator circuit and method for generating a clock signal |
| WO2018077719A1 (en) * | 2016-10-28 | 2018-05-03 | Ams Ag | Oscillator circuit and method for generating a clock signal |
| CN109845106B (en) * | 2016-10-28 | 2023-06-23 | ams有限公司 | Oscillator circuit and method for generating clock signals |
| US10742200B2 (en) | 2016-10-28 | 2020-08-11 | Ams Ag | Oscillator circuit and method for generating a clock signal |
| CN109845106A (en) * | 2016-10-28 | 2019-06-04 | ams有限公司 | For generating the pierce circuit and method of clock signal |
| CN107681994A (en) * | 2017-09-23 | 2018-02-09 | 深圳大学 | A kind of pierce circuit |
| CN107919855A (en) * | 2017-11-22 | 2018-04-17 | 武汉新芯集成电路制造有限公司 | A kind of PVT self compensations oscillator |
| CN107919855B (en) * | 2017-11-22 | 2019-07-02 | 武汉新芯集成电路制造有限公司 | A kind of PVT self compensation oscillator |
| CN108001047A (en) * | 2017-12-29 | 2018-05-08 | 重庆辰罡科技有限公司 | A kind of metal derby coding assembly line |
| CN108001047B (en) * | 2017-12-29 | 2023-11-24 | 重庆辰罡科技有限公司 | Metal block code spraying assembly line |
| CN108512532A (en) * | 2018-06-29 | 2018-09-07 | 长江存储科技有限责任公司 | Relaxor |
| US10873292B2 (en) | 2018-12-11 | 2020-12-22 | Analog Devices International Unlimited Company | Relaxation oscillators with delay compensation |
| TWI673952B (en) * | 2018-12-28 | 2019-10-01 | 大陸商北京集創北方科技股份有限公司 | RC oscillator |
| CN111181552A (en) * | 2020-01-08 | 2020-05-19 | 电子科技大学 | Bidirectional frequency synchronous oscillator circuit |
| CN114144954A (en) * | 2020-02-04 | 2022-03-04 | 富士电机株式会社 | Detection circuit, switch control circuit, and power supply circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102811054A (en) | Relaxation oscillator with low power consumption | |
| CN106059538B (en) | A kind of relaxor of included process deviation calibration function | |
| US9590638B2 (en) | Low power clock source | |
| US9099994B2 (en) | Relaxation oscillator | |
| CN102664605B (en) | Relaxation oscillator with low temperature drift characteristic, and debug method thereof | |
| CN102983836B (en) | Active RC filter automatic frequency tuning circuit | |
| CN102868396A (en) | Relaxation oscillator of low power consumption and high performance | |
| CN104113329A (en) | Frequency-locked loop circuit and semiconductor integrated circuit | |
| CN102684685B (en) | Phase locked loop and method thereof | |
| CN103595244A (en) | Relaxation oscillator with frequency jittering function | |
| CN103023461A (en) | RC (remote control) oscillating circuit | |
| CN103296968A (en) | Systems and methods of low power clocking for sleep mode radios | |
| US20200366298A1 (en) | Time-to-digital converter and phase locked loop | |
| CN104660216A (en) | High-precision frequency calibration circuit for Gm-C filter | |
| CN102832915A (en) | Programmable power-on reset system | |
| US11115036B1 (en) | Resistor-capacitor oscillator (RCO) with digital calibration and quantizaton noise reduction | |
| CN103107820A (en) | Full-integration complementary metal oxide semiconductor (CMOS) super-regeneration time division multiplexing wireless receiver structure | |
| CN115425925A (en) | High-precision RC oscillator circuit | |
| CN105720946A (en) | Relaxation oscillator | |
| CN102158202A (en) | High accuracy digital adjustable RC (Resistance Capacitance) oscillator | |
| CN104065344B (en) | Low-consumption oscillator | |
| CN104135277A (en) | An on-chip reference clock generation circuit and method thereof | |
| CN101447788A (en) | Circuit for generating phase-locked loop locking signal | |
| CN112615619B (en) | Three-threshold IF conversion circuit | |
| CN105610436A (en) | Charge pump phase-locked loop with adaptive acceleration locking structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| DD01 | Delivery of document by public notice |
Addressee: He Lin Document name: Notification of Passing Preliminary Examination of the Application for Invention |
|
| C06 | Publication | ||
| PB01 | Publication | ||
| DD01 | Delivery of document by public notice |
Addressee: He Lin Document name: Notification of before Expiration of Request of Examination as to Substance |
|
| DD01 | Delivery of document by public notice |
Addressee: He Lin Document name: Notification that Application Deemed to be Withdrawn |
|
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20121205 |