CN102158202A - High accuracy digital adjustable RC (Resistance Capacitance) oscillator - Google Patents
High accuracy digital adjustable RC (Resistance Capacitance) oscillator Download PDFInfo
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Abstract
The invention relates to a high accuracy digital adjustable RC (Resistance Capacitance) oscillator, which is formed by plugging a capacitive digital cap trimming module into a common RC (Resistance Capacitance) oscillator. The high accuracy digital adjustable RC (Resistance Capacitance) oscillator comprises two comparators COMP1 and COMP2, a RC (Resistance Capacitance) trigger, an NAND gate, three inverters INV1-INV3, six switching NMOS (N-Mental-Oxide-Semiconductor) tubes M1-M6, two capacitors C1 and C2, and a capacitive digital cap trimming module. The simulation result shows that, in the invention, by setting the signal value of the digital cap trimming module, the frequency can be regulated to approach a preset frequency, and the final frequency can bias within 2.6%. The circuit is simple in structure and applicable to various common RC (Resistance Capacitance) oscillators with capacitors.
Description
Technical field
The present invention relates to a kind of digital integrated circuit, particularly relate to the adjustable RC oscillator of a kind of high accuracy number.
Background technology
In the design of a lot of very lagre scale integrated circuit (VLSIC), clock signal is absolutely necessary, the circuit of clocking generally is a pierce circuit, the RC oscillator is that the oscillator the inside is most widely used, its cost is lower, simple in structure, the power consumption of other circuit is also less relatively, but the very big output frequency that must influence it of the operating voltage of circuit and working temperature, the technology correlation is poor, and precision is lower.
Fig. 1 is a kind of common RC oscillator circuit structure, it comprises two COMP comparators, a rest-set flip-flop, an electric capacity, form with a tri-state switch pipe, its operation principle is as follows: come the charge and discharge switch of control capacitance C with the output signal of rest-set flip-flop, when electric capacity was uncharged, RS triggered output low level, this moment, switch was connected to top Ic current source, electric capacity begins charging, and Vc increases, and surpasses V up to the Vc value
HThe time, comparator flows to high level of S end after relatively, makes rest-set flip-flop upset output high level, and switch is influenced by high level and is transferred to following Ic current source at once, and electric capacity begins discharge, and Vc reduces, and is less than V up to the Vc value
LThe time, comparator relatively back is carried high level of R end, makes rest-set flip-flop upset output low level, and then switch can be transferred to top Ic current source again automatically.By the feedback regulation switch capacitor C is carried out auto charge and discharge like this, produce periodic square-wave signal at output Q, the top crown at electric capacity produces a sawtooth signal simultaneously.
If electric capacity charging current I1, discharging current I2, then be the cycle of oscillation of capacitor C:
In the ideal case, this common RC oscillator frequency and capacitance size are inversely proportional to, and are directly proportional with the capacitance current value, (promptly linear) with set time constant RC, and under actual conditions, consider the transmission delay of comparator, the actual cycle will increase, and frequency will reduce.So the output waveform of common RC oscillator such as Fig. 2, capacitance voltage Vc is surpassing V
HAfter td time of still need charging just can make rest-set flip-flop upset, promptly its cycle has increased the time of td at least, the fluctuation of supply voltage in addition, the increase of temperature, the deviation of technology all can have influence on the gate leve time-delay of circuit, and then influences the circuit precision.
Summary of the invention
The objective of the invention is to provides a kind of high accuracy number adjustable RC oscillator at the not high shortcoming of common RC oscillator precision.Its circuit structure is simple, is applicable to the various common RC pierce circuits that contain electric capacity.
For reaching above-mentioned purpose, the present invention adopts following technical proposals:
A kind of high accuracy number is adjustable RC oscillator comprises comparator C OMP1, comparator C OMP2 and a rest-set flip-flop.It is characterized in that, the top crown of the capacitor C 1 of positive input termination of described comparator C OMP1, negative input end meets a reference voltage signal Vref, the S end of the described rest-set flip-flop of output termination; The top crown of the capacitor C 2 of positive input termination of described comparator C MOP2, negative input end meets reference voltage signal Vref, the R end of the described rest-set flip-flop of output termination; The output Q of described rest-set flip-flop connects the input of an inverter INV1; The input of the inverter INV2 of output termination of this inverter INV1; The output end signal of this inverter INV2 is Vq, connects the input of a NAND gate NAND; Another input termination Ven signal of this NAND gate NAND, output end signal is VqN, meets an inverter INV3; The output end signal of this inverter INV3 is Vout; The bottom crown ground connection of two described capacitor C 1, C2; The drain electrode of a nmos switch pipe M1 connects the top crown of capacitor C 1, and source ground, grid connect the Vq signal; The drain electrode of a nmos switch pipe M2 connects the top crown of capacitor C 2, and source ground, grid connect the VqN signal; The drain electrode of a nmos switch pipe M3 meets bias current signal Ibias1, and source electrode connects the top crown of capacitor C 1, and grid connects the VqN signal; The drain electrode of a nmos switch pipe M4 meets bias current signal Ibias2, and source electrode connects the top crown of capacitor C 2, and grid connects the Vq signal; The drain electrode of a nmos switch pipe M5 meets bias current signal Ibias1, and source ground, grid connect the Vq signal; The drain electrode of a nmos switch pipe M6 meets bias current signal Ibias2, and source ground, grid connect the VqN signal; The top crown of the described capacitor C 1 of A1 termination of an electric capacity digital trimming module Cap triming, the top crown of the described capacitor C 2 of A2 termination.
Above-mentioned comparator C OMP1, COMP2 adopt common source differential pair structure.
Above-mentioned Cap trimming module comprises the capacitor C 3 ~ C12 of ten switch NMOS pipe M7 ~ M16 and ten different capacitances, wherein the drain D of five NMOS pipe M7 ~ M11 meets port A1, the source electrode of M7 connects the top crown of capacitor C 3, the grid of M7 meets configuration signal EN1, the source electrode of M8 connects the top crown of capacitor C 4, the grid of M8 meets configuration signal EN2, the source electrode of M9 connects the top crown of capacitor C 5, the grid of M9 meets configuration signal EN3, the source electrode of M10 connects the top crown of capacitor C 6, the grid of M10 meets configuration signal EN4, and the source electrode of M11 connects the top crown of capacitor C 7, and the grid of M11 meets configuration signal EN5; The drain D of five NMOS pipe M12 ~ M16 meets port A2 in addition, the source electrode of M12 connects the top crown of capacitor C 8, the grid of M12 meets configuration signal EN6, the source electrode of M13 connects the top crown of capacitor C 9, the grid of M13 meets configuration signal EN7, the source electrode of M14 connects the top crown of capacitor C 10, the grid of M9 meets configuration signal EN8, the source electrode of M15 connects the top crown of capacitor C 11, the grid of M15 meets configuration signal EN9, the source electrode of M16 connects the top crown of capacitor C 12, and the grid of M16 meets configuration signal EN10, and the bottom crown of ten capacitor C 3 ~ C12 is ground connection all.
The present invention compared with prior art has following conspicuous outstanding substantive distinguishing features and remarkable advantage:
1. the present invention shows through simulation result, sees Table 1, and The data CADENCE SPECTRE circuit simulation tools obtains in the table; The used parameter model of emulation is to go up 0.5 micron BICMOS process modeling of China; Under the condition that power supply changes from 3.5V to 5.0V, the frequency change of common RC oscillator is bigger.The present invention can adjust to frequency near the frequency of setting by the signal value of digital trimming module is set, and can make last frequency departure in 2.6%;
Table 1 supply voltage digital capacitance fine setting table
2. circuit structure of the present invention is simple, is applicable to the various common RC oscillator occasions that contain electric capacity.
Description of drawings
Fig. 1 is existing common RC pierce circuit figure;
Fig. 2 is the corresponding simulation waveform of existing common RC pierce circuit figure;
Fig. 3 is the circuit structure block diagram of the embodiment of the invention;
Fig. 4 is a Cap trimming digital trimming functional-block diagram in Fig. 3 example of the present invention;
Fig. 5 is Cap trimming circuit theory diagrams in Fig. 3 example of the present invention.
Embodiment
See Fig. 3, Fig. 4, Fig. 5, preferential embodiment accompanying drawings of the present invention is as follows: this high accuracy number is adjustable, and the RC oscillator comprises comparator C OMP1, comparator C OMP2 and a rest-set flip-flop.
Operation principle is as follows: referring to Fig. 3, comparator C OMP1 and COMP2 have an input to be connected to reference voltage source Vref respectively, another input respectively connects an electric capacity, initial bias current Ib ias1 and Ibias2 equate, respectively to capacitor C 1 and C2 charging, if the capacitance of initial C1 is greater than the capacitance of C2, then the voltage VC2 on the C2 electric capacity surpasses Vref at first, comparator C OMP2 exports high level, the R of rest-set flip-flop end is pulled to high potential then, and voltage VC1 also surpasses Vref, comparator C OMP1 output low level on the while C1 electric capacity, make the S end of rest-set flip-flop be pulled down to electronegative potential, rest-set flip-flop is in reset mode, and output Vq is a low level signal, and VqN is a high level signal, the output Vout of last oscillator is a low level signal, make M2, M3, three metal-oxide-semiconductor conductings of M6, then C2 electric capacity begin the discharge, in case on the C2 electric capacity voltage VC2 less than Vref, comparator C OMP2 begins output low level, makes the R end output electronegative potential of rest-set flip-flop.Meanwhile, when the Vq signal is low level, M1, M4, three metal-oxide-semiconductors of M5 turn-off, bias current continues capacitor C 1 charging, up to the C1 capacitance voltage greater than Vref, comparator C OMP1 exports high level, make the S end of rest-set flip-flop be pulled to high potential, so rest-set flip-flop is in SM set mode, the output Vout of last oscillator is a high level signal, output Vq is a high level signal, can make M1, M4, three metal-oxide-semiconductor conductings of M5, VqN is a low level signal, makes M2, M3, three metal-oxide-semiconductors of M6 end, Vref continues charging to C2, till the voltage VC2 on the C2 is greater than Vref voltage.Said process has just produced the square wave oscillator signal constantly repeatedly.
Low level time formula:
The time formula of high level:
The whole clock cycle is:
Can release from height electric formula (1)～(3), the frequency of circuit mainly is subjected to the influence of bias current Ibias1, Ibias2 in addition of capacitor C 1, C2 value, can reduce the influence of electric capacity to the circuit precision by the method that adopts digital trimming electric capacity.Difference by configurable register disposes the size of finely tuning C1, C2 capacitance, and then changes the frequency of circuit.
Referring to Fig. 4, above-mentioned Cap trimming digital trimming theory diagram, configurable register is connected to Cap trimming by EN1 ~ EN10 signal, Cap trimming module is connected on the oscillator by A1, A2 signal, configurable register is controlled the value of EN1～EN10 signal by the configuration of regulating different high electronegative potentials above 10 bit registers, with this capacitance size of finely tuning Cap trimming module and linking pierce circuit, reach the purpose that changes the impulse electricity time, and then finish fine setting output frequency.
Referring to Fig. 5, above-mentioned Cap trimming is by ten switch NMOS pipe M7 ~ M16, capacitor C 3 ~ the C12 of ten different capacitances forms, wherein, the value of each electric capacity is the relation that is multiplied successively, C8=C3=C2=C1, C9=C4=2C1, C10=C5=4C1, C11=C6=8C1, C12=C7=16C1.And A1 is connected to one of C1 charging pole plate, makes six electric capacity of C1, C3～C7 and be unified into total capacitance C1 '; A2 is connected to the charging pole plate of C2, makes remaining six electric capacity of C2, C8～C12 be parallel to together, and total capacitance is C2 '.
By disposing EN＜5:1 respectively〉and EN＜10:6 the value of ten signals, C1, the C2 value of shunt capacitance C1 ' and C2 ' separately can be changed.For example as EN＜10:1〉when being 1111111111, the M7 ~ whole conductings of M16 switching tube, the capacitance maximum of C1 ' and C2 ', by cycle formula (3) as can be seen, this moment output signal the cycle maximum, the frequency minimum; And as EN＜10:1 when being 0000000000, M7 ~ M16 switching tube all turn-offs, the capacitance minimum of C1 ' and C2 ', this moment output signal the cycle minimum, the frequency maximum; And as EN＜10:1 when being 1000001111, capacitance is in the centre position of adjustable extent, oscillator is in the center cycle.If initial Ibias1=Ibias2=I1, C1=C2, then the cycle of oscillator is as follows:
Maximum cycle:
(4)
The center cycle:
(5)
Minimum period:
(6)
Setting cycle of oscillation is center period T mid, and then the cycle can be regulated between Tmax and Tmin, and adjustable extent is:
Minimum tunable capacitor is C1, so the periodic adjustment precision is:
By formula (7) and (8) △ T=31 △ Tmin is arranged, the regulating cycle deviation of general RC oscillator is 1%～10%, makes △ T=± 10%, △ Tmin=± 0.323% then, thus determine the optimal period degree of regulation of RC oscillator.
Claims (3)
1. adjustable RC oscillator of high accuracy number, comprise comparator C OMP1, comparator C OMP2 and a rest-set flip-flop, it is characterized in that, the top crown of the capacitor C 1 of positive input termination of described comparator C OMP1, negative input end meets a reference voltage signal Vref, the S end of the described rest-set flip-flop of output termination; The top crown of the capacitor C 2 of positive input termination of described comparator C MOP2, negative input end meets reference voltage signal Vref, the R end of the described rest-set flip-flop of output termination; The output Q of described rest-set flip-flop connects the input of an inverter INV1; The input of the inverter INV2 of output termination of this inverter INV1; The output end signal of this inverter INV2 is Vq, connects the input of a NAND gate NAND; Another input termination Ven signal of this NAND gate NAND, output end signal is VqN, meets an inverter INV3; The output end signal of this inverter INV3 is Vout; The bottom crown ground connection of two described capacitor C 1, C2; The drain electrode of a nmos switch pipe M1 connects the top crown of capacitor C 1, and source ground, grid connect the Vq signal; The drain electrode of a nmos switch pipe M2 connects the top crown of capacitor C 2, and source ground, grid connect the VqN signal; The drain electrode of a nmos switch pipe M3 meets bias current signal Ibias1, and source electrode connects the top crown of capacitor C 1, and grid connects the VqN signal; The drain electrode of a nmos switch pipe M4 meets bias current signal Ibias2, and source electrode connects the top crown of capacitor C 2, and grid connects the Vq signal; The drain electrode of a nmos switch pipe M5 meets bias current signal Ibias1, and source ground, grid connect the Vq signal; The drain electrode of a nmos switch pipe M6 meets bias current signal Ibias2, and source ground, grid connect the VqN signal; The top crown of the described capacitor C 1 of A1 termination of an electric capacity digital trimming module Cap triming, the top crown of the described capacitor C 2 of A2 termination.
2. the adjustable RC oscillator of high accuracy number according to claim 1 is characterized in that described comparator C OMP1, COMP2 adopt common source differential pair structure.
3. the digital integrated circuit of the adjustable RC oscillator of high accuracy number according to claim 1 is characterized in that described electric capacity digital trimming module Cap timming comprises the capacitor C 3 ~ C12 of ten switch NMOS pipe M7 ~ M16 and ten different capacitances; Wherein the drain D of five NMOS pipe M7 ~ M11 meets port A1, the source electrode of M7 connects the top crown of capacitor C 3, the grid of M7 meets configuration signal EN1, and the source electrode of M8 connects the top crown of capacitor C 4, and the grid of M8 meets configuration signal EN2, the source electrode of M9 connects the top crown of capacitor C 5, the grid of M9 meets configuration signal EN3, and the source electrode of M10 connects the top crown of capacitor C 6, and the grid of M10 meets configuration signal EN4, the source electrode of M11 connects the top crown of capacitor C 7, and the grid of M11 meets configuration signal EN5; The drain D of five NMOS pipe M12 ~ M16 meets port A2 in addition, the source electrode of M12 connects the top crown of capacitor C 8, the grid of M12 meets configuration signal EN6, the source electrode of M13 connects the top crown of capacitor C 9, the grid of M13 meets configuration signal EN7, the source electrode of M14 connects the top crown of capacitor C 10, the grid of M9 meets configuration signal EN8, the source electrode of M15 connects the top crown of capacitor C 11, the grid of M15 meets configuration signal EN9, the source electrode of M16 connects the top crown of capacitor C 12, and the grid of M16 meets configuration signal EN10, and the bottom crown of ten capacitor C 3 ~ C12 is ground connection all.
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| CN103401553A (en) * | 2013-07-19 | 2013-11-20 | 电子科技大学 | Synchronous oscillator circuit |
| CN103873048A (en) * | 2014-03-12 | 2014-06-18 | 无锡中科微电子工业技术研究院有限责任公司 | On-chip RC oscillator with frequency self correction function and frequency self correction method |
| CN106026997A (en) * | 2016-06-21 | 2016-10-12 | 四川和芯微电子股份有限公司 | Differential comparator |
| CN103888138B (en) * | 2014-03-23 | 2017-04-12 | 上海正耘电子科技有限公司 | Method for outputting high-precision and high-frequency clock signals and oscillating circuit |
| CN107947764A (en) * | 2017-12-13 | 2018-04-20 | 中国科学院微电子研究所 | A kind of COMS pierce circuits |
| CN109474260A (en) * | 2019-01-11 | 2019-03-15 | 成都信息工程大学 | A kind of adjustable oscillator of number |
| CN110943496A (en) * | 2018-09-21 | 2020-03-31 | 北京兆易创新科技股份有限公司 | Charging and discharging circuit and oscillator |
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Cited By (11)
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| CN103401553A (en) * | 2013-07-19 | 2013-11-20 | 电子科技大学 | Synchronous oscillator circuit |
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| CN103873048B (en) * | 2014-03-12 | 2017-02-01 | 无锡中科微电子工业技术研究院有限责任公司 | On-chip RC oscillator with frequency self correction function and frequency self correction method |
| CN103888138B (en) * | 2014-03-23 | 2017-04-12 | 上海正耘电子科技有限公司 | Method for outputting high-precision and high-frequency clock signals and oscillating circuit |
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| CN110943496A (en) * | 2018-09-21 | 2020-03-31 | 北京兆易创新科技股份有限公司 | Charging and discharging circuit and oscillator |
| CN109474260A (en) * | 2019-01-11 | 2019-03-15 | 成都信息工程大学 | A kind of adjustable oscillator of number |
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Application publication date: 20110817 |