CN103023461A - RC (remote control) oscillating circuit - Google Patents
RC (remote control) oscillating circuit Download PDFInfo
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- CN103023461A CN103023461A CN2011103010270A CN201110301027A CN103023461A CN 103023461 A CN103023461 A CN 103023461A CN 2011103010270 A CN2011103010270 A CN 2011103010270A CN 201110301027 A CN201110301027 A CN 201110301027A CN 103023461 A CN103023461 A CN 103023461A
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Abstract
The invention provides an RC (remote control) oscillating circuit which comprises a reference current offering module, a first charge-discharge capacitor, a second charge-discharge capacitor, an integrating comparator, an integrating capacitor, and a clock generator, wherein one ends of the first charge-discharge capacitor and the second charge-discharge capacitor are respectively connected with a grounded terminal, the other ends of the first charge-discharge capacitor and the second charge-discharge capacitor are respectively connected with a first switch and a second switch, both ends of the first charge-discharge capacitor and the second charge-discharge capacitor are respectively connected with a third switch and a fourth switch in parallel, the positive input end of the integrating comparator is connected with a reference voltage, the negative input end of the integrating comparator is connected with a point of common coupling of the first switch, the second switch and the reference current-offering module, the integrating capacitor is connected between the negative input end and output end of the integrating comparator, the clock generator is connected between the output ends of the integrating comparator and the RC oscillating circuit, thus generating a first clock frequency signal and a second clock frequency signal which are inverted, wherein the second switch and the third switch are controlled by the first clock frequency signal and the first switch and the fourth switch are controlled by the second clock frequency signal. According to the RC oscillating circuit, an accurate clock frequency signal which is not affected by temperature can be obtained.
Description
Technical field
The present invention relates to the hybrid digital-analog integrated circuit design field, specifically, the present invention relates to a kind of RC oscillating circuit.
Background technology
In the hybrid digital-analog integrated circuit system, clock circuit is essential accurately.In order to produce accurate clock signal, conventional method is to adopt the outer crystal oscillator of sheet as clock generator.Much more like this, the components and parts that to increase have just greatly promoted the cost of chip.And if adopt RC oscillator in the sheet as clock generator because the impact that is subjected to easily temperature time of delay of the integral contrast device in the RC oscillating circuit, the clock frequency variation with temperature of generation and changing can not satisfy the requirement of precision clock frequency.
Fig. 1 is the electrical block diagram of a conventional RC active oscillating circuit of the prior art.In order to obtain accurate clock output, generally all be to adopt in such a way in the prior art.
As shown in the figure, it is to adopt reference voltage Vref 1, amplifier 101 and off chip resistor 301 to generate accurately reference current to electric capacity 302 chargings, so that the voltage Vcap on the electric capacity 302 rises from 0V is linear, when this voltage Vcap surpasses reference voltage Vref 2, integral contrast device 102 and clock generator 103 can produce clock control signal Ck1 and by control switch 401 electric charge on the electric capacity 302 be given out light, and allows the voltage Vcap on the electric capacity 302 come back to 0V.Like this, allow the voltage Vcap of electric capacity 302 maintain vibration between 0V and the reference voltage Vref 2 by FEEDBACK CONTROL, the output voltage V comp of integral contrast device 102 converts needed clock control signal Ck1 to by clock generator 103 again.
In addition, the output of amplifier 101 is connected to the grid of nmos pass transistor 201, and the source electrode of nmos pass transistor 201 is connected to off chip resistor 301.PMOS transistor 202,203 and voltage source V dd consist of mirror current source 205, produce the mirror image reference current.PMOS transistor 202,203 source electrode meet voltage source V dd, and grid docks each other, and the drain electrode of PMOS transistor 202 is connected with the drain electrode of nmos pass transistor 201, and the drain electrode of PMOS transistor 203 is connected with the negative input end of integral contrast device 102.The drain electrode of PMOS transistor 202 and its grid short circuit.Amplifier 101, nmos pass transistor 201 and mirror current source 205 consist of reference current provides module 204, and 401 on electric capacity 302 and switch consist of charge-discharge modules 305.
Note is I from the current value that PMOS transistor 203 flows out
s, the resistance value of off chip resistor 301 is R
0, the magnitude of voltage of reference voltage Vref 1 is V
1, then have:
I
s＝V
1/R
o (1)
The capacitance of note electric capacity 302 is C
0, the magnitude of voltage of reference voltage Vref 2 is V
2, the charging interval t of electric capacity 302 then
ChargeFor:
t
charge＝C
o·V
2/I
s (2)
Each clock cycle should be comprised of three part-times: the charging interval t of electric capacity 302
Charge, t discharge time of electric capacity 302
DischargeT time of delay with integral contrast device 102 and logical circuit
Delay, then the frequency f of final clock is:
As seen, the clock frequency that produces with prior art not only with electric capacity to discharge and recharge the time relevant, but also with the delay-correlated of integral contrast device and FEEDBACK CONTROL, these time-delays are highstrung to temperature often.When the clock frequency was higher, error then can be larger, these time-delays to affect meeting more outstanding, resulting clock frequency temperature influence is also just larger, so that can't obtain accurate clock frequency signal.
Summary of the invention
Technical problem to be solved by this invention provides a kind of oscillating circuit, can obtain the not accurate clock frequency signal of temperature influence.
For solving the problems of the technologies described above, the invention provides a kind of RC oscillating circuit, comprising:
Reference current provides module, is used for providing reference current;
The first charge and discharge capacitance, the one end is connected in an earth terminal, and the other end is connected in one first switch, and the other end of described the first switch is connected in described reference current module is provided, and the two ends of described the first charge and discharge capacitance are connected in parallel to one the 3rd switch;
The second charge and discharge capacitance, the one end is connected in an earth terminal, and the other end is connected in a second switch, and the other end of described second switch is connected in described reference current module is provided, and the two ends of described the second charge and discharge capacitance are connected in parallel to one the 4th switch;
The integral contrast device, its positive input terminal is connected in a reference voltage, and its negative input end is connected in the points of common connection that described the first switch, described second switch and described reference current provide module;
Integrating capacitor is connected between the negative input end and output of described integral contrast device;
Clock generator is connected between the output of the output of described integral contrast device and described RC oscillating circuit, produces the first clock frequency signal inverting each other and second clock frequency signal;
Wherein, described second switch and described the 3rd switch are controlled by described the first clock frequency signal, and described the first switch and described the 4th switch are controlled by described second clock frequency signal.
Alternatively, described reference current provides module to comprise:
Error amplifier, its positive input terminal is connected in another reference voltage, and its negative input end is connected in an off chip resistor, and the other end of described off chip resistor is connected in an earth terminal;
Nmos pass transistor, its grid is connected in the output of described error amplifier, and its source electrode is connected in the negative input end of described error amplifier;
Mirror current source, the one end is connected in the drain electrode of described nmos pass transistor, and the other end is connected in the points of common connection of described the first switch and described second switch, is used for providing the electric current identical with opposite side.
Alternatively, described mirror current source comprises:
The one PMOS transistor, its drain electrode is connected in the drain electrode of described nmos pass transistor, and its source electrode is connected in a voltage source, its grid and drain electrode short circuit;
The 2nd PMOS transistor, its source electrode is connected in described voltage source, and its grid is connected in the transistorized grid of a described PMOS, and its drain electrode is connected in the points of common connection of described the first switch and described second switch.
Alternatively, described the first charge and discharge capacitance is identical with the capacitance of the second charge and discharge capacitance.
Alternatively, the calculating formula of the clock frequency of generation is:
Wherein, the clock frequency of f for producing, V
1And V
2Be respectively the magnitude of voltage of above-mentioned reference voltage and another reference voltage, R
oBe the resistance value of described off chip resistor, C
oCapacitance for described the first charge and discharge capacitance and the second charge and discharge capacitance.
Compared with prior art, the present invention has the following advantages:
The present invention has increased an integrating capacitor on the basis of original integral contrast device, make its function be converted into storage and the release of electric charge by original simple voltage ratio.When the RC oscillating circuit reaches dynamic equilibrium, the clock frequency of output only with two sheets in electric capacity discharge and recharge time correlation, and irrelevant with the time of delay of integral contrast device and FEEDBACK CONTROL, reached thus the purpose of accurate clock frequency signal output.
The present invention has adopted the method for current integration to eliminate to the full extent the impact of integral contrast device time of delay, utilize simultaneously the compound mode of electric capacity in off chip resistor and the sheet, add the later stage calibration to two reference voltages, just can compensate because the variation of the inconsistent capacitor's capacity that causes of temperature and technique, in the situation that does not substantially increase additional devices, realize the output of accurate clock frequency signal, make it not be subjected to the impact of temperature and technique.And the power consumption the during normal operation of not impact system has so just greatly reduced system cost.
Description of drawings
The above and other features of the present invention, character and advantage will become more obvious by the description below in conjunction with drawings and Examples, wherein:
Fig. 1 is the electrical block diagram of a conventional RC active oscillating circuit of the prior art;
Fig. 2 is the electrical block diagram of the RC oscillating circuit of one embodiment of the invention;
Fig. 3 is each parameter waveform schematic diagram of the course of work of the RC oscillating circuit of one embodiment of the invention.
Embodiment
The invention will be further described below in conjunction with specific embodiments and the drawings; set forth in the following description more details so that fully understand the present invention; but the present invention obviously can implement with multiple this description ground alternate manner that is different from; those skilled in the art can do similar popularization, deduction according to practical situations in the situation of intension of the present invention, therefore should be with content constraints protection scope of the present invention of this specific embodiment.
Fig. 2 is the electrical block diagram of the RC oscillating circuit of one embodiment of the invention.As shown in the figure, this RC oscillating circuit 600 can comprise for generation of accurate clock frequency signal: reference current provides the assemblies such as module 704, integral contrast device 602, clock generator 603, integrating capacitor 804, the first charge and discharge capacitance 802 and the second charge and discharge capacitance 803.Wherein, reference current provides module 704 to be used for providing reference current; One end of the first charge and discharge capacitance 802 is connected in an earth terminal, and the other end that the other end is connected in one first switch, 901, the first switches 901 is connected in reference current provides the two ends of module 704, the first charge and discharge capacitances 802 to be connected in parallel to one the 3rd switch 903; One end of the second charge and discharge capacitance 803 is connected in an earth terminal, and the other end is connected in a second switch 902, and the other end of second switch 902 is connected in reference current provides the two ends of module 704, the second charge and discharge capacitances 803 to be connected in parallel to one the 4th switch 904; The positive input terminal of integral contrast device 602 is connected in a reference voltage Vref 2, and its negative input end is connected in the points of common connection that the first switch 901, second switch 902 and reference current provide module 704; Integrating capacitor 804 is connected between the negative input end and output of integral contrast device 602; Clock generator 603 is connected between the output of the output of integral contrast device 602 and RC oscillating circuit 600, produces the first clock frequency signal Ck1 inverting each other and second clock frequency signal Ck2; Wherein, second switch 902 and the 3rd switch 903 are controlled by the first clock frequency signal Ck1, and the first switch 901 and the 4th switch 904 are controlled by second clock frequency signal Ck2.The first charge and discharge capacitance 802, the second charge and discharge capacitance 803, the first switch 901, second switch 902, the 3rd switch 903 and the 4th switch 904 can form charge-discharge modules 805.
In the present embodiment, reference current provides module 704 to comprise: error amplifier 601, nmos pass transistor 701 and mirror current source 705.Continue as shown in Figure 2, wherein, the positive input terminal of error amplifier 601 is connected in the first reference voltage Vref 1, and negative input end is connected in off chip resistor 801, and the other end of off chip resistor 801 is connected in earth terminal; The grid of nmos pass transistor 701 is connected in the output of error amplifier 601, and source electrode is connected in the negative input end of error amplifier 601; One end of mirror current source 705 is connected in the drain electrode of nmos pass transistor 701, and the other end is connected in the points of common connection of the first switch 901 and second switch 902, is used for providing the electric current identical with opposite side, i.e. reference current.
In the present embodiment, mirror current source 705 can comprise: a PMOS transistor 702 and the 2nd PMOS transistor 703.Still as shown in Figure 2, wherein, the drain electrode of a PMOS transistor 702 is connected in the drain electrode of nmos pass transistor 701, and source electrode is connected in a voltage source V dd, grid and drain electrode short circuit; The source electrode of the 2nd PMOS transistor 703 is connected in voltage source V dd, and grid is connected in the grid of a PMOS transistor 702, and drain electrode is connected in the points of common connection of the first switch 901 and second switch 902.
After circuit powered on, T1 constantly the second reference voltage Vref 2 established, and T2 produces reference current by off chip resistor 801 and the first reference voltage Vref 1 constantly.This moment, the first switch 901 and the 4th switch 904 kept on-state, and second switch 902 and the 3rd switch 903 remain open state.This reference current at first charges to the first charge and discharge capacitance 802 and integrating capacitor 804, and the voltage Vint of integral contrast device 602 negative input ends raises gradually.At T3 constantly, when voltage Vint surpassed the second reference voltage Vref 2, because the existence of integral contrast device 602, the voltage Vout of its output reduced synchronously.When the voltage Vout of integral contrast device 602 outputs is reduced to logical circuit (clock generator 603) turn threshold of back, it is the T4 moment, the on off state of its control changes, and the first clock frequency signal Ck1 and second clock frequency signal Ck2 are anti-phase.This moment, second switch 902 and the 3rd switch 903 began to connect, and the first switch 901 and the 4th switch 904 disconnect, and the electric charge zero clearing on the first charge and discharge capacitance 802, simultaneously the second charge and discharge capacitance 803 of zero charge are inserted charge circuit.
In the moment that above-mentioned on off state switches, integrating capacitor 804 will be finished redistributing of electric charge with the second charge and discharge capacitance 803.At this moment, the voltage Vint of integral contrast device 602 negative input ends can be dragged down by moment, reference current charges to these two electric capacity more again, this moment, Vint voltage can raise gradually, but owing to still be lower than the second reference voltage Vref 2, the output end voltage Vout of integral contrast device 602 also can rise synchronously, until voltage Vint surpasses the voltage levvl of the second reference voltage Vref 2, it is the T5 moment, this moment is because the variation of integral contrast device 602 input terminal voltages, the voltage Vout of output can transfer decline to by rising, constantly be reduced to the turn threshold of back logical circuit at T6, trigger the logical circuit (clock generator 603) of back, the on off state of enable clock generator 603 controls changes again, and the first clock frequency signal Ck1 and second clock frequency signal Ck2 is again anti-phase again.So repeatedly, when the metastable state of system held, because the electric charge of integrating capacitor 804 is in the state of dynamic equilibrium, in beginning and the end of a clock cycle, its quantity of electric charge can remain unchanged.Like this, the electric charge that brings of reference current can equivalence be thought and all is stored on first, second charge and discharge capacitance 802 or 803.And the time of delay of integral contrast device 602 and FEEDBACK CONTROL also with the stack of time that discharges and recharges of electric capacity, on not impact of clock frequency, so just can obtain accurately clock and export.
In the capacitor charging process, when the value of voltage Vint during near the second reference voltage Vref 2, reference current can continue to bring extra system mismatch for integral contrast device 602 to integrating capacitor 804 chargings, and the voltage Vint after stablizing thus can depart from the second reference voltage Vref 2.In order to eliminate this mismatch, reference current need to be introduced integral contrast device 602, allow it offset because the system mismatch that the voltage Vout of output introduces to integral contrast device 602 when reducing.
Fig. 3 is each parameter waveform schematic diagram of the course of work of the RC oscillating circuit of one embodiment of the invention.As shown in the figure, after circuit powers on, the second reference voltage Vref 2 and reference current model.This moment, non-the first overlapping clock frequency signal Ck1 was low level, and second clock frequency signal Ck2 is high level, and the first charge and discharge capacitance 802 and integrating capacitor 804 are charged by reference current so that voltage Vint climbed.When voltage Vint surpassed the second reference voltage Vref 2, under the effect of integral contrast device 602, voltage Vout slowly reduced until be lower than the threshold value of clock generator 603.At this moment, clock frequency signal Ck1, Ck2 level will overturn, and the electric charge elder generation and the second charge and discharge capacitance 803 that are stored in integrating capacitor 804 carry out the electric charge distribution.Voltage Vint will be dragged down by instantaneous like this, then can again be filled height by reference current again.Before voltage Vint arrived the second reference voltage Vref 2 level, voltage Vout was also at climbed, until voltage Vint surpasses the second reference voltage Vref 2.Above process can periodically be carried out, thereby produces clock frequency output.
Here with following analysis among, ignored the impact of parasitic capacitance and quiescent biasing part.When circuit was in stable state, the electric charge that reference current brings in charge cycle can equivalence be thought and all is stored on the first or second charge and discharge capacitance 802 or 803.Can derive thus in this invention the calculating formula of the clock frequency f of generation:
Remember that the current value that the 2nd PMOS transistor 703 flows out is I
s(being reference current), the resistance value of off chip resistor 801 are R
o, the magnitude of voltage of the first reference voltage Vref 1 is V
1, then have:
I
s＝V
1/R
o (4)
In the present invention, the capacitance of the first charge and discharge capacitance 802 and the second charge and discharge capacitance 803 can be identical, also can be different.In the present embodiment, easy for what narrate, the capacitance of supposing both is identical.The capacitance of then remembering the first and second charge and discharge capacitances 802 and 803 is C
o, the magnitude of voltage of the second reference voltage Vref 2 is V
2, t is the time of each charge cycle, then has:
I
s·t＝C
o·V
2 (5)
Because a clock cycle can respectively charge once to the first and second charge and discharge capacitances 802 and 803, the corresponding clock cycle is 2t, and then the clock frequency f of RC oscillating circuit 600 outputs of present embodiment should be:
Can find out that from whole process clock frequency f of the present invention only these the several aspects of ratio with off chip resistor, the interior electric capacity of sheet and two reference voltage Vref 1 and Vref2 is relevant, these parameters are subjected to the impact of temperature very little, can ignore.By calibrating the ratio of two reference voltage Vref 1 and Vref2, can compensate because the variation of the inconsistent charge and discharge capacitance appearance value that causes of technique so just can obtain accurate clock frequency signal.And this is easy to accomplish, and the power consumption in not impact system when normal operation.In addition, the present invention does not introduce extra circuit unit substantially, has greatly reduced the cost of system.
Above-described, be an example of the present invention only, be not to limit the scope of protection of present invention.Provide module such as reference current, realize with the first reference voltage, off chip resistor and operational amplifier herein, but in the specific implementation process, also can realize this function with other special temperature independent reference current sources; And for the control of the switch in the charging process, be to adopt two identical interior electric capacity of sheet of capacitance to select respectively, discharge and recharge, but in specific implementation process, also can adopt the size of control reference current that single electric capacity is discharged and recharged to realize. herein
The present invention has increased an integrating capacitor on the basis of original comparator, make its function be converted into storage and the release of electric charge by original simple voltage ratio.When the RC oscillating circuit reaches dynamic equilibrium, the clock frequency of output only with two sheets in electric capacity discharge and recharge time correlation, and irrelevant with the time of delay of comparator and FEEDBACK CONTROL, reached thus the purpose of accurate clock frequency signal output.
The present invention has adopted the method for current integration to eliminate to the full extent the impact of comparator time of delay, utilize simultaneously the compound mode of electric capacity in off chip resistor and the sheet, add the later stage calibration to two reference voltages, just can compensate because the variation of the inconsistent capacitor's capacity that causes of temperature and technique, in the situation that does not substantially increase additional devices, realize the output of accurate clock frequency signal, make it not be subjected to the impact of temperature and technique.And the power consumption the during normal operation of not impact system has so just greatly reduced system cost.
Although the present invention with preferred embodiment openly as above, it is not to limit the present invention, and any those skilled in the art can make possible change and modification without departing from the spirit and scope of the present invention.Therefore, every content that does not break away from technical solution of the present invention, all falls within the protection range that claim of the present invention defines any modification, equivalent variations and modification that above embodiment does according to technical spirit of the present invention.
Claims (5)
1. RC oscillating circuit comprises:
Reference current provides module (704), is used for providing reference current;
The first charge and discharge capacitance (802), the one end is connected in an earth terminal, the other end is connected in one first switch (901), the other end of described the first switch (901) is connected in described reference current module (704) is provided, and the two ends of described the first charge and discharge capacitance (802) are connected in parallel to one the 3rd switch (903);
The second charge and discharge capacitance (803), the one end is connected in an earth terminal, the other end is connected in a second switch (902), the other end of described second switch (902) is connected in described reference current module (704) is provided, and the two ends of described the second charge and discharge capacitance (803) are connected in parallel to one the 4th switch (904);
Integral contrast device (602), its positive input terminal is connected in a reference voltage (Vref2), and its negative input end is connected in the points of common connection that described the first switch (901), described second switch (902) and described reference current provide module (704);
Integrating capacitor (804) is connected between the negative input end and output of described integral contrast device (602);
Clock generator (603), be connected between the output of the output of described integral contrast device (602) and described RC oscillating circuit (600), produce the first clock frequency signal (Ck1) inverting each other and second clock frequency signal (Ck2);
Wherein, described second switch (902) is controlled by described the first clock frequency signal (Ck1) with described the 3rd switch (903), and described the first switch (901) is controlled by described second clock frequency signal (Ck2) with described the 4th switch (904).
2. RC oscillating circuit according to claim 1 is characterized in that, described reference current provides module (704) to comprise:
Error amplifier (601), its positive input terminal are connected in another reference voltage (Vref1), and its negative input end is connected in an off chip resistor (801), and the other end of described off chip resistor (801) is connected in an earth terminal;
Nmos pass transistor (701), its grid is connected in the output of described error amplifier (601), and its source electrode is connected in the negative input end of described error amplifier (601);
Mirror current source (705), the one end is connected in the drain electrode of described nmos pass transistor (701), the other end is connected in the points of common connection of described the first switch (901) and described second switch (902), is used for providing the electric current identical with opposite side.
3. RC oscillating circuit according to claim 2 is characterized in that, described mirror current source (705) comprising:
The one PMOS transistor (702), its drain electrode is connected in the drain electrode of described nmos pass transistor (701), and its source electrode is connected in a voltage source (Vdd), its grid and drain electrode short circuit;
The 2nd PMOS transistor (703), its source electrode is connected in described voltage source (Vdd), its grid is connected in the grid of a described PMOS transistor (702), and its drain electrode is connected in the points of common connection of described the first switch (901) and described second switch (902).
4. each described RC oscillating circuit in 3 according to claim 1 is characterized in that described the first charge and discharge capacitance (802) is identical with the capacitance of the second charge and discharge capacitance (803).
5. RC oscillating circuit according to claim 4 is characterized in that, the calculating formula of the clock frequency of generation is:
Wherein, the clock frequency of f for producing, V
1And V
2Be respectively the magnitude of voltage of above-mentioned reference voltage (Vref2) and another reference voltage (Vref1), R
oBe the resistance value of described off chip resistor (801), C
oCapacitance for described the first charge and discharge capacitance (802) and the second charge and discharge capacitance (803).
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| CN2011103010270A CN103023461A (en) | 2011-09-28 | 2011-09-28 | RC (remote control) oscillating circuit |
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| CN2011103010270A CN103023461A (en) | 2011-09-28 | 2011-09-28 | RC (remote control) oscillating circuit |
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| CN103475189A (en) * | 2013-08-28 | 2013-12-25 | 中国航天科技集团公司第九研究院第七七一研究所 | Oscillator of PWM (pulse-width modulation) controller |
| CN105187030A (en) * | 2015-07-30 | 2015-12-23 | 上海华虹宏力半导体制造有限公司 | Oscillator |
| CN105262457A (en) * | 2015-09-24 | 2016-01-20 | 深圳市芯海科技有限公司 | Bias circuit of RC oscillator capable of on-chip and off-chip frequency modulation |
| CN105305961A (en) * | 2015-10-29 | 2016-02-03 | 上海华力微电子有限公司 | Oscillating circuit for eliminating comparator delay |
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| CN110429915A (en) * | 2019-07-29 | 2019-11-08 | 上海华虹宏力半导体制造有限公司 | RC oscillating circuit |
| CN112187216A (en) * | 2020-10-12 | 2021-01-05 | 上海磐启微电子有限公司 | RC oscillator with output frequency irrelevant to temperature |
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| CN103475189B (en) * | 2013-08-28 | 2015-11-18 | 中国航天科技集团公司第九研究院第七七一研究所 | A kind of oscillator of PWM controller |
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| CN105262457A (en) * | 2015-09-24 | 2016-01-20 | 深圳市芯海科技有限公司 | Bias circuit of RC oscillator capable of on-chip and off-chip frequency modulation |
| CN105305961B (en) * | 2015-10-29 | 2018-08-10 | 上海华力微电子有限公司 | Eliminate the oscillating circuit of comparator delay |
| CN105305961A (en) * | 2015-10-29 | 2016-02-03 | 上海华力微电子有限公司 | Oscillating circuit for eliminating comparator delay |
| CN106656044A (en) * | 2015-10-30 | 2017-05-10 | 德克萨斯仪器股份有限公司 | Systems and methods for tuning an oscillator frequency |
| CN106452395B (en) * | 2016-09-13 | 2019-03-05 | 华为技术有限公司 | A kind of multipath clock distribution circuit and electronic equipment |
| CN106452395A (en) * | 2016-09-13 | 2017-02-22 | 华为技术有限公司 | Multi-clock distribution circuit and electronic device |
| US10122354B2 (en) | 2016-09-13 | 2018-11-06 | Huawei Technologies Co., Ltd. | Multi-channel clock distribution circuit and electronic device |
| CN110350887B (en) * | 2018-04-08 | 2023-03-28 | 中芯国际集成电路制造(上海)有限公司 | Resistance-capacitance oscillator circuit and clock signal generating method |
| CN110350887A (en) * | 2018-04-08 | 2019-10-18 | 中芯国际集成电路制造(上海)有限公司 | The production method of RC oscillator circuit and clock signal |
| CN109639135A (en) * | 2019-01-22 | 2019-04-16 | 上海艾为电子技术股份有限公司 | A kind of charge pump circuit |
| CN109639135B (en) * | 2019-01-22 | 2024-03-01 | 上海艾为电子技术股份有限公司 | Charge pump circuit |
| CN110071696B (en) * | 2019-04-24 | 2023-06-09 | 聚辰半导体股份有限公司 | Continuous time integrator for temperature sensor |
| CN110071696A (en) * | 2019-04-24 | 2019-07-30 | 聚辰半导体股份有限公司 | A kind of continuous time integrator can be used for temperature sensor |
| CN110429915A (en) * | 2019-07-29 | 2019-11-08 | 上海华虹宏力半导体制造有限公司 | RC oscillating circuit |
| CN110429915B (en) * | 2019-07-29 | 2023-06-30 | 上海华虹宏力半导体制造有限公司 | RC oscillating circuit |
| CN112187216A (en) * | 2020-10-12 | 2021-01-05 | 上海磐启微电子有限公司 | RC oscillator with output frequency irrelevant to temperature |
| CN112187216B (en) * | 2020-10-12 | 2024-03-29 | 上海磐启微电子有限公司 | RC oscillator with output frequency irrelevant to temperature |
| CN113346878A (en) * | 2021-06-17 | 2021-09-03 | 南京英锐创电子科技有限公司 | Clock circuit and electronic device |
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Application publication date: 20130403 |