CN109639135A - A kind of charge pump circuit - Google Patents
A kind of charge pump circuit Download PDFInfo
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- CN109639135A CN109639135A CN201910056713.2A CN201910056713A CN109639135A CN 109639135 A CN109639135 A CN 109639135A CN 201910056713 A CN201910056713 A CN 201910056713A CN 109639135 A CN109639135 A CN 109639135A
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/075—Charge pumps of the Schenkel-type including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The present invention provides a kind of charge pump circuits, including clock signal generating module, first capacitor, the second capacitor, charge and discharge control module and bias current generation module；The bias current generation module is used to sample the electric current in load, and generates bias current according to the electric current of the sampling；The clock signal generating module is used to generate clock signal according to the bias current；The charge and discharge control module is used to control that one in the first capacitor and second capacitor charging, another is to the load supplying according to the clock signal.When the load, the electric current in the load of sampling and bias current meeting corresponding change, so that the frequency of the clock signal generated may also change accordingly, so that ripple voltage reduces or remains unchanged, so that the voltage fluctuation in load reduces.
Description
Technical field
The present invention relates to charge pumping technique fields, more specifically to a kind of charge pump circuit.
Background technique
Charge pump is one of common module in IC system, the original that it utilizes capacitor both end voltage that cannot be mutated
Reason so that output voltage realizes the function of increasing input reference voltage multiplication of voltage, while in turn discharging to output loading.Electricity
Lotus pumps due to having the advantages that area is small, structure is simple, being not necessarily to component outside piece, have become many interior high pressure systems
The power supply module of system.But in existing charge pump, when the load of charge pump reduces, the ripple that charge pump output generates is electric
Pressure will increase, and causes the voltage fluctuation in load too big, influences the stability of output stage, significantly limit the application of charge pump
Range.
Summary of the invention
In view of this, the present invention provides a kind of charge pump circuit, to solve the voltage wave in existing charge pump load
Dynamic too big problem.
To achieve the above object, the invention provides the following technical scheme:
A kind of charge pump circuit, including clock signal generating module, first capacitor, the second capacitor, charge and discharge control module
With bias current generation module；
The bias current generation module is used to sample the electric current in load, and generates biasing according to the electric current of the sampling
Electric current；
The clock signal generating module is used to generate clock signal according to the bias current；
The charge and discharge control module is used to control the first capacitor and second capacitor according to the clock signal
In a charging, another is to the load supplying.
Optionally, the bias current generation module includes sampling resistor, trsanscondutance amplifier, the first transistor, the second crystalline substance
Body pipe and fixed bias current source；
The sampling resistor and the load in series, are converted for sampling the electric current in the load, and by the electric current
For voltage；
One input terminal of the trsanscondutance amplifier is connected with one end of the sampling resistor, the trsanscondutance amplifier it is another
One input terminal is connected with the other end of the sampling resistor, and the trsanscondutance amplifier is used to turn the voltage of the sampling resistor
It is changed to electric current；
The first end of the first transistor is connected with the first end of the second transistor, the grid of the first transistor
Pole is connected with the grid of the second transistor, the grid phase of the second end of the first transistor and the first transistor
Even, and the second end of the first transistor is connected with an output end of the trsanscondutance amplifier, the trsanscondutance amplifier
Another output ground connection；The electricity that the first transistor and the second transistor are used to be exported according to the trsanscondutance amplifier
The raw image current of miscarriage；
The one end in the fixed bias current source is connected with the first end of the second transistor, the fixed bias current
The other end in source is connected with the second end of the second transistor, so that the fixed bias electricity of fixed bias current source output
Stream is superimposed to form the bias current with the image current.
Optionally, the first transistor and the second transistor are PMOS transistor.
Optionally, the clock signal generating module includes comparator, the first phase inverter, the second phase inverter and third electricity
Hold；
The first input end of the comparator is connected with the second end of the second transistor, and the second of the comparator is defeated
Enter end to be connected with reference voltage, and the first input end of the comparator passes through the third capacity earth；
The output end of the comparator is produced by first phase inverter and second phase inverter and the clock signal
The output end of raw module is connected.
Optionally, the charge and discharge control module includes third phase inverter, the 4th phase inverter, third transistor to the 6th crystalline substance
Body pipe；
The input terminal of the third phase inverter is connected with the output end of the clock signal generating module, the third reverse phase
The output end of device is connected with one end of the first capacitor, the grid of the other end of the first capacitor and the third transistor
It is connected；
The input terminal of 4th phase inverter is connected with the output end of the third phase inverter, the 4th phase inverter it is defeated
Outlet is connected with one end of second capacitor, and the other end of second capacitor is connected with the grid of the 4th transistor；
The first end of the third transistor is connected with the first end of the 4th transistor, and the of the third transistor
Two ends are connected with the grid of the 4th transistor, and the first end phase of the second end of the third transistor and the 5th transistor
Even, the grid of the 5th transistor is connected with the grid of the third transistor, the second end and electricity of the 5th transistor
Source is connected；
The second end of 4th transistor is connected with the grid of the third transistor, and the second of the 4th transistor
End is connected with the 6th transistor first end, and the grid of the 6th transistor is connected with the grid of the 4th transistor,
The second end of 6th transistor is connected with the second end of the 5th transistor；
The first end of the third transistor is connected with the output end of the charge and discharge control module, the charge and discharge control
The output end of module is connected with the load.
Optionally, the third transistor and the 4th transistor are PMOS transistor, the 5th transistor and institute
Stating the 6th transistor is NMOS transistor.
Compared with prior art, the technical scheme provided by the invention has the following advantages:
Charge pump circuit provided by the present invention, the electric current that the sampling of bias current generation module loads, and according to sampling
Electric current generate bias current, clock signal generating module according to bias current generate clock signal, when the load, sampling
Load on electric current and bias current can corresponding change so that the frequency of clock signal generated may also change accordingly, thus
So that ripple voltage reduces or remains unchanged, so that the voltage fluctuation in load reduces.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of existing structural schematic diagram of charge pump；
Fig. 2 is a kind of structural schematic diagram of charge pump circuit provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of charge pump circuit and clock signal generating module provided in an embodiment of the present invention；
Fig. 4 is the ripple characteristics figure of output voltage provided in an embodiment of the present invention.
Specific embodiment
As described in background, in existing charge pump, when the load of charge pump reduces, charge pump output is generated
Ripple voltage will increase, and cause the voltage fluctuation in load too big.Inventor is the study found that the reason of causing this problem is main
It is that the period for the clock signal that the clock signal generating module in existing charge pump generates is fixed.
As shown in Figure 1, clock signal generating module is generated according to the fixed current of fixed bias current source IB output
The signal of fixed cycle is as clock signal clk, and when clock signal clk is high level, CLK1 is low level, and CLK2 is
High level.Because first capacitor C1 and the voltage at the second both ends capacitor C2 cannot be mutated, VA1=VIN, VA2=2VIN, this
When, the voltage of node A1 is pulled to V by transistor MN2 conductingIN, so that transistor MN1 is turned off, and transistor MP1 conducting, transistor
MP2 shutdown, at this point, the second capacitor C2 passes through transistor MP1 to load RLPower supply, VINEnd passes through transistor MN2 to first capacitor
C1 charging；When clock signal clk is low level, CLK1 is high level, and CLK2 is low level, at this point, VA1=2VIN, VA2=
VIN, transistor MN1 open, the grid of transistor MP2 is pulled to VIN, so that transistor MP2 is connected, first capacitor C1 passes through crystalline substance
Body pipe MP2 to load RLPower supply.
It follows that output voltageBecause charge pump is to be carried out using capacitor charge and discharge to load
Power supply, therefore, the process of charge and discharge can make output voltage VOUTRipple is generated, i.e. generation ripple voltage Vripple, and
Since the clock cycle f of clock signal clk is fixed value, as load RLWhen fixed, R is loadedLOn electric current
ILIt is fixed value, according to above-mentioned formula it is found that ripple voltage VrippleIt is also fixed value.But as load RLBecome smaller, load RLOn
Electric current ILWhen becoming larger, ripple voltage VrippleAlso it can become larger, cause to load RLOn voltage fluctuation it is too big.
Based on this, the present invention provides a kind of charge pump circuit, to overcome the above problem of the existing technology, including when
Clock signal generator module, first capacitor, the second capacitor, charge and discharge control module and bias current generation module；
The bias current generation module is used to sample the electric current in load, and generates biasing according to the electric current of the sampling
Electric current；
The clock signal generating module is used to generate clock signal according to the bias current；
The charge and discharge control module is used to control the first capacitor and second capacitor according to the clock signal
In a charging, another is to the load supplying.
Charge pump circuit provided by the invention, the electric current that the sampling of bias current generation module loads, and according to sampling
Electric current generates bias current, and clock signal generating module generates clock signal, when the load, sampling according to bias current
Electric current and bias current meeting corresponding change in load, so that the frequency of the clock signal generated may also change accordingly, to make
It obtains ripple voltage to reduce or remain unchanged, so that the voltage fluctuation in load reduces.
It is core of the invention thought above, to keep the above objects, features and advantages of the present invention more obvious easily
Understand, following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention is clearly and completely retouched
It states, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based on the present invention
In embodiment, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a kind of charge pump circuit, the charge pump circuit can be widely applied to power transmitter,
In overvoltage protector and signal transmission chip, as shown in Fig. 2, the charge pump circuit includes clock signal generating module, the first electricity
Hold C1, the second capacitor C2, charge and discharge control module and bias current generation module.
Wherein, bias current generation module is for sampling load RLOn electric current IL, and according to the electric current I of samplingLIt generates inclined
Set electric current IIB_IN；Clock signal generating module is used for according to bias current IIB_INGenerate clock signal clk；Charge and discharge control mould
Block is used to be charged according to one in clock signal control first capacitor C1 and the second capacitor C2, another is to load RLPower supply.
In the embodiment of the present invention, R is loadedLWith load capacitance CLIt is in parallel；Bias current generation module includes sampling resistor RSNS、
Trsanscondutance amplifier GM, the first transistor M1, second transistor M2 and fixed bias current source IB1.
Sampling resistor RSNSWith load RLSeries connection, for sampling load RLOn electric current, and convert electrical current into voltage；Mutual conductance
Amplifier GMAn input terminal and sampling resistor RSNSOne end be connected, trsanscondutance amplifier GMAnother input terminal and sampling electricity
Hinder RSNSThe other end be connected, trsanscondutance amplifier GMFor by sampling resistor RSNSVoltage be converted to electric current.
The first end of the first transistor M1 is connected with the first end of second transistor M2, the grid of the first transistor M1 and
The grid of two-transistor M2 is connected, and the second end of the first transistor M1 is connected with the grid of the first transistor M1, and first crystal
The second end and trsanscondutance amplifier G of pipe M1MAn output end be connected, trsanscondutance amplifier GMAnother output ground connection；First
Transistor M1 and second transistor M2 is used for according to trsanscondutance amplifier GMThe electric current of output generates image current IACT, mirror image electricity
Flow IACTWith load RLOn electric current ILIt is positively correlated.
One end of fixed bias current source IB1 is connected with the first end of second transistor M2, fixed bias current source IB1's
The other end is connected with the second end of second transistor M2, so that the fixed bias current I of fixed bias current source IB1 outputB1With
Image current IACTSuperposition forms bias current IIB_IN=IB1+IACT。
In the embodiment of the present invention, as shown in figure 3, clock signal generating module includes comparator COMP, the first phase inverter
INV1, the second phase inverter INV2 and third capacitor CCLK；The first input end of comparator COMP and the second end of second transistor M2
It is connected, the second input terminal and reference voltage V of comparator COMPCLKIt is connected, and the first input end of comparator COMP passes through third
Capacitor CCLKGround connection；The output end of comparator COMP is produced by the first phase inverter INV1 and the second phase inverter INV2 and clock signal
The output end of raw module is connected.
As shown in Figures 2 and 3, charge and discharge control module includes third phase inverter INV3, the 4th phase inverter INV4, third crystalline substance
Body pipe M3 to the 6th transistor M6；The input terminal of third phase inverter INV3 is connected with the output end of clock signal generating module, the
The output end of three phase inverter INV3 is connected with one end of first capacitor C1, and the other end of first capacitor C1 is with third transistor M3's
Grid is connected；The input terminal of 4th phase inverter INV4 is connected with the output end of third phase inverter INV3, the 4th phase inverter INV4's
Output end is connected with one end of the second capacitor C2, and the other end of the second capacitor C2 is connected with the grid of the 4th transistor M4；Third
The first end of transistor M3 is connected with the first end of the 4th transistor M4, the second end of third transistor M3 and the 4th transistor M4
Grid be connected, and the second end of third transistor M3 is connected with the first end of the 5th transistor M5, the grid of the 5th transistor M5
Pole is connected with the grid of third transistor M3, the second end and power end V of the 5th transistor M5INIt is connected；4th transistor M4's
Second end is connected with the grid of third transistor M3, and the second end of the 4th transistor M4 is connected with the 6th transistor M6 first end,
The grid of 6th transistor M6 is connected with the grid of the 4th transistor M4, the second end and the 5th transistor M5 of the 6th transistor M6
Second end be connected；The first end of third transistor M3 is connected with the output end of charge and discharge control module, charge and discharge control module
Output end and load RLIt is connected.
It should be noted that in the embodiment of the present invention, the first transistor M1, second transistor M2, third transistor M3 and
4th transistor M4 is PMOS transistor, and the 5th transistor M5 and the 6th transistor M6 are NMOS transistor.Certainly, this hair
It is only illustrated as example in bright embodiment, it is not limited to this.
When clock signal clk be high level when, third phase inverter INV3 output clock signal clk 1 be low level, the 4th
The clock signal clk 2 of phase inverter INV4 output is high level.Because first capacitor C1 and the voltage at the second both ends capacitor C2 cannot
Mutation, therefore, VA1=VIN, VA2=2VIN, at this point, the 6th transistor M6 is connected, the voltage of node A1 is pulled to VIN, so that the
Five transistor M5 shutdown, third transistor M3 conducting, the 4th transistor M4 shutdown, at this point, the second capacitor C2 passes through third crystal
Pipe M3 to load RLPower supply, VINIt is charged by the 6th transistor M6 to first capacitor C1 at end.
When clock signal clk be low level when, third phase inverter INV3 output clock signal clk 1 be high level, the 4th
The clock signal clk 2 of phase inverter INV4 output is low level, at this point, VA1=2VIN, VA2=VIN, the 5th transistor M5 unlatching will
The grid of 4th transistor M4 is pulled to VIN, so that the 4th transistor M4 is connected, first capacitor C1 is by the 4th transistor M4 to negative
Carry RLPower supply.
If N is the breadth length ratio of the first transistor M1 or second transistor M2, then image current IACT=N*IL*RSNS*gm,
In, gmFor trsanscondutance amplifier GMEquivalent transconductance.Therefore, the frequency for the clock signal that clock signal generating module generatesWherein, CCLK、VCLK、RSNS、gm、IB1It is all fixed value, charge with N
Pump circuit output voltage VOUTRipple voltage
According to the formula it is found that as load RLWhen reduction, the load R of samplingLOn electric current ILWith bias current IIB_INIt can increase
Greatly, so that the frequency f of the clock signal generatedCLKAlso it will increase, at this point, the charge/discharge speed meeting of first capacitor and the second capacitor
Accelerate, so that ripple voltage VrippleReduce, so that load RLOn voltage fluctuation reduce.
As load RLWhen constant, the load R of samplingLOn electric current ILWith bias current IIB_INIt is constant, so that the clock generated
The frequency f of signalCLKAlso it immobilizes, ripple voltage VrippleAlso it immobilizes.
As load RLWhen increase, the load R of samplingLOn electric current ILWith bias current IIB_INReduce, so that the clock generated
The frequency f of signalCLKReduce, lower power consumption, so that ripple voltage VrippleIt remains unchanged, so that load RLOn voltage wave
It is dynamic to reduce.
With reference to Fig. 4, Fig. 4 is the output voltage V of traditional charge pumpOUT1With charge pump circuit provided in an embodiment of the present invention
Output voltage VOUT2Ripple characteristics figure, when load current IL becomes larger suddenly, charge pump provided in an embodiment of the present invention electricity
The frequency f on roadCLKAlso can become larger, output ripple can reduce, provided in an embodiment of the present invention when load current IL becomes smaller suddenly
The frequency f of charge pump circuitCLKAlso can become smaller, lower power consumption, while output ripple remains unchanged.
That is, charge pump circuit provided in an embodiment of the present invention can be according to load RL size, in other words according to negative
The electric current IL size on RL is carried, dynamic adjusts the frequency f of clock signalCLK, to reduce output ripple, improve charge pump circuit
Whole efficiency, expand the application range of charge pump circuit.Therefore, charge pump circuit provided in an embodiment of the present invention has output
Small, the high-efficient and low in energy consumption characteristic of ripple.
Charge pump circuit provided by the present invention, the electric current that the sampling of bias current generation module loads, and according to sampling
Electric current generate bias current, clock signal generating module according to bias current generate clock signal, when the load, sampling
Load on electric current and bias current can corresponding change so that the frequency of clock signal generated may also change accordingly, thus
So that ripple voltage reduces or remains unchanged, so that the voltage fluctuation in load reduces.
Each embodiment in this specification is described in a progressive manner, the highlights of each of the examples are with other
The difference of embodiment, the same or similar parts in each embodiment may refer to each other.To the upper of the disclosed embodiments
It states bright, enables those skilled in the art to implement or use the present invention.Various modifications to these embodiments are to ability
Will be apparent for the professional technician in domain, the general principles defined herein can not depart from it is of the invention
In the case where spirit or scope, realize in other embodiments.Therefore, the present invention be not intended to be limited to it is shown in this article these
Embodiment, and it is to fit to the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. a kind of charge pump circuit, which is characterized in that including clock signal generating module, first capacitor, the second capacitor, charge and discharge
Control module and bias current generation module；
The bias current generation module is used to sample the electric current in load, and generates biased electrical according to the electric current of the sampling
Stream；
The clock signal generating module is used to generate clock signal according to the bias current；
The charge and discharge control module according to the clock signal for controlling in the first capacitor and second capacitor
One charging, another is to the load supplying.
2. circuit according to claim 1, which is characterized in that the bias current generation module include sampling resistor, across
Lead amplifier, the first transistor, second transistor and fixed bias current source；
The sampling resistor and the load in series, are converted to electricity for sampling the electric current in the load, and by the electric current
Pressure；
One input terminal of the trsanscondutance amplifier is connected with one end of the sampling resistor, the trsanscondutance amplifier another
Input terminal is connected with the other end of the sampling resistor, and the trsanscondutance amplifier is for being converted to the voltage of the sampling resistor
Electric current；
The first end of the first transistor is connected with the first end of the second transistor, the grid of the first transistor with
The grid of the second transistor is connected, and the second end of the first transistor is connected with the grid of the first transistor, and
The second end of the first transistor is connected with an output end of the trsanscondutance amplifier, the trsanscondutance amplifier another
Output end ground connection；The electric current that the first transistor and the second transistor are used to be exported according to the trsanscondutance amplifier generates
Image current；
The one end in the fixed bias current source is connected with the first end of the second transistor, the fixed bias current source
The other end is connected with the second end of the second transistor so that the fixed bias current source output fixed bias current with
The image current is superimposed to form the bias current.
3. circuit according to claim 2, which is characterized in that the first transistor and the second transistor are PMOS
Transistor.
4. circuit according to claim 2, which is characterized in that the clock signal generating module includes comparator, first
Phase inverter, the second phase inverter and third capacitor；
The first input end of the comparator is connected with the second end of the second transistor, the second input terminal of the comparator
It is connected with reference voltage, and the first input end of the comparator passes through the third capacity earth；
The output end of the comparator generates mould by first phase inverter and second phase inverter and the clock signal
The output end of block is connected.
5. circuit according to claim 4, which is characterized in that the charge and discharge control module includes third phase inverter,
Four phase inverters, third transistor to the 6th transistor；
The input terminal of the third phase inverter is connected with the output end of the clock signal generating module, the third phase inverter
Output end is connected with one end of the first capacitor, the grid phase of the other end of the first capacitor and the third transistor
Even；
The input terminal of 4th phase inverter is connected with the output end of the third phase inverter, the output end of the 4th phase inverter
It is connected with one end of second capacitor, the other end of second capacitor is connected with the grid of the 4th transistor；
The first end of the third transistor is connected with the first end of the 4th transistor, the second end of the third transistor
It is connected with the grid of the 4th transistor, and the second end of the third transistor is connected with the first end of the 5th transistor,
The grid of 5th transistor is connected with the grid of the third transistor, the second end and power end of the 5th transistor
It is connected；
The second end of 4th transistor is connected with the grid of the third transistor, the second end of the 4th transistor with
The 6th transistor first end is connected, and the grid of the 6th transistor is connected with the grid of the 4th transistor, described
The second end of 6th transistor is connected with the second end of the 5th transistor；
The first end of the third transistor is connected with the output end of the charge and discharge control module, the charge and discharge control module
Output end with it is described load be connected.
6. circuit according to claim 5, which is characterized in that the third transistor and the 4th transistor are PMOS
Transistor, the 5th transistor and the 6th transistor are NMOS transistor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| PCT/CN2020/072162 WO2020151540A1 (en) | 2019-01-22 | 2020-01-15 | Charge pump circuit and method for controlling ripple voltage of charge pump circuit |
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| WO2020151540A1 (en) * | 2019-01-22 | 2020-07-30 | 上海艾为电子技术股份有限公司 | Charge pump circuit and method for controlling ripple voltage of charge pump circuit |
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| CN109639135B (en) | 2024-03-01 |
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