CN108418418A - A kind of adaptive bi-directional charge pump dynamic regulator for this body bias of metal-oxide-semiconductor - Google Patents
A kind of adaptive bi-directional charge pump dynamic regulator for this body bias of metal-oxide-semiconductor Download PDFInfo
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- CN108418418A CN108418418A CN201810181530.9A CN201810181530A CN108418418A CN 108418418 A CN108418418 A CN 108418418A CN 201810181530 A CN201810181530 A CN 201810181530A CN 108418418 A CN108418418 A CN 108418418A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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Abstract
The invention discloses a kind of adaptive bi-directional charge pump dynamic regulators for this body bias of metal-oxide-semiconductor, the adjuster includes NMOS automatic adjusuments circuit, PMOS automatic adjusuments circuit and system digits logic, and the NMOS automatic adjusuments circuit includes that there are one oscillator clock, frequency current converter, quantization and D/A converting circuit, integrator and the charge pumps for biasing NMOS；The PMOS automatic adjusuments circuit include there are one oscillator clock, frequency current converter, quantization and D/A converting circuit, integrator and bias PMOS charge pump；The charge pump of the biasing NMOS and the charge pump of bias PMOS are connected to system digits logic, to realize that NMOS and PMOS threshold values are stablized.
Description
Technical field
The invention belongs to technical field of integrated circuits, more particularly to are specifically applied to the adaptive of CMOS transistor this body bias
Bi-directional charge is answered to pump dynamic regulation.
Background technology
As super large-scale integration manufacturing process receives the developing in depth and breadth of micron to depth, the diminution of device feature size is permitted
Perhaps more transistor units are integrated in integrated circuit (IC) system.But the even integrated electricity based on same manufacturing process
Road chip, due to the technique angular displacement that industrial manufacturing process is brought make the threshold value of the MOS transistor on same wafer have it is high, have
It is low：High threshold band comes lower leakage current, lower power consumption, but the maximum operational speed of system is limited；Low threshold value is advantageous
In the promotion of system running speed, cost is to generate higher leakage current, higher power consumption.By to MOS transistor ontology into
Its threshold value can be arranged in row fixed bias.Although this is a useful technology, in some applications, further dynamic regulation
The threshold value of MOS transistor reduces its discreteness, still has very much to make system self-adaption make balance between speed and power consumption
Meaning.
As patent application 201510672250.4 discloses a kind of system for the electromagnetic interference reducing switching power source chip, packet
Include voltage regulator, reset circuit, bias voltage generation module and oscillator module, the VRM Voltage Regulator Module respectively with partially
It sets voltage generating module with oscillator module to be connected, bias voltage generation module is connected with oscillator, reset circuit and oscillator
Module is connected.The system of the electromagnetic interference of the reduction switching power source chip of the present invention can not only inhibit Conduction Interference in source, and
And EMI filter part sizes are considerably reduced, reduce the shielding material for inhibiting radiation EMI.
However, in the above technical solution, the generation of bias voltage is only to act on oscillator, for MOS crystal
The further development that the ontology of pipe carries out the control technology of dynamic bias is needed.
Invention content
Based on this, therefore the primary mesh of the present invention be to provide a kind of adaptive two-way electricity for metal-oxide-semiconductor this body bias
Lotus pumps dynamic regulator, which realizes that metal-oxide-semiconductor threshold value is flexibly controllable by adaptive bi-directional charge pump, first pass through one
Carry out detection threshold value with the associated circular type shaker frequency variation of metal-oxide-semiconductor threshold value, and frequency signal is converted into current signal, it will be electric
Stream signal compares acquisition difference with reference signal, and then carries out quantization integral, and it is inclined finally to control charge pump output generation ontology
It sets voltage and carries out dynamic regulation.
Another mesh of the present invention it is to provide a kind of adaptive bi-directional charge pump dynamic for this body bias of metal-oxide-semiconductor
Adjuster, the adjuster can effectively eliminate the influence that NMOS, PMOS changes of threshold are brought so that circuit system is operated in most
Good speed-power-consumption balance state, to promote chip overall permanence.
To achieve the above object, the technical scheme is that：
A kind of adaptive bi-directional charge pump dynamic regulator for this body bias of metal-oxide-semiconductor, it is characterised in that the adjusting
Device includes NMOS automatic adjusuments circuit, PMOS automatic adjusuments circuit and system digits logic, and the NMOS is adaptively adjusted
Road economize on electricity including there are one oscillator clock, frequency-current converter, quantization and D/A converting circuit, integrator and biasings
The charge pump of NMOS；The PMOS automatic adjusuments circuit includes that there are one oscillator clock, frequency-current converter, quantizations
With the charge pump of D/A converting circuit, integrator and bias PMOS；The charge of the charge pump and bias PMOS of the biasing NMOS
Pump is connected to system digits logic, to realize that NMOS and PMOS threshold values are stablized.
Specifically, the circular type shaker of association NMOS threshold values exports one with the relevant oscillator clock CK of NMOS threshold values
(n), corresponding current signal I_freq_to_current (n), benchmark electricity then by a frequency-current converter are obtained
Stream signal Iref (n) does difference with the current signal and carries out quantization and digital-to-analogue conversion generation Vadj (n), and Vadj (n) is input to
Integrator carries out integral output Vintegrator (n), and then the charge pump for controlling biasing NMOS ontologies exports Vneg；Work as NMOS
Threshold value becomes smaller (or becoming larger), and output CK (n) frequencies of oscillator can and then become faster (or slack-off), frequency-current converter output
Switching current I_freq_to_current (n) become larger (or becoming smaller), the difference of Iref (n) and I_freq_to_current (n)
Value becomes smaller (or becoming larger), and difference carries out quantization and the transformed voltage signal Vadj (n) of digital-to-analogue becomes smaller (or becoming larger), and integrator is defeated
Go out Vintegrator (n) to become smaller (or becoming larger), to make the charge pump Vneg of biasing NMOS ontologies become smaller (or becoming larger)；Pass through
The threshold value of the control of Vneg, NMOS can become larger (or becoming smaller) with the fluctuation before making up accordingly, and then realize that NMOS threshold values are steady
It is fixed.
Similarly, the circular type shaker of association PMOS threshold values exports one with the relevant oscillator clock CK (p) of PMOS threshold values,
Corresponding current signal I_freq_to_current (p) is obtained by a frequency-current converter again, the current signal
Difference is done with reference current signal Iref (p) and carries out quantization and digital-to-analogue conversion generation Vadj (p), and Vadj (p) is input to integral
Device carries out integral output Vintegrator (p) and then controls the charge pump output Vpeg of bias PMOS ontology.When PMOS threshold values become
Output CK (p) frequencies of small (or becoming larger), oscillator can and then become faster (or slack-off), the conversion of frequency-current converter output
Electric current I_freq_to_current (p) becomes larger (or becoming smaller), and the difference of I_freq_to_current (p) and Iref (p) becomes larger
(or becoming smaller), difference carries out quantization and the transformed voltage signal Vadj (p) of digital-to-analogue becomes larger (or becoming smaller), integrator output
Vintegrator (p) and then becomes larger (or becoming smaller), to make the charge pump Vpeg of bias PMOS ontology become larger (or becoming smaller).It is logical
The control of Vpeg is crossed, the threshold value of PMOS can become larger (or becoming smaller) with the fluctuation before making up accordingly, and then realize PMOS threshold values
Stablize.
This bias voltage can dynamically be arranged to less than in the source of PMOS transistor by the charge pump of the PMOS ontologies
Voltage at pole carries out forward bias to the ontology of pair pmos transistor；Or this bias voltage is disposed above
Voltage at the source electrode of PMOS transistor carries out reverse bias to the ontology of pair pmos transistor.
This bias voltage can also be dynamically disposed above in NMOS transistor by the charge pump of the NMOS ontologies
Voltage at source electrode carries out forward bias to the ontology of pair nmos transistor；Or this bias voltage is arranged to be less than
Voltage at the source electrode of NMOS transistor carries out reverse bias to the ontology of pair nmos transistor.
Adjuster of the present invention realizes that metal-oxide-semiconductor threshold value is flexibly controllable by adaptive bi-directional charge pump, first passes through
One is carried out detection threshold value with the associated circular type shaker frequency variation of metal-oxide-semiconductor threshold value, and frequency signal is converted to current signal,
Current signal and reference signal are compared into acquisition difference, and then carry out quantization integral, charge pump output is finally controlled and generates this
Bias voltage carries out dynamic regulation.
Moreover, the present invention can effectively eliminate the influence that NMOS, PMOS changes of threshold are brought so that circuit system works
In best speed-power-consumption balance state, to promote chip overall permanence.
Description of the drawings
Fig. 1 is the system architecture block diagram that the present invention is implemented.
Fig. 2 is that the present invention implements a kind of circuit diagram of biasing NMOS ontologies.
Fig. 3 is that the present invention implements the circuit diagram for being associated with the circular type shaker of NMOS threshold values.
Fig. 4 is the circuit diagram of the implemented frequency-current converter of the present invention.
Fig. 5 is that the present invention implements the circuit diagram for being associated with NMOS electric current quantizers.
Fig. 6 is the circuit diagram of the implemented integrator of the present invention.
Fig. 7 is that the present invention implements to bias the circuit diagram of the charge pump of NMOS ontologies.
Fig. 8 is the circuit diagram of the implemented system digits logic NMOS tube of the present invention.
Fig. 9 is that the present invention implements entire this body bias of NMOS response process oscillogram.
Figure 10 is the circuit diagram that the present invention implements another bias PMOS ontology.
Figure 11 is that the present invention implements the circuit diagram for being associated with the circular type shaker of PMOS threshold values.
Figure 12 is that the present invention implements the circuit diagram for being associated with PMOS electric current quantizers.
Figure 13 is the circuit diagram of the charge pump of the implemented bias PMOS ontology of the present invention.
Figure 14 is that the present invention implements entire this body bias of PMOS response process oscillogram.
Specific implementation mode
In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Shown in Fig. 1, for the adaptive dynamic regulator for this body bias of metal-oxide-semiconductor that the present invention is realized, the adjusting
Device includes NMOS automatic adjusuments circuit, PMOS automatic adjusuments circuit and system digits logic, and the NMOS is adaptively adjusted
Road economize on electricity including there are one oscillator clock, frequency-current converter, quantization and D/A converting circuit, integrator and biasings
The charge pump of NMOS；The PMOS automatic adjusuments circuit includes that there are one oscillator clock, frequency-current converter, quantizations
With the charge pump of D/A converting circuit, integrator and bias PMOS；The charge of the charge pump and bias PMOS of the biasing NMOS
Pump is connected to system digits logic, to realize that NMOS and PMOS threshold values are stablized.
The circular type shaker for being associated with NMOS threshold values exports one with the relevant oscillator clock CK (n) of NMOS threshold values, then leads to
It crosses a frequency-current converter and obtains corresponding current signal I_freq_to_current (n), reference current signal
Iref (n) does difference with the current signal and carries out quantization and digital-to-analogue conversion generation Vadj (n), and Vadj (n) is input to integrator
Integral output Vintegrator (n) is carried out, and then the charge pump for controlling biasing NMOS ontologies exports Vneg；When NMOS threshold values become
Output CK (n) frequencies of small (or becoming larger), oscillator can and then become faster (or slack-off), the conversion of frequency-current converter output
Electric current I_freq_to_current (n) becomes larger (or becoming smaller), and the difference of Iref (n) and I_freq_to_current (n) becomes smaller
(or becoming larger), difference carries out quantization and the transformed voltage signal Vadj (n) of digital-to-analogue becomes smaller (or becoming larger), integrator output
Vintegrator (n) becomes smaller (or becoming larger), to make the charge pump Vneg of biasing NMOS ontologies become smaller (or becoming larger)；Pass through
The threshold value of the control of Vneg, NMOS can become larger (or becoming smaller) with the fluctuation before making up accordingly, and then realize that NMOS threshold values are steady
It is fixed.
Similarly, the circular type shaker of association PMOS threshold values exports one with the relevant oscillator clock CK (p) of PMOS threshold values,
Corresponding current signal I_freq_to_current (p) is obtained by a frequency-current converter again, the current signal
Difference is done with reference current signal Iref (p) and carries out quantization and digital-to-analogue conversion generation Vadj (p), and Vadj (p) is input to integral
Device carries out integral output Vintegrator (p) and then controls the charge pump output Vpeg of bias PMOS ontology.When PMOS threshold values become
Output CK (p) frequencies of small (or becoming larger), oscillator can and then become faster (or slack-off), the conversion of frequency-current converter output
Electric current I_freq_to_current (p) becomes larger (or becoming smaller), and the difference of I_freq_to_current (p) and Iref (p) becomes larger
(or becoming smaller), difference carries out quantization and the transformed voltage signal Vadj (p) of digital-to-analogue becomes larger (or becoming smaller), integrator output
Vintegrator (p) and then becomes larger (or becoming smaller), to make the charge pump Vpeg of bias PMOS ontology become larger (or becoming smaller).It is logical
The control of Vpeg is crossed, the threshold value of PMOS can become larger (or becoming smaller) with the fluctuation before making up accordingly, and then realize PMOS threshold values
Stablize.
By taking NMOS this body bias processes as an example, detailed implementation is as follows：
Fig. 2 is a kind of concrete application mode that the present invention is realized, Fig. 3 is that NMOS threshold values are associated in application shown in Fig. 2
Multi-level differential can be used to circular type shaker in circular type shaker, and series is even number.
As shown in figure 3, differential levels basic unit is configured to：M1, M2 are difference PMOS input pipes, the source electrode and tail of M1, M2
The one end current source Iss is connected, and the tail current source Iss other ends come from power vd D；M3, M4 are the NMOS tube as load, M3, M4
Drain electrode and the drain electrode of M1, M2 be connected, and be connected to the grid of M5, M6；M5, M6 are the PMOS tube for being connected into capacitive form.M3, M4 sheet
Body bias is by inputting Vneg controls.
The frequency fosc of circular type shaker is related with cascade delay, as follows with the threshold value relationship of M3, M4：
fosc∝1/TD∝Un*Cox*(W/L)3,4*(Vb-Vthn)/Up*Cox*(W/L)5,6
∝Un*(W/L)3,4*(Vb-Vthn)/Up*(W/L)5,6
Un, Up are surface mobilities, and Cox is capacitive oxide, and W is NMOS, PMOS tube width, and L is NMOS, PMOS tube
Length, Vthn are the threshold values of NMOS tube, and Vb, which is fixed bias voltage, makes M3, M4 be operated in linear zone.
When NMOS threshold values Vthn becomes smaller, then oscillator fosc frequencies become faster, conversely, oscillator frequency is then slack-off.
The circular type shaker output CK (ring_osc) of association NMOS threshold values is connected to frequency-current converter, can be used
Structure it is as shown in Figure 4.
When CK is high, Sc0, Sc2, Sc4 switch conductions, Sc1, Sc3, which is switched, to be ended, and Cc1 discharges into ground, Cc2 by Sc0
The negative terminal of amplifier A1 is connected to by switch Sc2, the voltage that previous moment is stored in the charge generation of capacitance Cc2 does ratio with Vmid
Compared with generation control voltage VN2 generates electric current Ic4 by Mc1 and Rc1 and flows through Sc4 switches.When CK is low, Sc0, Sc2, Sc4
Switch cut-off, Sc1, Sc3 switch conductions, the voltage on VN2 is constant, and generating electric current Ic3 by Mc1 and Rc1 flows through Sc3 switches,
Ic3 is equal with the Ic4 electric currents of previous moment (when CK is high), and Ic3 maps generation Ic0 by current mirror 2 and charges to Cc1 and Cc2.
It it is low this section of moment (half of circular type shaker period 1/ (2*fosc)) in CK, Cc1 and Cc2 can be charged to Ic0/ [2*fosc*
(Cc1+Cc2)].When CK is again high, Cc2 is switched to the negative terminal of amplifier A1, and previous moment is stored in the charge production of capacitance Cc2
Raw voltage Ic0/ [2*fosc* (Cc1+Cc2)] is compared with Vmid, to generate new control voltage VN2 and control electric current
Ic4.It is fed back eventually by whole system, Ic0/ [2*fosc* (Cc1+Cc2)], Ic0=[2*fosc* equal with Vmid voltages
(Cc1+Cc2)]*Vmid.Therefore, when CK is high, Ic0=0, Ic3=0, Ic4 ∝ fosc；When CK is low, Ic0 ∝ fosc,
Ic3 ∝ fosc, Ic4=0；Ic1 ∝ Ic4, Ic2 ∝ Ic3, I_freq_to_current=Ic1+ are generated by current mirror 1,2
Ic2, therefore, in the entire CK clock cycle, I_freq_to_current ∝ fosc.
Output I_freq_to_current and the Iref of frequency-current converter do relatively, taking-up difference (Iref-I_
Freq_to_current quantization and digital-to-analogue conversion) are carried out, as shown in Figure 5.
Iref is reference current, pair it is contemplated that NMOS baseline thresholds Vthn_ref.For given NMOS, such as its threshold value
It is expected to Vthn_ref, has corresponding CK_ref (ring_osc) output in Fig. 3, is had by Fig. 4 frequencies-electric current conversion a
Reference current exports I_freq_to_current_ref, therefore can be arranged to Iref to work as I_freq_to_current_ref,
That is Iref=I_freq_to_current_ref ∝ CK_ref (ring_osc) ∝ (Vb-Vthn_ref).As NMOS threshold values Vthn
It shifts, respective change can be followed higher or lower than desired value Vthn_ref, I_freq_to_current.Work as I_freq_
To_current=Iref, N quantizer outputs are that intermediate code 1000...000, DAC output is fallen in axis Vmid；Work as I_
Freq_to_current is more than Iref to a certain extent, and N quantizer outputs are that maximum code 1111...111, DAC output is maximum
For Vmid+Vref；When I_freq_to_current is less than Iref to a certain extent, N quantizer outputs are minimum code
0000...000, DAC exports minimum Vmid-Vref；Therefore the fluctuation range of Vadj is [Vmid-Vref, Vmid+Vref].
DAC outputs Vadj in Fig. 5 is input to integrator and is integrated, and the basic structure of integrator is as shown in Figure 6：
When initial reset, Si0 conductings, N8 nodes are connected into buffer forms with output Vintegrator short circuits, amplifier A2,
Output Vintegrator is Vmid.Si0 ends after reset, when φ 1 is high, φ 2 is low, Si1, and Si2 switch conductions,
Ci1 both end voltages are charged to Vadj-Vmid by Si3, Si4 switch cut-off, Vadj by Si1, Si2；When φ 2 is high, φ 1 is low
When, Si3, Si4 switch conductions, Si1, Si2 switch cut-off, because of empty short equal, the Ci1 both end voltages of two input terminals of amplifier A2
Become Vmid-VN8, VN8=Vmid；Therefore, the charge variation on Ci1 is (Vmid-Vadj) * Ci1, exports Vintegrator
The respective change of voltage is：-(Vmid-Vadj)*Ci1/Ci2.It is constantly integrated by the difference of integrator, (Vadj-Vmid)
And it is reflected in output.
The output Vintegrator of integrator is connected to the charge pump (as shown in Figure 7) of a biasing NMOS ontology, works as φ
When 1 is high, φ 2 is low, S1, S2 conducting, S3, S4 end, and N9 is connected to power vd D, N10 and Vintegrator, C1 is followed to deposit at both ends
Storing up electricity lotus is C1* (VDD-Vintegrator)；When φ 2 is high, φ 1 is low, S3, S4 conducting, S1, S2 cut-off, N9 point voltages
For Vintegrator, it is finally defeated to the charge and discharge of load C L, RL by S4 that the both ends C1 store charge C1* (VDD-Vintegrator)
It is Vintegrator- (VDD-Vintegrator)=2*Vintegrator-VDD to go out Vneg；When Vintegrator is Vmid
When, export Vneg=2*Vintegrator-VDD=0；Work as Vintegrator>Vmid, then Vneg>0；Work as Vintegrator<
Vmid, then Vneg<0；Vintegrator is inputted by adjusting, Vneg will produce the voltage more than or less than 0, to control figure 8
NMOS body potentials in system digits logic realize that threshold value is adjusted.
Vneg outputs are connected to the circular type shaker of Fig. 3 association NMOS threshold values, when NMOS threshold values shift, i.e. in Fig. 3
M3, M4 threshold value shift, circular type shaker CK (ring_osc) and frequency-electric current export I_freq_to_current
Can respective offsets, handled by the difference to reference current Iref and I_freq_to_current (quantization, digital-to-analogue conversion,
Integral) to control the charge pump of biasing NMOS bulk voltages generate needed for M3 in bias voltage Vneg control circular type shaker,
M4 ontologies.When NMOS (M3, M4) threshold value is adjusted to desired value, I_freq_to_current=Iref, Vadj=Vmid, product
Device is divided to stop integral, Vintegrator maintains some voltage and Vneg=2*Vintegrator-VDD is allow to bias NMOS
Threshold value is to desired value.
Meanwhile Vneg can be connected to the ontology of Fig. 8 system digits logic NMOS tubes, be indicated for simplifying, Fig. 8 only lists crystalline substance
Body pipe T1, T2, T3, T4 and T5, T6, and actual electronic equipment can have any amount of transistor to Tn-1, Tn and not
Same combination.When in the range required for circular type shaker NMOS threshold values are eventually arrived at by Vneg controls, it is connected to Fig. 7 systems
The Vneg of system Digital Logic also can accordingly adjust NMOS threshold values to eliminate the speed or power consumption that NMOS threshold deviations are brought
Sacrifice, to meet the equalization requirement of system speed and power consumption.
Entire NMOS this body bias response process waveforms are as shown in Figure 9：
I_freq_to_current=Iref when stable state, Vadj=Vmid.In sometime (such as t1 moment) NMOS
Threshold value shifts, and instantaneous threshold value becomes larger, and circular type shaker CK (ring_osc) frequency of association NMOS threshold values ensues change
Change, Frequency downshift, the switching current I_freq_to_current of frequency-current converter output becomes smaller, Iref and I_freq_
The difference of to_current becomes larger, and difference carries out quantization and the transformed voltage signal Vadj of digital-to-analogue becomes larger, Vadj>Vmid,
(Vadj-Vmid) it is constantly integrated, integrator output Vintegrator gradually becomes larger, and biases the charge pump Vneg of NMOS ontologies
Also gradually become larger.With the increase of Vneg, NMOS source voltage and the Vneg voltage differences of circular type shaker become smaller, and threshold value can phase
That answers becomes smaller.As NMOS threshold values become smaller, circular type shaker CK (ring_osc) can become larger, and I_freq_to_current is followed
Become larger.When NMOS threshold values are dynamically adjusted to system feedback when corresponding frequency-electric current exports I_freq_to_current=Iref
Reach stable state, Vadj=Vmid, integrator stops integral, and Vintegrator maintains some voltage, and Vneg maintains some electricity
Pressure value makes NMOS threshold values turn desired value down.
It shifts in another moment (such as t2 moment) NMOS threshold value, instantaneous threshold value becomes smaller, association NMOS threshold values
Circular type shaker CK (ring_osc) frequency ensues variation, and frequency becomes faster, the switching current of frequency-current converter output
I_freq_to_current becomes larger, and the difference of Iref and I_freq_to_current become smaller, and difference carries out quantization and digital-to-analogue turns
Voltage signal Vadj after changing becomes smaller, Vadj<Vmid, (Vadj-Vmid) are constantly integrated, and integrator exports Vintegrator
Gradually become smaller, the charge pump Vneg of biasing NMOS ontologies also gradually becomes smaller.With the reduction of Vneg, the sources NMOS of circular type shaker
Pole tension becomes larger with Vneg voltage differences, and threshold value can become larger accordingly.As NMOS threshold values become larger, circular type shaker CK (ring_
Osc) can become smaller, I_freq_to_current and then becomes smaller.When NMOS threshold values are dynamically adjusted to corresponding frequency-electric current output
System feedback reaches stable state, Vadj=Vmid when I_freq_to_current=Iref, and integrator stops integral,
Vintegrator maintains some voltage, and Vneg maintains some voltage value and NMOS threshold values is made to increase to desired value.
This body bias of PMOS process (as shown in Figure 10) is similar to aforementioned this body bias of NMOS process, only circular type shaker
It is slightly distinguished with charge pump：Using the charge pump of the circular type shaker and bias PMOS ontology of association PMOS threshold values.
Figure 11 is the circular type shaker of the association PMOS threshold values in application shown in Figure 10, and multi-level differential can be used to ring-like
Oscillator, series are even number.
Differential levels basic unit is configured to：M1, M2 are difference NMOS input pipes, the source electrode and tail current source Iss mono- of M1, M2
End is connected, and the tail current source Iss other ends are from ground；M3, M4 are the PMOS tube as load, the drain electrode of M3, M4 and the leakage of M1, M2
Extremely it is connected, and is connected to the grid of M5, M6；M5, M6 are the NMOS tubes for being connected into capacitive form.This body bias of M3, M4 is by inputting Vpeg
Control.
The frequency of circular type shaker is related with cascade delay, as follows with the threshold value relationship of M3, M4：
fosc∝1/TD∝Up*Cox*(W/L)3,4*(VDD-Vb-|Vthp|)/Un*Cox*(W/L)5,6
∝Up*(W/L)3,4*(VDD-Vb-|Vthp|)/Un*(W/L)5,6
When PMOS threshold values Vthp becomes smaller, then oscillator fosc frequencies become faster, conversely, oscillator frequency is then slack-off.
The circular type shaker output CK (ring_osc) of association PMOS threshold values is connected to frequency-current converter, frequency-electric current
The structure that converter uses is identical as aforementioned (Fig. 4).Unlike NMOS this body bias processes：Fig. 4 frequencies-current converter
Output I_freq_to_current and Iref do compared with, take out reversed difference (I_freq_to_current-Iref) into
Row quantization and digital-to-analogue conversion, as shown in figure 12.
DAC outputs Vadj is connected to integrator and is integrated, and the basic structure of integrator still uses structure shown in earlier figures 6.
The output Vintegrator of integrator is connected to the charge pump (as shown in figure 13) of a bias PMOS ontology, when
When φ 1 is high, φ 2 is low, S1, S2 conducting, S3, S4 cut-off, with being connected to, N10 follows Vintegrator, the storage of the both ends C1 to N9
Charge is C1* (- Vintegrator)；When φ 2 is high, φ 1 is low, S3, S4 conducting, S1, S2 end, and N9 point voltages are
The both ends Vintegrator, C1 store charge C1* (0-Vintegrator), by S4 to the charge and discharge of load C L, RL.Final output
Vpeg is Vintegrator- (- Vintegrator)=2*Vintegrator；As Vintegrator=Vmid, output
Vpeg=2*Vintegrator=VDD；Work as Vintegrator>Vmid, then Vpeg>VDD；Work as Vintegrator<Vmid, then
Vpeg<VDD；Vintegrator is inputted by adjusting, Vpeg will produce the voltage more than or less than VDD, to control system number
PMOS body potentials in word logic realize that threshold value is adjusted.
Entire PMOS this body bias response process waveforms are as shown in figure 14：
I_freq_to_current=Iref when stable state, Vadj=Vmid.In sometime (such as t1 moment) PMOS
Threshold value shifts, and instantaneous threshold value becomes larger, and circular type shaker CK (ring_osc) frequency of association PMOS threshold values ensues change
Change, Frequency downshift, the switching current I_freq_to_current of frequency-current converter output becomes smaller, I_freq_to_
The difference of current and Iref becomes smaller, and difference carries out quantization and the transformed voltage signal Vadj of digital-to-analogue becomes smaller, Vadj<Vmid,
(Vadj-Vmid) it is constantly integrated, integrator output Vintegrator gradually becomes smaller, the charge pump Vpeg of bias PMOS ontology
Also gradually become smaller.With the reduction of Vpeg, Vpeg voltages and the pmos source voltage difference of circular type shaker become smaller, and threshold value can phase
That answers becomes smaller.As PMOS threshold values become smaller, circular type shaker CK (ring_osc) can become larger, and I_freq_to_current is followed
Become larger.When PMOS threshold values are dynamically adjusted to system feedback when corresponding frequency-electric current exports I_freq_to_current=Iref
Reach stable state, Vadj=Vmid, integrator stops integral, and Vintegrator maintains some voltage, and Vpeg maintains some electricity
Pressure value makes PMOS threshold values turn desired value down.
It shifts in another moment (such as t2 moment) PMOS threshold value, instantaneous threshold value becomes smaller, association PMOS threshold values
Circular type shaker CK (ring_osc) frequency ensues variation, and frequency becomes faster, the switching current of frequency-current converter output
I_freq_to_current becomes larger, and the difference of I_freq_to_current and Iref become larger, and difference carries out quantization and digital-to-analogue turns
Voltage signal Vadj after changing becomes larger, Vadj>Vmid, (Vadj-Vmid) are constantly integrated, and integrator exports Vintegrator
Gradually become larger, the charge pump Vpeg of bias PMOS ontology also gradually becomes larger.With the increase of Vpeg, the Vpeg electricity of circular type shaker
Pressure becomes larger with pmos source voltage difference, and threshold value can become larger accordingly.As PMOS threshold values become larger, circular type shaker CK (ring_
Osc) can become smaller, I_freq_to_current and then becomes smaller.When PMOS threshold values are dynamically adjusted to corresponding frequency-electric current output
System feedback reaches stable state, Vadj=Vmid when I_freq_to_current=Iref, and integrator stops integral,
Vintegrator maintains some voltage, and Vpeg maintains some voltage value and PMOS threshold values is made to increase to desired value.
The influence that NMOS, PMOS changes of threshold are brought effectively is eliminated by above-mentioned adaptive dynamic regulator so that is
System circuit is operated in best speed-power-consumption balance state, to promote chip overall permanence.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
All any modification, equivalent and improvement etc., should all be included in the protection scope of the present invention made by within refreshing and principle.
Claims (5)
1. a kind of adaptive bi-directional charge pump dynamic regulator for this body bias of metal-oxide-semiconductor, it is characterised in that the adjuster
Include NMOS automatic adjusuments circuit, PMOS automatic adjusuments circuit and system digits logic, the NMOS automatic adjusuments
Circuit includes that there are one oscillator clock, frequency-current converter, quantization and D/A converting circuit, integrator and biasing NMOS
Charge pump；The PMOS automatic adjusuments circuit includes that there are one oscillator clock, frequency-current converter, quantization sum numbers
The charge pump of analog conversion circuit, integrator and bias PMOS；The charge pump of the biasing NMOS and the charge pump of bias PMOS are equal
It is connected to system digits logic, to realize that NMOS and PMOS threshold values are stablized.
2. the adaptive bi-directional charge pump dynamic regulator for this body bias of metal-oxide-semiconductor, feature exist as described in claim 1
One is exported with the relevant oscillator clock CK (n) of NMOS threshold values in the circular type shaker of association NMOS threshold values, then passes through one
Frequency-current converter obtains corresponding current signal I_freq_to_current (n), reference current signal Iref (n) with
The current signal do difference and carry out quantization and digital-to-analogue conversion generate Vadj (n), Vadj (n) be input to integrator integrate it is defeated
Go out Vintegrator (n), and then the charge pump for controlling biasing NMOS ontologies exports Vneg；When NMOS threshold values become smaller or larger, shake
Swinging output CK (n) frequencies of device can and then become faster (or slack-off), the switching current I_freq_to_ of frequency-current converter output
Current (n) becomes larger (or becoming smaller), and the difference of Iref (n) and I_freq_to_current (n) becomes smaller or larger, and difference carries out
Quantization and the transformed voltage signal Vadj (n) of digital-to-analogue become smaller or larger, and integrator output Vintegrator (n) becomes smaller or becomes
Greatly, to make the charge pump Vneg of biasing NMOS ontologies become smaller or larger；By the control of Vneg, the threshold value of NMOS can be corresponding
Become larger or become smaller, with the fluctuation before making up, and then realizes that NMOS threshold values are stablized.
3. the adaptive bi-directional charge pump dynamic regulator for this body bias of metal-oxide-semiconductor, feature exist as described in claim 1
One is exported with the relevant oscillator clock CK (p) of PMOS threshold values in the circular type shaker of association PMOS threshold values, then passes through one
Frequency-current converter obtains corresponding current signal I_freq_to_current (p), the current signal and reference current
Signal Iref (p) does difference and carries out quantization and digital-to-analogue conversion generation Vadj (p), and Vadj (p) is input to integrator and is integrated
It exports Vintegrator (p) and then controls the charge pump output Vpeg of bias PMOS ontology；When PMOS threshold values become smaller or larger,
Output CK (p) frequencies of oscillator can and then become faster or slack-off, the switching current I_freq_to_ of frequency-current converter output
Current (p) becomes larger or becomes smaller, and the difference of I_freq_to_current (p) and Iref (p) becomes larger or becomes smaller, the difference amount of progress
Change and the transformed voltage signal Vadj (p) of digital-to-analogue become larger or become smaller, integrator output Vintegrator (p) and then become larger or
Become smaller, to make the charge pump Vpeg of bias PMOS ontology become larger or become smaller；By the control of Vpeg, the threshold value of PMOS can be corresponding
Become larger or become smaller, with the fluctuation before making up, and then realize that PMOS threshold values are stablized.
4. the adaptive bi-directional charge pump dynamic regulator for this body bias of metal-oxide-semiconductor, feature exist as claimed in claim 3
Dynamically this bias voltage can be arranged to less than at the source electrode of PMOS transistor in the charge pump of the PMOS ontologies
Voltage carries out forward bias to the ontology of pair pmos transistor；Or this bias voltage is disposed above in PMOS crystal
Voltage at the source electrode of pipe carries out reverse bias to the ontology of pair pmos transistor.
5. the adaptive bi-directional charge pump dynamic regulator for this body bias of metal-oxide-semiconductor, feature exist as claimed in claim 2
Dynamically this bias voltage can be disposed above at the source electrode of NMOS transistor in the charge pump of the NMOS ontologies
Voltage carries out forward bias to the ontology of pair nmos transistor；Or this bias voltage is arranged to less than in NMOS crystal
Voltage at the source electrode of pipe carries out reverse bias to the ontology of pair nmos transistor.
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| TWI740203B (en) * | 2019-08-22 | 2021-09-21 | 大陸商敦泰電子(深圳)有限公司 | Gate driving circuit, charge pump having the same, and chip |
| CN115224932A (en) * | 2022-08-24 | 2022-10-21 | 北京智芯微电子科技有限公司 | Charge pump circuit, chip and electronic equipment |
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