CN108418418B

CN108418418B - Self-adaptive bidirectional charge pump dynamic regulator for MOS tube body bias

Info

Publication number: CN108418418B
Application number: CN201810181530.9A
Authority: CN
Inventors: 陈敏
Original assignee: Chipsea Technologies Shenzhen Co Ltd
Current assignee: Chipsea Technologies Shenzhen Co Ltd
Priority date: 2018-03-06
Filing date: 2018-03-06
Publication date: 2020-07-14
Anticipated expiration: 2038-03-06
Also published as: CN108418418A

Abstract

The invention discloses a self-adaptive bidirectional charge pump dynamic regulator for biasing a MOS (metal oxide semiconductor) tube body, which comprises an NMOS (N-channel metal oxide semiconductor) self-adaptive regulating circuit, a PMOS (P-channel metal oxide semiconductor) self-adaptive regulating circuit and system digital logic, wherein the NMOS self-adaptive regulating circuit comprises an oscillator clock, a frequency-current converter, a quantization and digital-analog conversion circuit, an integrator and a charge pump for biasing an NMOS; the PMOS self-adaptive adjusting circuit comprises an oscillator clock, a frequency-current converter, a quantization and digital-to-analog conversion circuit, an integrator and a charge pump of a bias PMOS; and the charge pump of the bias NMOS and the charge pump of the bias PMOS are both connected with system digital logic so as to realize the stability of threshold values of the NMOS and the PMOS.

Description

Self-adaptive bidirectional charge pump dynamic regulator for MOS tube body bias

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to self-adaptive bidirectional charge pump dynamic regulation specifically applied to CMOS transistor body biasing.

Background

As the ultra-large scale integrated circuit fabrication processes move to the deep nanometer micron regime, the shrinking feature sizes of the devices allow more transistor cells to be integrated on an Integrated Circuit (IC) system. However, even if the integrated circuit chips are based on the same process, the threshold of the MOS transistor on the same wafer is high or low due to the process angle deviation caused by the process manufacturing process: a high threshold results in lower leakage current, lower power consumption, but the maximum operating speed of the system is limited; the low threshold value is beneficial to improving the running speed of the system, and the cost is higher leakage current and higher power consumption. By fixedly biasing the MOS transistor body, its threshold can be set. Although this is a useful technique, in some applications it is still significant to further dynamically adjust the threshold of the MOS transistor, reducing its dispersion, so that system adaptation balances speed and power consumption.

For example, patent application 201510672250.4 discloses a system for reducing electromagnetic interference of a switching power supply chip, which includes a voltage regulator, a reset circuit, a bias voltage generation module and an oscillator module, wherein the voltage regulator module is respectively connected to the bias voltage generation module and the oscillator module, the bias voltage generation module is connected to the oscillator, and the reset circuit is connected to the oscillator module. The system for reducing the electromagnetic interference of the switching power supply chip not only can inhibit conducted interference at the source, but also greatly reduces the size of an EMI filtering part and reduces shielding materials for inhibiting radiation EMI.

However, in the above-described solutions, the generation of the bias voltage is only applied to the oscillator, and further development of the control technique for dynamically biasing the body of the MOS transistor is required.

Disclosure of Invention

Based on this, the first object of the present invention is to provide a self-adaptive bidirectional charge pump dynamic regulator for MOS transistor body bias, which implements flexible and controllable MOS transistor threshold through a self-adaptive bidirectional charge pump, first detects a threshold through a ring oscillator frequency variation associated with the MOS transistor threshold, converts a frequency signal into a current signal, compares the current signal with a reference signal to obtain a difference, further performs quantization integration, and finally controls the charge pump to output a body bias voltage to perform dynamic regulation.

Another objective of the present invention is to provide a dynamic regulator for an adaptive bidirectional charge pump for body bias of a MOS transistor, which can effectively eliminate the influence caused by threshold variation of NMOS and PMOS, so that a system circuit works in an optimal speed-power consumption balance state, thereby improving the overall characteristics of a chip.

In order to achieve the purpose, the technical scheme of the invention is as follows:

a self-adaptive bidirectional charge pump dynamic regulator for MOS tube body bias is characterized in that the regulator comprises an NMOS self-adaptive regulating circuit, a PMOS self-adaptive regulating circuit and system digital logic, wherein the NMOS self-adaptive regulating circuit comprises a ring oscillator, a frequency-current converter, a quantization and digital-analog conversion circuit, an integrator and a charge pump for biasing the NMOS; the PMOS self-adaptive adjusting circuit comprises a ring oscillator, a frequency-current converter, a quantization and digital-to-analog conversion circuit, an integrator and a charge pump of a bias PMOS; and the charge pump of the bias NMOS and the charge pump of the bias PMOS are both connected with system digital logic so as to realize the stability of threshold values of the NMOS and the PMOS.

Specifically, the ring oscillator associated with the NMOS threshold outputs an oscillator clock ck (n) associated with the NMOS threshold, and then a frequency-current converter obtains a corresponding current signal I _ freq _ to _ current (n), the reference current signal iref (n) is differentiated from the current signal and quantized and subjected to digital-to-analog conversion to generate vadj (n), and vadj (n) is input to an integrator to perform integral output vintagor (n), thereby controlling the charge pump of the biased NMOS body to output Vneg; when the NMOS threshold becomes smaller (or larger), the frequency of the output ck (n) of the oscillator becomes faster (or slower), the switching current I _ freq _ to _ current (n) output by the frequency-current converter becomes larger (or smaller), the difference between iref (n) and I _ freq _ to _ current (n) becomes smaller (or larger), the voltage signal vadj (n) after the difference is quantized and subjected to digital-to-analog conversion becomes smaller (or larger), and the output vintagtor (n) becomes smaller (or larger), so that the charge pump Vneg biasing the NMOS body becomes smaller (or larger); through Vneg control, the threshold of the NMOS can be correspondingly increased (or decreased) to compensate the previous fluctuation, and then the threshold stability of the NMOS is realized.

Similarly, the ring oscillator associated with the PMOS threshold outputs an oscillator clock ck (p) associated with the PMOS threshold, and then a frequency-current converter obtains a corresponding current signal I _ freq _ to _ current (p), which is differentiated from the reference current signal iref (p) and quantized and converted by a digital-to-analog converter to generate vadj (p), and the vadj (p) is input to the integrator to perform integration output vintgraph (p) so as to control the charge pump of the bias PMOS body to output Vpeg. When the PMOS threshold becomes smaller (or larger), the frequency of the oscillator output ck (p) becomes faster (or slower), the switching current I _ freq _ to _ current (p) output by the frequency-current converter becomes larger (or smaller), the difference between I _ freq _ to _ current (p) and iref (p) becomes larger (or smaller), the voltage signal vadj (p) after the difference is quantized and subjected to digital-to-analog conversion becomes larger (or smaller), and the integrator output vintagrator (p) becomes larger (or smaller) accordingly, so that the charge pump Vpeg for biasing the PMOS body becomes larger (or smaller). Through control of Vpeg, the threshold value of the PMOS can be correspondingly increased (or decreased) to compensate the previous fluctuation, and then the PMOS threshold value is stabilized.

The charge pump of the PMOS body may dynamically set a body bias voltage lower than a voltage at the source of the PMOS transistor to forward bias the body of the PMOS transistor; or the body bias voltage is set higher than the voltage at the source of the PMOS transistor to reverse bias the body of the PMOS transistor.

The charge pump of the NMOS body may also dynamically set the body bias voltage higher than the voltage at the source of the NMOS transistor to forward bias the body of the NMOS transistor; or the body bias voltage is set lower than the voltage at the source of the NMOS transistor to reverse bias the body of the NMOS transistor.

The regulator realizes the flexible and controllable MOS tube threshold value through a self-adaptive bidirectional charge pump, firstly detects the threshold value through the frequency change of a ring oscillator associated with the MOS tube threshold value, converts a frequency signal into a current signal, compares the current signal with a reference signal to obtain a difference value, further performs quantitative integration, and finally controls the charge pump to output a body bias voltage to perform dynamic regulation.

Moreover, the invention can effectively eliminate the influence caused by the threshold value change of NMOS and PMOS, so that the system circuit works in the optimal speed-power consumption balance state, thereby improving the overall characteristics of the chip.

Drawings

FIG. 1 is a block diagram of a system architecture in which the present invention is implemented.

FIG. 2 is a circuit diagram of a biased NMOS body implemented in accordance with the present invention.

FIG. 3 is a circuit diagram of a ring oscillator with associated NMOS thresholds as implemented in the present invention.

Fig. 4 is a circuit diagram of a frequency-to-current converter implemented in the present invention.

FIG. 5 is a circuit diagram of an associated NMOS current quantizer implemented in accordance with the present invention.

Fig. 6 is a circuit diagram of an integrator implemented in the present invention.

Fig. 7 is a circuit diagram of a charge pump for biasing an NMOS body as implemented in the present invention.

FIG. 8 is a circuit diagram of a digital logic NMOS transistor of a system implemented in accordance with the present invention.

FIG. 9 is a waveform diagram illustrating the overall NMOS body bias response process implemented in the present invention.

FIG. 10 is a circuit diagram of another biased PMOS body in which the present invention is implemented.

FIG. 11 is a circuit diagram of a ring oscillator with associated PMOS thresholds implemented in accordance with the present invention.

Fig. 12 is a circuit diagram of an associated PMOS current quantizer implemented in accordance with the present invention.

Fig. 13 is a circuit diagram of a charge pump for biasing a PMOS body as implemented in the present invention.

FIG. 14 is a waveform diagram of the overall PMOS body bias response process implemented by the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Fig. 1 shows an adaptive dynamic regulator for MOS transistor body bias implemented by the present invention, where the regulator includes an NMOS adaptive regulator circuit, a PMOS adaptive regulator circuit, and system digital logic, and the NMOS adaptive regulator circuit includes a ring oscillator, a frequency-to-current converter, a quantization and digital-to-analog conversion circuit, an integrator, and a charge pump for biasing the NMOS; the PMOS self-adaptive adjusting circuit comprises a ring oscillator, a frequency-current converter, a quantization and digital-to-analog conversion circuit, an integrator and a charge pump of a bias PMOS; and the charge pump of the bias NMOS and the charge pump of the bias PMOS are both connected with system digital logic so as to realize the stability of threshold values of the NMOS and the PMOS.

The ring oscillator associated with the NMOS threshold value outputs an oscillator clock CK (n) related to the NMOS threshold value, then a corresponding current signal I _ freq _ to _ current (n) is obtained through a frequency-current converter, a reference current signal Iref (n) is differed with the current signal and is subjected to quantization and digital-to-analog conversion to generate Vadj (n), the Vadj (n) is input into an integrator to perform integral output Vintegrator (n), and further a charge pump of the bias NMOS body is controlled to output Vneg; when the NMOS threshold becomes smaller (or larger), the frequency of the output ck (n) of the oscillator becomes faster (or slower), the switching current I _ freq _ to _ current (n) output by the frequency-current converter becomes larger (or smaller), the difference between iref (n) and I _ freq _ to _ current (n) becomes smaller (or larger), the voltage signal vadj (n) after the difference is quantized and subjected to digital-to-analog conversion becomes smaller (or larger), and the output vintagtor (n) becomes smaller (or larger), so that the charge pump Vneg biasing the NMOS body becomes smaller (or larger); through Vneg control, the threshold of the NMOS can be correspondingly increased (or decreased) to compensate the previous fluctuation, and then the threshold stability of the NMOS is realized.

Taking the NMOS body bias process as an example, the detailed implementation process is as follows:

FIG. 2 shows a specific application of the present invention, and FIG. 3 shows a ring oscillator associated with NMOS threshold in the application of FIG. 2, which can be a multi-stage differential pair ring oscillator with even number of stages.

As shown in fig. 3, the differential stage basic unit is configured to: m1 and M2 are differential PMOS input tubes, the sources of M1 and M2 are connected with one end of a tail current source Iss, and the other end of the tail current source Iss is from a power supply VDD; m3 and M4 are NMOS tubes as loads, and the drains of M3 and M4 are connected with the drains of M1 and M2 and are connected to the gates of M5 and M6; m5 and M6 are PMOS tubes connected in a capacitor mode. The M3, M4 body bias is controlled by an input Vneg.

The ring oscillator frequency fosc is related to the cascading delay, which is related to the thresholds of M3 and M4 as follows:

fosc∝1/T_D∝Un*Cox*(W/L)_3,4*(Vb-Vthn)/Up*Cox*(W/L)_5,6

∝Un*(W/L)_3,4*(Vb-Vthn)/Up*(W/L)_5,6

un and Up are surface mobility, Cox is oxide capacitance, W is NMOS and PMOS transistor width, L is NMOS and PMOS transistor length, Vthn is NMOS transistor threshold, Vb is fixed bias voltage to make M3 and M4 work in linear region.

When the NMOS threshold Vthn becomes smaller, the oscillator fosc frequency becomes faster, whereas the oscillator frequency becomes slower.

The ring oscillator output CK (ring _ osc) associated with the NMOS threshold is connected to the frequency-to-current converter, and the structure thereof can be adopted as shown in FIG. 4.

When CK is high, switches Sc0, Sc2 and Sc4 are turned on, switches Sc1 and Sc3 are turned off, Cc1 discharges to the ground through Sc0, Cc2 is connected to the negative end of operational amplifier A1 through a switch Sc2, the voltage generated by the charges stored in capacitor Cc2 at the previous moment is compared with Vmid to generate control voltage VN2, and current Ic4 flows through a switch Sc4 through Mc1 and Rc 1. When CK is low, the switches Sc0, Sc2 and Sc4 are turned off, the switches Sc1 and Sc3 are turned on, the voltage on VN2 is not changed, current Ic3 is generated through Mc1 and Rc1 and flows through the switch Sc3, the current Ic3 is equal to the current Ic4 at the previous moment (when CK is high), and the current mirror 2 is used for mapping the Ic3 to generate Ic0 to charge Cc1 and Cc 2. At the time CK is low (half ring oscillator cycle 1/(2 × fosc)), Cc1 and Cc2 are charged to Ic0/[2 × fosc (Cc1+ Cc2) ]. When CK is high again, Cc2 switches to the negative terminal of operational amplifier a1, and the voltage Ic0/[2 × fosc (Cc1+ Cc2) ] generated by the charge stored in capacitor Cc2 at the previous time is compared with Vmid, thereby generating a new control voltage VN2 and a new control current Ic 4. Finally, Ic0/[2 × fosc (Cc1+ Cc2) ] is equal to the Vmid voltage, and Ic0 [2 × fosc (Cc1+ Cc2) ]) Vmid by the whole system feedback. Therefore, when CK is high, Ic0 ═ 0, Ic3 ═ 0, Ic4 ═ fosc; when CK is low, Ic0 ^ fosc, Ic3 ^ fosc and Ic4 ^ 0; ic1 oc Ic4, Ic2 oc Ic3, I _ freq _ to _ current Ic1+ Ic2 are generated by the

current mirrors

1, 2, and therefore, I _ freq _ to _ current oc fosc is generated throughout the CK clock cycle.

The outputs I _ freq _ to _ current of the frequency-current converter are compared with Iref, and the difference (Iref-I _ freq _ to _ current) is taken out for quantization and digital-to-analog conversion, as shown in fig. 5.

Iref is a reference current that corresponds to a desired NMOS reference threshold Vthn ref. For a given NMOS, if the threshold is expected to be Vthn _ ref, there are a corresponding CK _ ref (ring _ osc) output in FIG. 3, and there are a reference current output I _ freq _ to _ current _ ref after the frequency-current conversion in FIG. 4, so Iref can be set to be greater than or equal to CK _ ref (ring _ osc) — (Vthn _ ref) when I _ freq _ to _ current _ ref, i.e., Iref ═ I _ freq _ to _ current _ ref. When the NMOS threshold Vthn shifts above or below the desired value Vthn _ ref, I _ freq _ to _ current changes accordingly. When I _ freq _ to _ current is Iref, the output of the N-bit quantizer is the intermediate code 1000.. 000, and the DAC output falls on the middle axis Vmid; when the I _ freq _ to _ current is larger than the Iref to a certain degree, the output of the N-bit quantizer is 1111.. 111 at the maximum, and the output of the DAC is Vmid + Vref at the maximum; when the I _ freq _ to _ current is smaller than Iref to a certain degree, the output of the N-bit quantizer is the minimum code 0000.. 000, and the output of the DAC is the minimum Vmid-Vref; the fluctuation range of Vadj is therefore [ Vmid-Vref, Vmid + Vref ].

The DAC output Vadj in fig. 5 is input to an integrator for integration, and the basic structure of the integrator is shown in fig. 6:

during initial reset, Si0 is conducted, the node N8 is short-circuited with the output Vintegrator, the operational amplifier A2 is connected into a buffer form, and the output Vintegrator is Vmid. Si0 is cut off after reset

Is high,

When the voltage is low, the Si1 and the Si2 switch are turned on, the Si3 and the Si4 switch are turned off, Vadj charges the voltage at the two ends of Ci1 to Vadj-Vmid through Si1 and Si 2; when in use

Is high,

When the voltage is low, the Si3 and Si4 switches are turned on, the Si1 and Si2 switches are turned off, and the two outputs of the operational amplifier A2The input end virtual short is equal, the voltage of the two ends of Ci1 is Vmid-VN8, and VN8 is Vmid; thus, the charge on Ci1 changes to (Vmid-Vadj) × Ci1, and the corresponding change in the output vintagator voltage is: - (Vmid-Vadj) × Ci1/Ci 2. The difference (Vadj-Vmid) is continuously integrated and reflected on the output by the integrator.

The output of the integrator, vintagator, is connected to a charge pump (as shown in figure 7) that biases the NMOS body when the charge pump is turned on

Is high,

When the voltage is low, S1, S2 are turned on, S3, S4 are turned off, N9 is connected to a power supply VDD, N10 follows a Vintegrator, and the charge stored across C1 is C1 (VDD-Vintegrator); when in use

Is high,

When the voltage is low, S3, S4 is conducted, S1 and S2 are cut off, the voltage at the point N9 is Vintegrator, C1 (VDD-Vintegrator) stored at two ends of C1 charges and discharges the loads C L and R L through S4, and finally the output Vneg is Vintegrator- (VDD-Vintegrator) ═ 2 Vintegrator-VDD, when the Vintegrator is Vmid, the output Vneg 2 Vintegrator-VDD is 0, and when the Vintegrator is Vmid, the output Vnegtegrator is 2 Vintegrator-VDD>Vmid, then Vneg>0; when the Vintegrator<Vmid, then Vneg<0; by adjusting the input Vintegrator, Vneg will generate a voltage greater or less than 0, thereby controlling the NMOS bulk potential in the digital logic of the system of FIG. 8 to realize threshold adjustment.

The Vneg output is connected to the ring oscillator associated with the NMOS threshold in fig. 3, when the NMOS threshold is shifted, that is, the thresholds M3 and M4 in fig. 3 are shifted, the ring oscillator CK (ring _ osc) and the frequency-current output I _ freq _ to _ current are also shifted accordingly, and the charge pump for controlling the bias NMOS bulk voltage generates the required bias voltage Vneg to control the bodies M3 and M4 in the ring oscillator by processing (quantizing, digital-to-analog converting, integrating) the difference between the reference current Iref and the I _ freq _ to _ current. When the NMOS (M3, M4) threshold is adjusted to the desired value, I _ freq _ to _ current is Iref, Vadj is Vmid, the integrator stops integrating, and the vintagrator is maintained at a voltage such that Vneg 2 vintagrator-VDD can bias the NMOS threshold to the desired value.

While Vneg will be connected to the body of the digital logic NMOS transistor of the system of fig. 8, fig. 8 only lists transistors T1, T2, T3, T4 and T5, T6 for simplicity of representation, and a practical electronic device may have any number of transistor pairs Tn-1, Tn and various combinations. When the NMOS threshold of the ring oscillator is finally controlled by Vneg to reach the required range, Vneg connected to the digital logic of the system of fig. 7 will also adjust the NMOS threshold accordingly, thereby eliminating the sacrifice in speed or power consumption caused by the NMOS threshold deviation, and thus satisfying the requirement for balancing the speed and power consumption of the system.

The whole NMOS body bias response process waveform is shown in fig. 9:

in steady state, I _ freq _ to _ current is Iref, and Vadj is Vmid. At a certain time (for example, at time t 1), the NMOS threshold value is shifted, the instantaneous threshold value is increased, the frequency of the ring oscillator CK (ring _ osc) associated with the NMOS threshold value is changed, the frequency is decreased, the conversion current I _ freq _ to _ current output by the frequency-current converter is decreased, the difference between Iref and I _ freq _ to _ current is increased, the voltage signal Vadj after quantization and digital-to-analog conversion of the difference is increased, Vadj > Vmid, (Vadj-Vmid) is integrated continuously, the integrator output vintagrator is gradually increased, and the charge pump Vneg of the biased NMOS body is also gradually increased. As Vneg increases, the voltage difference between the NMOS source voltage and Vneg of the ring oscillator decreases, and the threshold value decreases accordingly. As the NMOS threshold becomes smaller, the ring oscillator CK (ring _ osc) becomes larger, and I _ freq _ to _ current becomes larger. When the NMOS threshold is dynamically adjusted to the corresponding frequency-current output I _ freq _ to _ current ═ Iref, the system feedback reaches a steady state, Vadj ═ Vmid, the integrator stops integrating, the vintagator maintains a certain voltage, and Vneg maintains a certain voltage value, so that the NMOS threshold is adjusted to an expected value.

At another time (for example, time t 2), the NMOS threshold is shifted, the instantaneous threshold is decreased, the frequency of the ring oscillator CK (ring _ osc) associated with the NMOS threshold is changed, the frequency is increased, the conversion current I _ freq _ to _ current output by the frequency-current converter is increased, the difference between Iref and I _ freq _ to _ current is decreased, the voltage signal Vadj after quantization and digital-to-analog conversion is decreased, Vadj < Vmid, (Vadj-Vmid) is integrated continuously, the integrator output vintagtor is decreased gradually, and the charge pump Vneg for biasing the NMOS body is also decreased gradually. As Vneg decreases, the voltage difference between the NMOS source of the ring oscillator and Vneg increases, and the threshold increases accordingly. As the NMOS threshold becomes larger, the ring oscillator CK (ring _ osc) becomes smaller, and I _ freq _ to _ current becomes smaller. When the NMOS threshold is dynamically adjusted to the corresponding frequency-current output I _ freq _ to _ current ═ Iref, the system feedback reaches steady state, Vadj ═ Vmid, the integrator stops integrating, vintagator is maintained at a certain voltage, Vneg is maintained at a certain voltage value so that the NMOS threshold increases to the desired value.

The PMOS body bias process (as shown in fig. 10) is similar to the NMOS body bias process described above, except that the ring oscillator and charge pump are slightly different: a ring oscillator with associated PMOS thresholds and a charge pump biasing the PMOS body are employed.

FIG. 11 is a diagram of a ring oscillator for the application of FIG. 10, which may employ multiple differential pair ring oscillators, with an even number of stages.

The differential stage basic unit is composed of: m1 and M2 are differential NMOS input tubes, the sources of M1 and M2 are connected with one end of a tail current source Iss, and the other end of the tail current source Iss is from the ground; m3 and M4 are PMOS tubes as loads, and the drains of M3 and M4 are connected with the drains of M1 and M2 and are connected to the gates of M5 and M6; m5 and M6 are NMOS tubes connected in a capacitance mode. The M3, M4 body bias is controlled by the input Vpeg.

The frequency of the ring oscillator is related to the cascade delay, and the relationship between the frequency and the thresholds of M3 and M4 is as follows:

fosc∝1/T_D∝Up*Cox*(W/L)_3,4*(V_DD-Vb-|Vthp|)/Un*Cox*(W/L)_5,6

∝Up*(W/L)_3,4*(V_DD-Vb-|Vthp|)/Un*(W/L)_5,6

when the PMOS threshold Vthp becomes smaller, the oscillator fosc frequency becomes faster, whereas the oscillator frequency becomes slower.

The ring oscillator output CK (ring _ osc) associated with the PMOS threshold is connected to the frequency-to-current converter, which has the same structure as described above (fig. 4). Unlike the NMOS body bias process: fig. 4 shows that the outputs I _ freq _ to _ current of the frequency-current converter are compared with Iref, and the inverse difference (I _ freq _ to _ current-Iref) is taken out for quantization and digital-to-analog conversion, as shown in fig. 12.

The DAC output Vadj is connected to an integrator for integration, and the basic structure of the integrator still adopts the structure shown in fig. 6.

The output of the integrator, Vintegrator, is connected to a charge pump (as shown in FIG. 13) biasing the PMOS body, when φ 1 is high and φ 2 is low, S1, S2 is turned on, S3, S4 is turned off, N9 is connected to ground, N10 follows the Vintegrator, the charge stored across C1 is C1 (-Vintegrator), when φ 2 is high and φ 1 is low, S3, S4 is turned on, S1, S2 is turned off, the voltage at point N9 is Vintegrator, the charge stored across C1 is C1 (0-Vintegrator), the loads C L and R L are charged and discharged through S4, the final output Vpeg is Vintegrator- (-Vintegrator) (-2 Vintegrator), when Vpeg is Vnegator Vmid, when Vpegger is larger than Vp, the Vp is regulated by Vpg 2 Vneglig, when Vvmid is regulated by Vpg, and the Vpg is regulated by Vpg 2 Vvdd.

The whole PMOS body bias response process waveform is shown in FIG. 14:

in steady state, I _ freq _ to _ current is Iref, and Vadj is Vmid. At a certain time (for example, at time t 1), the PMOS threshold is shifted, the instantaneous threshold is increased, the frequency of the ring oscillator CK (ring _ osc) associated with the PMOS threshold is changed accordingly, the frequency is decreased, the conversion current I _ freq _ to _ current output by the frequency-current converter is decreased, the difference between I _ freq _ to _ current and Iref is decreased, the voltage signal Vadj after quantization and digital-to-analog conversion of the difference is decreased, Vadj < Vmid, (Vadj-Vmid) is integrated continuously, the integrator output vintagtor is decreased gradually, and the charge pump Vpeg for biasing the PMOS body is also decreased gradually. As Vpeg decreases, the voltage difference between the ring oscillator Vpeg and the PMOS source becomes smaller, and the threshold value becomes smaller accordingly. As the PMOS threshold becomes smaller, the ring oscillator CK (ring _ osc) becomes larger, and I _ freq _ to _ current becomes larger. When the PMOS threshold is dynamically adjusted to the corresponding frequency-current output I _ freq _ to _ current ═ Iref, the system feedback reaches a steady state, Vadj ═ Vmid, the integrator stops integrating, the vintagator is maintained at a certain voltage, and Vpeg is maintained at a certain voltage value, so that the PMOS threshold is adjusted to an expected value.

At another time (for example, time t 2), the PMOS threshold is shifted, the instantaneous threshold is decreased, the frequency of the ring oscillator CK (ring _ osc) associated with the PMOS threshold is changed, the frequency is increased, the conversion current I _ freq _ to _ current output by the frequency-current converter is increased, the difference between I _ freq _ to _ current and Iref is increased, the voltage signal Vadj after the difference is quantized and subjected to digital-to-analog conversion is increased, Vadj > Vmid, (Vadj-Vmid) is integrated continuously, the integrator output vintagrator is increased gradually, and the charge pump Vpeg for biasing the PMOS bulk is also increased gradually. As Vpeg increases, the difference between the Vpeg voltage and the PMOS source voltage of the ring oscillator increases, and the threshold value increases accordingly. As the PMOS threshold becomes larger, the ring oscillator CK (ring _ osc) becomes smaller, and I _ freq _ to _ current becomes smaller. When the PMOS threshold is dynamically adjusted to the corresponding frequency-current output I _ freq _ to _ current ═ Iref, the system feedback reaches steady state, Vadj ═ Vmid, the integrator stops integrating, vintagator is maintained at a certain voltage, Vpeg is maintained at a certain voltage value so that the PMOS threshold is increased to the desired value.

The influence caused by threshold value change of NMOS and PMOS is effectively eliminated by the self-adaptive dynamic regulator, so that the system circuit works in the optimal speed-power consumption balance state, and the overall characteristics of the chip are improved.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims

1. A self-adaptive bidirectional charge pump dynamic regulator for MOS tube body bias is characterized in that the regulator comprises an NMOS self-adaptive regulating circuit, a PMOS self-adaptive regulating circuit and system digital logic, wherein the NMOS self-adaptive regulating circuit comprises a ring oscillator, a frequency-current converter, a quantization and digital-analog conversion circuit, an integrator and a charge pump for biasing the NMOS; the PMOS self-adaptive adjusting circuit comprises a ring oscillator, a frequency-current converter, a quantization and digital-to-analog conversion circuit, an integrator and a charge pump of a bias PMOS; and the charge pump of the bias NMOS and the charge pump of the bias PMOS are both connected with system digital logic so as to realize the stability of threshold values of the NMOS and the PMOS.

2. The adaptive bi-directional charge pump dynamic regulator for body bias of MOS transistors of claim 1, wherein the ring oscillator associated with the NMOS threshold outputs an oscillator clock ck (n) associated with the NMOS threshold, and a frequency-to-current converter obtains a corresponding current signal I _ freq _ to _ current (n), the reference current signal iref (n) is differentiated from the current signal and quantized and digital-to-analog converted to generate vadj (n), and vadj (n) is input to the integrator for integrating output vintagor (n), thereby controlling the charge pump output Vneg of the biased NMOS body; when the NMOS threshold becomes smaller or larger, the frequency of the output ck (n) of the oscillator becomes faster or slower, the switching current I _ freq _ to _ current (n) output by the frequency-current converter becomes larger or smaller, the difference between iref (n) and I _ freq _ to _ current (n) becomes smaller or larger, the voltage signal vadj (n) after quantization and digital-to-analog conversion of the difference becomes smaller or larger, and the output vintagrator (n) becomes smaller or larger, so that the charge pump Vneg of the biased NMOS body becomes smaller or larger; through Vneg control, the threshold value of the NMOS can be correspondingly increased or decreased to make up the previous fluctuation, and then the stability of the threshold value of the NMOS is realized.

3. The adaptive bi-directional charge pump dynamic regulator for body bias of MOS transistors of claim 1, wherein the ring oscillator associated with the PMOS threshold outputs an oscillator clock ck (p) associated with the PMOS threshold, and further obtains a corresponding current signal I _ freq _ to _ current (p) through a frequency-to-current converter, the current signal being differentiated from a reference current signal iref (p) and quantized and digitally-analog converted to generate vadj (p), the vadj (p) is input to the integrator for integrating output vintagor (p) to control the charge pump output Vpeg of the biased PMOS body; when the PMOS threshold becomes smaller or larger, the frequency of the oscillator output ck (p) becomes faster or slower, the switching current I _ freq _ to _ current (p) output by the frequency-current converter becomes larger or smaller, the difference between I _ freq _ to _ current (p) and iref (p) becomes larger or smaller, the voltage signal vadj (p) after the difference is quantized and subjected to digital-to-analog conversion becomes larger or smaller, and the integrator output vintagrator (p) becomes larger or smaller, so that the charge pump Vpeg for biasing the PMOS body becomes larger or smaller; through the control of Vpeg, the threshold value of the PMOS can be correspondingly increased or decreased so as to compensate the previous fluctuation and further realize the stabilization of the threshold value of the PMOS.

4. The adaptive bi-directional charge pump dynamic regulator for MOS transistor body-biasing of claim 3, wherein the charge pump of the PMOS body can dynamically set the body-bias voltage lower than the voltage at the source of the PMOS transistor to forward bias the body of the PMOS transistor; or the body bias voltage is set higher than the voltage at the source of the PMOS transistor to reverse bias the body of the PMOS transistor.

5. The adaptive bi-directional charge pump dynamic regulator for MOS transistor body biasing of claim 2, wherein the charge pump for NMOS body can dynamically set the body bias voltage higher than the voltage at the source of the NMOS transistor to forward bias the body of the NMOS transistor; or the body bias voltage is set lower than the voltage at the source of the NMOS transistor to reverse bias the body of the NMOS transistor.