CN115224932B - Charge pump circuit, chip and electronic equipment - Google Patents

Charge pump circuit, chip and electronic equipment Download PDF

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Publication number
CN115224932B
CN115224932B CN202211021916.6A CN202211021916A CN115224932B CN 115224932 B CN115224932 B CN 115224932B CN 202211021916 A CN202211021916 A CN 202211021916A CN 115224932 B CN115224932 B CN 115224932B
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charge pump
field effect
effect transistor
type field
stage
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CN115224932A (en
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潘杰
原义栋
沈红伟
温立国
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Beijing Smartchip Microelectronics Technology Co Ltd
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Beijing Smartchip Microelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The present disclosure relates to the field of circuit technology, and in particular to a charge pump circuit, a chip and an electronic device, the charge pump circuit includes: at least two stages of charge pump units and auxiliary stage units; in the at least two stages of charge pump units, the body terminal of a first N-type field effect transistor in the ith stage of charge pump unit is connected with the drain terminal of a first N-type field effect transistor in the (i + 1) th stage of charge pump unit and the drain terminal of a first P-type field effect transistor in the (i + 1) th stage of charge pump unit, and the body terminal of a second N-type field effect transistor in the ith stage of charge pump unit is connected with the drain terminal of a second N-type field effect transistor in the (i + 1) th stage of charge pump unit and the drain terminal of a second P-type field effect transistor in the (i + 1) th stage of charge pump unit. By adopting the scheme, the threshold voltage of the switching tube in a conduction state can be reduced through the feedforward body bias voltage of the switching tube, so that the conduction resistance of the switching tube is reduced, and the charge pump can work under ultralow voltage.

Description

Charge pump circuit, chip and electronic equipment
Technical Field
The disclosure relates to the technical field of circuits, in particular to a charge pump circuit, a chip and electronic equipment.
Background
The charge pump is a dc-dc converter, which uses at least one capacitor as an energy storage element to generate an output voltage larger than an input voltage or generate a negative output voltage, and the charge pump based on the cascade connection of voltage doubler units is widely used in micro energy collection chips.
Specifically, in the conventional three-stage charge pump structure, the bulk terminals of all the switching tubes are connected with the self-source terminals. Because there is no body bias effect, the threshold voltage of the switching tube can only be determined by the device process capability. If the switching tube is to be turned on, the input voltage needs to be greater than the threshold voltage of the switching tube. In micro-energy harvesting applications, the energy collector voltage as the pump source is often below 200mV, and a standard Complementary Metal Oxide Semiconductor (CMOS) process has difficulty in providing such low threshold voltage transistor devices, thereby causing charge pump operation difficulties at ultra-low voltages.
Disclosure of Invention
In order to solve the problems in the related art, embodiments of the present disclosure provide a charge pump circuit, a chip, and an electronic device.
In a first aspect, an embodiment of the present disclosure provides a charge pump circuit, including: at least two stages of charge pump units and auxiliary stage units;
in the at least two stages of charge pump units, the body end of a first N-type field effect transistor in the ith stage of charge pump unit is connected with the drain end of a first N-type field effect transistor in the (i + 1) th stage of charge pump unit and the drain end of a first P-type field effect transistor in the (i + 1) th stage of charge pump unit, the body end of a second N-type field effect transistor in the ith stage of charge pump unit is connected with the drain end of a second N-type field effect transistor in the (i + 1) th stage of charge pump unit and the drain end of a second P-type field effect transistor in the (i + 1) th stage of charge pump unit, and i is more than or equal to 1;
the auxiliary stage unit is connected with the output end of the last stage charge pump unit of the at least two stages of charge pump units and is used for providing bias voltage for the last stage charge pump unit;
the body end of a first P-type field effect transistor in a first-stage charge pump unit and the body end of a second P-type field effect transistor in the first-stage charge pump unit are used for receiving a driving clock signal, the body end of the first P-type field effect transistor in a target-stage charge pump unit except the first-stage charge pump unit in at least two stages of charge pump units is connected with the drain end of a first N-type field effect transistor in a last-stage charge pump unit of the target-stage charge pump unit and the drain end of the first P-type field effect transistor in the last-stage charge pump unit, and the body end of the second P-type field effect transistor in the target-stage charge pump unit is connected with the drain end of a second N-type field effect transistor in the last-stage charge pump unit and the drain end of the second P-type field effect transistor in the last-stage charge pump unit;
the source end of each N-type field effect transistor in the first-stage charge pump unit is connected with the input end of the charge pump circuit, the output end of the ith-stage charge pump unit is connected with the input end of the (i + 1) th-stage charge pump unit, and the output end of the charge pump circuit is connected with the output end of the last-stage charge pump unit.
With reference to the first aspect, the present disclosure provides in a first implementation manner of the first aspect, each stage of the charge pump unit includes a first N-type field effect transistor, a first P-type field effect transistor, a second N-type field effect transistor, and a second P-type field effect transistor;
a gate end of a first N-type field effect transistor in the ith stage charge pump unit is connected with a gate end of a first P-type field effect transistor in the ith stage charge pump unit, and is connected with a drain end of a second N-type field effect transistor in the ith stage charge pump unit and a drain end of a second P-type field effect transistor in the ith stage charge pump unit;
the source end of a first N-type field effect transistor in the ith-stage charge pump unit is connected with the source end of a second N-type field effect transistor in the ith-stage charge pump unit, and the source end of a first P-type field effect transistor in the ith-stage charge pump unit is connected with the source end of a second P-type field effect transistor in the ith-stage charge pump unit.
With reference to the first aspect and the first implementation manner, in a second implementation manner of the first aspect, the ith stage charge pump unit further includes a first capacitor and a second capacitor;
one end of the first capacitor is used for receiving a first driving clock signal, the other end of the first capacitor is connected with a drain end of a first N-type field effect transistor in the i-th stage charge pump unit and a drain end of a first P-type field effect transistor in the i-th stage charge pump unit, one end of the second capacitor is used for receiving a second driving clock signal, the other end of the second capacitor is connected with a drain end of a second N-type field effect transistor in the i-th stage charge pump unit and a drain end of a second P-type field effect transistor in the i-th stage charge pump unit, and the first driving clock signal and the second driving clock signal are complementary driving clock signals.
With reference to the first aspect and the first implementation manner, in a third implementation manner of the first aspect, a source end of a first P-type field effect transistor in the i-th stage charge pump unit is connected to a source end of a second P-type field effect transistor in the i-th stage charge pump unit, and is connected to a source end of a first N-type field effect transistor in the i + 1-th stage charge pump unit and a source end of a second N-type field effect transistor in the i + 1-th stage charge pump unit.
With reference to the first aspect, in a fourth implementation manner of the first aspect, the auxiliary stage unit includes a first N-type field effect transistor, a first P-type field effect transistor, a second N-type field effect transistor, and a second P-type field effect transistor, and a source terminal and a body terminal of each field effect transistor in the auxiliary stage unit are connected;
a gate terminal of a first N-type field effect transistor in the auxiliary stage unit is connected with a gate terminal of a first P-type field effect transistor in the auxiliary stage unit, and is connected with a drain terminal of a second N-type field effect transistor in the auxiliary stage unit and a drain terminal of a second P-type field effect transistor in the auxiliary stage unit, and a drain terminal of the first N-type field effect transistor in the auxiliary stage unit is connected with a drain terminal of the first P-type field effect transistor in the auxiliary stage unit, and is connected with a gate terminal of the second N-type field effect transistor in the auxiliary stage unit and a gate terminal of the second P-type field effect transistor in the auxiliary stage unit;
the source end of the first N-type field effect transistor in the auxiliary level unit is connected with the source end of the second N-type field effect transistor in the auxiliary level unit, and the source end of the first P-type field effect transistor in the auxiliary level unit is connected with the source end of the second P-type field effect transistor in the auxiliary level unit.
With reference to the first aspect and the fourth implementation manner, in a fifth implementation manner of the first aspect, the auxiliary stage unit further includes a third capacitor and a fourth capacitor, where one end of the third capacitor is configured to receive a third driving clock signal, and the other end of the third capacitor is connected to a drain of a first N-type field effect transistor in the auxiliary stage unit and a drain of a first P-type field effect transistor in the auxiliary stage unit, one end of the fourth capacitor is connected to a fourth driving clock signal, and the other end of the fourth capacitor is connected to a drain of a second N-type field effect transistor in the auxiliary stage unit and a drain of a second P-type field effect transistor in the auxiliary stage unit;
wherein the third driving clock signal and the fourth driving clock signal are complementary driving clock signals.
With reference to the first aspect and the fourth implementation manner, in a sixth implementation manner of the first aspect, the source terminal of the first N-type field effect transistor in the secondary unit is connected to the source terminal of the second N-type field effect transistor in the secondary unit, and is connected to the source terminal of the first P-type field effect transistor in the last-stage charge pump unit and the source terminal of the second P-type field effect transistor in the last-stage charge pump unit.
With reference to the first aspect, in a seventh implementation manner of the first aspect, a body terminal of a first P-type field effect transistor in the first stage charge pump unit is configured to receive a fifth driving clock signal, a body terminal of a second P-type field effect transistor in the first stage charge pump unit is configured to receive a sixth driving clock signal, and the fifth driving clock signal and the driving clock signal are complementary driving clock signals.
In a second aspect, a chip is provided in an embodiment of the present disclosure, which includes the charge pump circuit as described in the first aspect and any one of the first to seventh implementations.
In a third aspect, an embodiment of the present disclosure provides an electronic device, including the chip of the second aspect.
According to the technical scheme provided by the embodiment of the disclosure, the threshold voltage of the switching tube in a conducting state can be reduced through the feedforward body bias voltage of the switching tube, so that the conducting resistance of the switching tube is reduced, the switching tube can work under ultralow voltage, and the working capacity of the charge pump under ultralow voltage is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments when taken in conjunction with the accompanying drawings. In the drawings:
fig. 1 shows a block diagram of a charge pump circuit according to an embodiment of the disclosure.
Fig. 2 shows a schematic diagram of the on-resistance of a field effect transistor according to an embodiment of the present disclosure.
Fig. 3 shows a schematic diagram of the off-resistance of a field effect transistor according to an embodiment of the disclosure.
Fig. 4 shows a block diagram of a chip according to an embodiment of the disclosure.
Fig. 5 shows a block diagram of an electronic device according to an embodiment of the present disclosure.
Detailed Description
Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. Furthermore, parts that are not relevant to the description of the exemplary embodiments have been omitted from the drawings for the sake of clarity.
In the present disclosure, it is to be understood that terms such as "including" or "having," etc., are intended to indicate the presence of the disclosed features, numerals, steps, actions, components, parts, or combinations thereof in the specification, and are not intended to preclude the possibility that one or more other features, numerals, steps, actions, components, parts, or combinations thereof are present or added.
It should also be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
In the present disclosure, if an operation of acquiring user information or user data or an operation of presenting user information or user data to others is involved, the operations are all operations authorized, confirmed by a user, or actively selected by the user.
As mentioned above, the charge pump is a dc-dc converter that generates an output voltage larger than an input voltage or generates a negative output voltage using at least one capacitor as an energy storage element, and the charge pump based on the cascade connection of voltage doubler units is widely used in micro energy collection chips.
Specifically, in the conventional three-stage charge pump structure, the bulk terminals of all the switching tubes are connected with the self-source terminals. Because there is no body bias effect, the threshold voltage of the switching tube can only be determined by the device process capability. If the switching tube is to be turned on, the input voltage needs to be greater than the threshold voltage of the switching tube. In micro-energy harvesting applications, the energy collector voltage as the pump source is often below 200mV, and a standard Complementary Metal Oxide Semiconductor (CMOS) process has difficulty in providing such low threshold voltage transistor devices, thereby causing charge pump operation difficulties at ultra-low voltages.
In view of the above technical drawbacks, an embodiment of the present disclosure provides a charge pump circuit, including: at least two stages of charge pump units and auxiliary stage units;
in the at least two stages of charge pump units, the body end of a first N-type field effect transistor in the ith stage of charge pump unit is connected with the drain end of a first N-type field effect transistor in the (i + 1) th stage of charge pump unit and the drain end of a first P-type field effect transistor in the (i + 1) th stage of charge pump unit, the body end of a second N-type field effect transistor in the ith stage of charge pump unit is connected with the drain end of a second N-type field effect transistor in the (i + 1) th stage of charge pump unit and the drain end of a second P-type field effect transistor in the (i + 1) th stage of charge pump unit, and i is more than or equal to 1;
the auxiliary stage unit is connected with the output end of the last stage charge pump unit of the at least two stages of charge pump units and is used for providing bias voltage for the last stage charge pump unit;
the body end of a first P-type field effect transistor in a first-stage charge pump unit and the body end of a second P-type field effect transistor in the first-stage charge pump unit are used for receiving a driving clock signal, the body end of the first P-type field effect transistor in a target-stage charge pump unit except the first-stage charge pump unit in at least two stages of charge pump units is connected with the drain end of a first N-type field effect transistor in a last-stage charge pump unit of the target-stage charge pump unit and the drain end of the first P-type field effect transistor in the last-stage charge pump unit, and the body end of the second P-type field effect transistor in the target-stage charge pump unit is connected with the drain end of a second N-type field effect transistor in the last-stage charge pump unit and the drain end of the second P-type field effect transistor in the last-stage charge pump unit;
the source end of each N-type field effect transistor in the first-stage charge pump unit is connected with the input end of the charge pump circuit, the output end of the ith-stage charge pump unit is connected with the input end of the (i + 1) th-stage charge pump unit, and the output end of the charge pump circuit is connected with the output end of the last-stage charge pump unit.
According to the technical scheme provided by the embodiment of the disclosure, the threshold voltage of the switching tube in a conducting state can be reduced through the feedforward body bias voltage of the switching tube, so that the conducting resistance of the switching tube is reduced, the switching tube can work under ultralow voltage, and the working capacity of the charge pump under ultralow voltage is improved.
According to the charge pump circuit of the embodiment of the present disclosure, the charge pump circuit includes at least two stages of charge pump units and an auxiliary stage unit;
in the at least two stages of charge pump units, the body end of a first N-type field effect transistor in the ith stage of charge pump unit is connected with the drain end of a first N-type field effect transistor in the (i + 1) th stage of charge pump unit and the drain end of a first P-type field effect transistor in the (i + 1) th stage of charge pump unit, the body end of a second N-type field effect transistor in the ith stage of charge pump unit is connected with the drain end of a second N-type field effect transistor in the (i + 1) th stage of charge pump unit and the drain end of a second P-type field effect transistor in the (i + 1) th stage of charge pump unit, and i is more than or equal to 1;
the auxiliary stage unit is connected with the output end of the last stage charge pump unit of the at least two stages of charge pump units and is used for providing bias voltage for the last stage charge pump unit;
the body end of a first P-type field effect transistor in a first-stage charge pump unit and the body end of a second P-type field effect transistor in the first-stage charge pump unit are used for receiving a driving clock signal, the body end of the first P-type field effect transistor in a target-stage charge pump unit except the first-stage charge pump unit in at least two stages of charge pump units is connected with the drain end of a first N-type field effect transistor in a last-stage charge pump unit of the target-stage charge pump unit and the drain end of the first P-type field effect transistor in the last-stage charge pump unit, and the body end of the second P-type field effect transistor in the target-stage charge pump unit is connected with the drain end of a second N-type field effect transistor in the last-stage charge pump unit and the drain end of the second P-type field effect transistor in the last-stage charge pump unit;
the source end of each N-type field effect transistor in the first-stage charge pump unit is connected with the input end of the charge pump circuit, the output end of the ith-stage charge pump unit is connected with the input end of the (i + 1) th-stage charge pump unit, and the output end of the charge pump circuit is connected with the output end of the last-stage charge pump unit.
In an embodiment of the present disclosure, the target-stage charge pump is any one of the at least two stages of charge pump units except for the first-stage charge pump unit.
Illustratively, a charge pump circuit including a three-stage charge pump cell is taken as an example. As shown in fig. 1, a structure diagram of a three-stage charge pump circuit 200 includes a first stage charge pump unit 201, a second stage charge pump unit 202, a third stage charge pump unit 203, and an auxiliary unit 204.
Specifically, as shown in fig. 1, the body terminal of the first N-type field effect transistor MN1 in the first stage charge pump unit 201 is connected to the drain terminal of the first N-type field effect transistor MN4 in the second stage charge pump unit 202 and the drain terminal of the first P-type field effect transistor MP4 in the second stage charge pump unit 202 (i.e., connected to the node B2), the body terminal of the second N-type field effect transistor MN2 in the first stage charge pump unit 201 is connected to the drain terminal of the second N-type field effect transistor MN3 in the second stage charge pump unit 202 and the drain terminal of the second P-type field effect transistor MP3 in the second stage charge pump unit 202 (i.e., connected to the node A2), the body terminal of the first P-type field effect transistor MP1 in the first stage charge pump unit 201 is configured to receive the driving clock signal CLK _ B, and the body terminal of the second P-type field effect transistor MP2 in the first stage charge pump unit 201 is configured to receive the driving clock signal CLK; the body terminal of the first N-type field effect transistor MN4 in the second stage charge pump unit 202 is connected to the drain terminal of the first N-type field effect transistor MN5 in the third stage charge pump unit 203 and the drain terminal of the first P-type field effect transistor MP5 in the second stage charge pump unit 203 (i.e., connected to node A3), the body terminal of the second N-type field effect transistor MN3 in the second stage charge pump unit 202 is connected to the drain terminal of the second N-type field effect transistor MN6 in the third stage charge pump unit 203 and the drain terminal of the second P-type field effect transistor MP6 in the third stage charge pump unit 203 (i.e., connected to node B3), the body terminal of the first P-type field effect transistor MN4 in the second stage charge pump unit 202 is connected to the drain terminal of the first N-type field effect transistor MN1 in the first stage charge pump unit 201 and the drain terminal of the first P-type field effect transistor MP1 in the first stage charge pump unit 201 (i.e., connected to node A1), the body terminal of the second P-type field effect transistor MP3 in the second stage charge pump unit 202 is connected to the drain terminal of the second N-type field effect transistor MN2 in the first stage charge pump unit 201 and the drain terminal of the first stage charge pump unit 201 (i.e., connected to node B2); the body terminal of the first N-type field effect transistor MN5 in the third stage charge pump unit 203 is connected to the drain terminal of the first N-type field effect transistor MN8 in the auxiliary stage unit 204 and the drain terminal of the first P-type field effect transistor MP8 in the auxiliary stage unit 204 (i.e., connected to node B4), the body terminal of the second N-type field effect transistor MN6 in the third stage charge pump unit 203 is connected to the drain terminal of the second N-type field effect transistor MN7 in the auxiliary stage unit 204 and the drain terminal of the second P-type field effect transistor MP7 in the auxiliary stage unit 204 (i.e., connected to node A4), the body terminal of the first P-type field effect transistor MP5 in the third stage charge pump unit 203 is connected to the drain terminal of the first N-type field effect transistor MN4 in the second stage charge pump unit 202 and the drain terminal of the first P-type field effect transistor MP4 in the second stage charge pump unit 202 (i.e., connected to node B2), the body terminal of the second P-type field effect transistor MP6 in the third stage charge pump unit 203 is connected to the drain terminal of the second N-type field effect transistor MN3 in the second N-type field effect transistor MN 202 and the drain terminal of the second P-type field effect transistor MP3 in the second stage charge pump unit 202 (i.e., connected to node A2). The input voltage of the first-stage charge pump unit 201 is VIN, the output voltage of the first-stage charge pump unit 201 is Vo1, the input voltage of the second-stage charge pump unit 202 is Vo1, the output voltage of the second-stage charge pump unit 202 is Vo2, the input voltage of the third-stage charge pump unit 203 is Vo2, the output voltage of the third-stage charge pump unit 203 is Vout, the output end of the third-stage charge pump unit 203 is connected with the output end of the charge pump circuit, and the input end of the auxiliary-stage unit 204 and the output end of the third-stage charge pump unit 203, that is, the input voltage of the auxiliary-stage unit 204 is Vout.
In fig. 1, the first stage charge pump unit is taken as an example: when CLK = VIN and CLK _ B =0, MN2 and MP1 are turned on, MN1 and MP2 are turned off, and the driving source VIN charges the capacitor C2 through the turned-on switching tube MN2 until the node B1 is equal to VIN (note that the smaller the turned-on resistance of the turned-on switching tube is, the higher the charging efficiency is), that is, the voltage difference between the upper and lower electrode plates of the capacitor C2 is VIN; when CLK =0 and CLK _ B = VIN, MN2 and MP1 are turned off, MN1 and MP2 are turned on, the excitation source VIN and the capacitor C2 are disconnected by the switch MN2 (note that the larger the off resistance of the disconnected switch is, the smaller the leakage loss is), after the clock switching, since the voltage difference between the upper and lower plates of the capacitor C2 cannot be suddenly changed, at this time, the lower plate CLK _ B is VIN and the upper plate B1 is 2VIN, that is, the output node Vo1 of the first-stage charge pump unit is pulled to 2VIN by the turned-on switch MP2. Similarly, under the periodic driving of the complementary clocks CLK and CLK _ B, when the cascaded charge pump is stable, the output voltage Vo1=2VIN of the first-stage charge pump unit, the output voltage Vo2=3VIN of the second-stage charge pump unit, and the output voltage Vout =4VIN of the third-stage charge pump unit.
In the disclosed embodiment, the body and source terminals of the field effect transistor in fig. 1 are not connected, i.e., the threshold voltage of the field effect transistor is adjusted using the body effect. Taking an N-type field effect transistor as an example, the threshold voltage can be significantly reduced by adopting a feed Forward Body Bias (FBB) technology, specifically according to the following formula:
Figure BDA0003814376770000071
wherein, V T,N Is the threshold voltage of the belt body effect, V T,N0 Is the threshold voltage of no body effect, gamma is the coefficient of body effect, V SB Is the difference between the Source (Source) and Bulk (Bulk) voltages, phi F Is the fermi potential.
From the above formula, it can be seen that the higher the body bias of the N-type field effect transistor, the lower the threshold voltage. Similarly, the higher the body bias, the lower the threshold voltage of the PFET.
In the charge pump circuit shown in fig. 1, in conjunction with fig. 1, the feed forward body bias voltages VFBB of all the field effect transistors at different clock phases are shown in the following table:
Figure BDA0003814376770000072
taking a typical 28nm fully depleted silicon technology CMOS process as an example, fig. 2 shows the analysis of the on-resistances of the N-type field effect transistor and the P-type field effect transistor at VGS =0.2V under different feed-forward body bias voltages, and fig. 3 shows the analysis of the off-resistances of the N-type field effect transistor and the P-type field effect transistor at VGS =0V under different feed-forward body bias voltages. In combination with the above table, when the starting voltage (i.e., VIN) is 200mV, the feedforward body bias voltage of the switching tube (i.e., the field effect transistor) in the on state is 400mV, the on resistance of the switching tube is reduced by-55% to-54% as compared with the switching tube without feedforward body bias, and the on resistance is reduced as the feedforward body bias voltage is increased; the feed-forward body bias voltage of the switching tube in the off state is 200mV, and the off resistance of the switching tube is reduced by-34% to-33% compared with the switching tube without the feed-forward body bias. Therefore, the reduction degree of the turn-off resistance is far lower than that of the turn-on resistance, and the starting capability of the charge pump under low voltage is greatly improved.
It should be noted that, compared with the related art, the voltage of the bulk terminal of the field effect transistor in each stage of the charge pump unit in the embodiment of the present disclosure is periodically fluctuated, so by dynamically switching the feed-forward body bias voltage, the on-resistance (45% to 46% of the on-resistance when there is no feed-forward body bias) of the field effect transistor (i.e., the switching tube) can be reduced, thereby improving the turn-on capability of the charge pump. As such, the charge pump provided by the embodiments of the present disclosure can operate in a lower voltage environment.
In the embodiment, the threshold voltage of the switching tube in the on state can be reduced through the feedforward body bias voltage of the switching tube, so that the on resistance of the switching tube is reduced, the switching tube can work under ultralow voltage, and the working capacity of the charge pump under ultralow voltage is improved.
In an embodiment of the present disclosure, a body terminal of a first P-type field effect transistor in the first stage charge pump unit is configured to receive a fifth driving clock signal, a body terminal of a second P-type field effect transistor in the first stage charge pump unit is configured to receive a sixth driving clock signal, and the fifth driving clock signal and the sixth driving clock signal are complementary driving clock signals.
In an embodiment of the present disclosure, it is understood that the fifth driving clock signal and the sixth driving clock signal are complementary driving clock signals, that is, the fifth driving clock signal and the sixth driving clock signal are inverted clock signals, that is, when the fifth driving clock signal is at a high level, the sixth driving clock signal is at a low level. It should be noted that, other complementary driving clock signals involved in the embodiments of the present disclosure can refer to this description, and the embodiments of the present disclosure are not described herein again.
In an embodiment of the present disclosure, the auxiliary stage unit is configured to provide a bias voltage for the last stage charge pump unit, which may be understood as providing a voltage for a body terminal of a first N-type field effect transistor in the last stage charge pump unit and a body terminal of a second N-type field effect transistor in the last stage charge pump unit.
Illustratively, as shown in fig. 1, a connection point B4 between the drain terminal of the first N-type field effect transistor MN8 in the auxiliary stage unit 204 and the drain terminal of the first P-type field effect transistor MP8 in the auxiliary stage unit 204 provides a voltage for the body terminal of the first N-type field effect transistor MN5 in the third stage charge pump unit 203, and a connection point A4 between the drain terminal of the second N-type field effect transistor MN7 in the auxiliary stage unit 204 and the drain terminal of the second P-type field effect transistor MP7 in the auxiliary stage unit 204 provides a voltage for the body terminal of the second N-type field effect transistor MN6 in the third stage charge pump unit 203.
In one embodiment of the present disclosure, each stage of the charge pump unit includes a first N-type field effect transistor, a first P-type field effect transistor, a second N-type field effect transistor, and a second P-type field effect transistor;
a gate end of a first N-type field effect transistor in the ith stage charge pump unit is connected with a gate end of a first P-type field effect transistor in the ith stage charge pump unit, and is connected with a drain end of a second N-type field effect transistor in the ith stage charge pump unit and a drain end of a second P-type field effect transistor in the ith stage charge pump unit, a drain end of the first N-type field effect transistor in the ith stage charge pump unit is connected with a drain end of the first P-type field effect transistor in the ith stage charge pump unit, and is connected with a gate end of the second N-type field effect transistor in the ith stage charge pump unit and a gate end of the second P-type field effect transistor in the ith stage charge pump unit;
the source end of a first N-type field effect transistor in the ith-stage charge pump unit is connected with the source end of a second N-type field effect transistor in the ith-stage charge pump unit, and the source end of a first P-type field effect transistor in the ith-stage charge pump unit is connected with the source end of a second P-type field effect transistor in the ith-stage charge pump unit.
Illustratively, again as in the first stage charge pump cell 201 of fig. 1. The first stage charge pump unit 201 includes a first N-type field effect transistor MN1, a first P-type field effect transistor MP1, a second N-type field effect transistor MN2, and a second P-type field effect transistor MP2.
Specifically, a gate terminal of a first N-type field effect transistor MN1 in the first-stage charge pump unit 201 is connected to a gate terminal of a first P-type field effect transistor MP1 in the first-stage charge pump unit 201, and is connected to a drain terminal of a second N-type field effect transistor MN2 in the first-stage charge pump unit 201 and a drain terminal of a second P-type field effect transistor MP2 in the first-stage charge pump unit 201, and a drain terminal MN1 of the first N-type field effect transistor in the first-stage charge pump unit 201 is connected to a drain terminal of the first P-type field effect transistor MP1 in the first-stage charge pump unit 201, and is connected to a gate terminal of the second N-type field effect transistor MN2 in the first-stage charge pump unit 201 and a gate terminal of the second P-type field effect transistor MP2 in the first-stage charge pump unit 201. The source end of a first N-type field effect transistor MN1 in the first-stage charge pump unit 201 is connected to the source end of a second N-type field effect transistor MN2 in the first-stage charge pump unit 201, and the source end of a first P-type field effect transistor MP1 in the first-stage charge pump unit 201 is connected to the source end of a second P-type field effect transistor MP2 in the first-stage charge pump unit 201.
It should be noted that, the above description is only exemplary of the circuit structure of the first stage charge pump unit, and the circuit structures of the other stage charge pump units may refer to the above detailed description.
In an embodiment of the present disclosure, the i-th stage charge pump unit further includes a first capacitor and a second capacitor;
one end of the first capacitor is used for receiving a first driving clock signal, the other end of the first capacitor is connected with a drain end of a first N-type field effect transistor in the i-th stage charge pump unit and a drain end of a first P-type field effect transistor in the i-th stage charge pump unit, one end of the second capacitor is used for receiving a second driving clock signal, the other end of the second capacitor is connected with a drain end of a second N-type field effect transistor in the i-th stage charge pump unit and a drain end of a second P-type field effect transistor in the i-th stage charge pump unit, and the first driving clock signal and the second driving clock signal are complementary driving clock signals.
Illustratively, as shown in fig. 1, the first stage charge pump unit 201 further includes a first capacitor C1 and a second capacitor C2, the second stage charge pump unit 202 further includes a first capacitor C3 and a second capacitor C4, and the third stage charge pump unit 203 further includes a first capacitor C5 and a second capacitor C6. Wherein, one end of the first capacitor C1 of the first-stage charge pump unit 201, one end of the first capacitor C3 of the second-stage charge pump unit 202, and one end of the first capacitor C5 of the third-stage charge pump unit 203 are used for receiving the same driving clock signal; one end of the first capacitor C2 of the first-stage charge pump unit 201, one end of the first capacitor C4 of the second-stage charge pump unit 202, and one end of the first capacitor C6 of the third-stage charge pump unit 203 are configured to receive the same driving clock signal.
Specifically, the first stage charge pump unit 201 in fig. 1 is taken as an example. One end of the first capacitor C1 is configured to receive a first driving clock signal CLK, and the other end of the first capacitor C1 is connected to the drain of the first N-type field effect transistor MN1 in the first-stage charge pump unit 201 and the drain of the first P-type field effect transistor MP1 in the first-stage charge pump unit 201, one end of the second capacitor C2 is configured to receive a second driving clock signal CLK _ B, and the other end of the second capacitor C2 is connected to the drain of the second N-type field effect transistor MN2 in the first-stage charge pump unit 201 and the drain of the second P-type field effect transistor MP2 in the first-stage charge pump unit, where the first driving clock signal CLK and the second driving clock signal CLK _ B are complementary driving clock signals.
In an embodiment of the present disclosure, the first driving clock signal is the same as the fifth driving clock signal, and the second driving clock signal is the same as the sixth driving clock signal.
In an embodiment of the present disclosure, a source end of a first P-type field effect transistor in the i-th stage charge pump unit is connected to a source end of a second P-type field effect transistor in the i-th stage charge pump unit, and is connected to a source end of a first N-type field effect transistor in the i + 1-th stage charge pump unit and a source end of a second N-type field effect transistor in the i + 1-th stage charge pump unit.
Illustratively, as also shown in fig. 1, a source terminal of the first P-type field effect transistor MP1 in the first stage charge pump unit 201 and a source terminal of the second P-type field effect transistor MP2 in the first stage charge pump unit 201 are connected to a source terminal of the first N-type field effect transistor MN4 in the second stage charge pump unit 202 and a source terminal of the second N-type field effect transistor MN3 in the second stage charge pump unit 202.
In an embodiment of the present disclosure, the auxiliary stage unit includes a first N-type field effect transistor, a first P-type field effect transistor, a second N-type field effect transistor, and a second P-type field effect transistor, and a source terminal and a body terminal of each field effect transistor in the auxiliary stage unit are connected;
a gate terminal of a first N-type field effect transistor in the auxiliary stage unit is connected with a gate terminal of a first P-type field effect transistor in the auxiliary stage unit, and is connected with a drain terminal of a second N-type field effect transistor in the auxiliary stage unit and a drain terminal of a second P-type field effect transistor in the auxiliary stage unit, and a drain terminal of the first N-type field effect transistor in the auxiliary stage unit is connected with a drain terminal of the first P-type field effect transistor in the auxiliary stage unit, and is connected with a gate terminal of the second N-type field effect transistor in the auxiliary stage unit and a gate terminal of the second P-type field effect transistor in the auxiliary stage unit;
the source end of the first N-type field effect transistor in the auxiliary level unit is connected with the source end of the second N-type field effect transistor in the auxiliary level unit, and the source end of the first P-type field effect transistor in the auxiliary level unit is connected with the source end of the second P-type field effect transistor in the auxiliary level unit.
Illustratively, as also shown in fig. 1, the auxiliary stage unit includes a first N-type field effect transistor MN8, a first P-type field effect transistor MP8, a second N-type field effect transistor MN7, and a second P-type field effect transistor MP7, with the source terminal and the body terminal of each field effect transistor in the auxiliary stage unit being connected.
Specifically, a gate terminal of a first N-type field effect transistor MN8 in the auxiliary stage unit 204 is connected to a gate terminal of a first P-type field effect transistor MP8 in the auxiliary stage unit 204, and is connected to a drain terminal of a second N-type field effect transistor MN7 in the auxiliary stage unit 204 and a drain terminal of a second P-type field effect transistor MP7 in the auxiliary stage unit 204, and a drain terminal of the first N-type field effect transistor MN8 in the auxiliary stage unit 204 is connected to a drain terminal of the first P-type field effect transistor MP8 in the auxiliary stage unit 204, and is connected to a gate terminal of the second N-type field effect transistor MN7 in the auxiliary stage unit 204 and a gate terminal of the second P-type field effect transistor MP7 in the auxiliary stage unit 204. A source end of the first N-type field effect transistor MN8 in the auxiliary stage unit 204 is connected to a source end of the second N-type field effect transistor MN7 in the auxiliary stage unit 204, and a source end of the first P-type field effect transistor MP8 in the auxiliary stage unit 204 is connected to a source end of the second P-type field effect transistor MP7 in the auxiliary stage unit 204.
In an embodiment of the present disclosure, the auxiliary stage unit further includes a third capacitor and a fourth capacitor, one end of the third capacitor is configured to receive a third driving clock signal, and the other end of the third capacitor is connected to a drain of a first N-type field effect transistor in the auxiliary stage unit and a drain of a first P-type field effect transistor in the auxiliary stage unit, one end of the fourth capacitor is connected to a fourth driving clock signal, and the other end of the fourth capacitor is connected to a drain of a second N-type field effect transistor in the auxiliary stage unit and a drain of a second P-type field effect transistor in the auxiliary stage unit;
wherein the third driving clock signal and the fourth driving clock signal are complementary driving clock signals.
Illustratively, the auxiliary stage unit 204 as in fig. 1 is still taken as an example. The auxiliary stage unit 204 further includes a third capacitor C7 and a fourth capacitor C8. One end of the third capacitor C7 is configured to receive a third driving clock signal CLK, and the other end of the third capacitor C7 is connected to the drain of the first N-type field effect transistor MN8 in the auxiliary stage unit 204 and the drain of the first P-type field effect transistor MP8 in the auxiliary stage unit 204, one end of the fourth capacitor C8 is connected to a fourth driving clock signal CLK _ B, and the other end of the fourth capacitor C8 is connected to the drain of the second N-type field effect transistor MN7 in the auxiliary stage unit 204 and the drain of the second P-type field effect transistor MP7 in the auxiliary stage unit; wherein the third driving clock signal CLK and the fourth driving clock signal CLK _ B are complementary driving clock signals.
In an embodiment of the present disclosure, a source end of a first N-type field effect transistor in the auxiliary stage unit is connected to a source end of a second N-type field effect transistor in the auxiliary stage unit, and is connected to a source end of a first P-type field effect transistor in the last stage charge pump unit and a source end of a second P-type field effect transistor in the last stage charge pump unit.
Illustratively, it is also exemplified as in fig. 1. A source end of the first N-type field effect transistor MN8 in the auxiliary stage unit 204 is connected to a source end of the second N-type field effect transistor MN7 in the auxiliary stage unit 204, and is connected to a source end of the first P-type field effect transistor MP5 in the last stage charge pump unit 203 and a source end of the second P-type field effect transistor MP6 in the last stage charge pump unit 203.
As shown in fig. 4, the present disclosure also provides a chip 300 including any of the charge pump circuits 200 described above.
As shown in fig. 5, the present disclosure also provides an electronic device 400 including the chip 300 as shown in fig. 4.
The foregoing description is only exemplary of the preferred embodiments of the disclosure and is illustrative of the principles of the technology employed. It will be appreciated by those skilled in the art that the scope of the invention in the present disclosure is not limited to the specific combination of the above-mentioned features, but also encompasses other embodiments in which any combination of the above-mentioned features or their equivalents is possible without departing from the inventive concept. For example, the above features and the technical features disclosed in the present disclosure (but not limited to) having similar functions are replaced with each other to form the technical solution.

Claims (10)

1. A charge pump circuit, comprising: at least two stages of charge pump units and auxiliary stage units;
in the at least two stages of charge pump units, the body end of a first N-type field effect transistor in an ith stage of charge pump unit is connected with the drain end of a first N-type field effect transistor in an (i + 1) th stage of charge pump unit and the drain end of a first P-type field effect transistor in the (i + 1) th stage of charge pump unit, the body end of a second N-type field effect transistor in the ith stage of charge pump unit is connected with the drain end of a second N-type field effect transistor in the (i + 1) th stage of charge pump unit and the drain end of a second P-type field effect transistor in the (i + 1) th stage of charge pump unit, and i is more than or equal to 1;
the auxiliary stage unit is connected with the output end of the last stage charge pump unit of the at least two stages of charge pump units and is used for providing bias voltage for the last stage charge pump unit;
the body end of a first P-type field effect transistor in a first-stage charge pump unit and the body end of a second P-type field effect transistor in the first-stage charge pump unit are used for receiving a driving clock signal, the body end of the first P-type field effect transistor in a target-stage charge pump unit except the first-stage charge pump unit in at least two stages of charge pump units is connected with the drain end of a first N-type field effect transistor in a last-stage charge pump unit of the target-stage charge pump unit and the drain end of the first P-type field effect transistor in the last-stage charge pump unit, and the body end of the second P-type field effect transistor in the target-stage charge pump unit is connected with the drain end of a second N-type field effect transistor in the last-stage charge pump unit and the drain end of the second P-type field effect transistor in the last-stage charge pump unit;
the source end of each N-type field effect transistor in the first-stage charge pump unit is connected with the input end of the charge pump circuit, the output end of the ith-stage charge pump unit is connected with the input end of the (i + 1) th-stage charge pump unit, and the output end of the charge pump circuit is connected with the output end of the last-stage charge pump unit.
2. The circuit of any one of claim 1, wherein each stage of charge pump unit comprises a first N-type field effect transistor, a first P-type field effect transistor, a second N-type field effect transistor, and a second P-type field effect transistor;
a gate end of a first N-type field effect transistor in the ith stage charge pump unit is connected with a gate end of a first P-type field effect transistor in the ith stage charge pump unit, and is connected with a drain end of a second N-type field effect transistor in the ith stage charge pump unit and a drain end of a second P-type field effect transistor in the ith stage charge pump unit;
the source end of a first N-type field effect transistor in the ith-stage charge pump unit is connected with the source end of a second N-type field effect transistor in the ith-stage charge pump unit, and the source end of a first P-type field effect transistor in the ith-stage charge pump unit is connected with the source end of a second P-type field effect transistor in the ith-stage charge pump unit.
3. The circuit of claim 2, wherein the i-th stage charge pump cell further comprises a first capacitor and a second capacitor;
one end of the first capacitor is used for receiving a first driving clock signal, the other end of the first capacitor is connected with a drain end of a first N-type field effect transistor in the i-th stage charge pump unit and a drain end of a first P-type field effect transistor in the i-th stage charge pump unit, one end of the second capacitor is used for receiving a second driving clock signal, the other end of the second capacitor is connected with a drain end of a second N-type field effect transistor in the i-th stage charge pump unit and a drain end of a second P-type field effect transistor in the i-th stage charge pump unit, and the first driving clock signal and the second driving clock signal are complementary driving clock signals.
4. The circuit of claim 2, wherein a source terminal of a first P-type field effect transistor in the i-th stage charge pump unit is connected to a source terminal of a second P-type field effect transistor in the i-th stage charge pump unit, and is connected to a source terminal of a first N-type field effect transistor in the i + 1-th stage charge pump unit and a source terminal of a second N-type field effect transistor in the i + 1-th stage charge pump unit.
5. The circuit of claim 1, wherein the auxiliary stage unit includes a first N-type field effect transistor, a first P-type field effect transistor, a second N-type field effect transistor, and a second P-type field effect transistor, and wherein a source terminal and a body terminal of each field effect transistor in the auxiliary stage unit are connected;
the grid end of a first N-type field effect transistor in the auxiliary stage unit is connected with the grid end of a first P-type field effect transistor in the auxiliary stage unit, and is connected with the drain end of a second N-type field effect transistor in the auxiliary stage unit and the drain end of a second P-type field effect transistor in the auxiliary stage unit;
the source end of the first N-type field effect transistor in the auxiliary level unit is connected with the source end of the second N-type field effect transistor in the auxiliary level unit, and the source end of the first P-type field effect transistor in the auxiliary level unit is connected with the source end of the second P-type field effect transistor in the auxiliary level unit.
6. The circuit of claim 5, wherein the auxiliary stage unit further comprises a third capacitor and a fourth capacitor, one end of the third capacitor is used for receiving a third driving clock signal, and the other end of the third capacitor is connected to the drain of the first NFET in the auxiliary stage unit and the drain of the first PFET in the auxiliary stage unit, one end of the fourth capacitor is connected to a fourth driving clock signal, and the other end of the fourth capacitor is connected to the drain of the second NFET in the auxiliary stage unit and the drain of the second PFET in the auxiliary stage unit;
wherein the third driving clock signal and the fourth driving clock signal are complementary driving clock signals.
7. The circuit of claim 5, wherein a source terminal of a first NFET in the secondary cell is connected to a source terminal of a second NFET in the secondary cell and to a source terminal of a first PFET in the last charge pump cell and a source terminal of a second PFET in the last charge pump cell.
8. The circuit of claim 1, wherein a body terminal of a first P-type field effect transistor in the first stage charge pump unit is configured to receive a fifth driving clock signal, wherein a body terminal of a second P-type field effect transistor in the first stage charge pump unit is configured to receive a sixth driving clock signal, and wherein the fifth driving clock signal and the driving clock signal are complementary driving clock signals.
9. A chip comprising a charge pump circuit as claimed in any one of claims 1 to 8.
10. An electronic device comprising the chip of claim 9.
CN202211021916.6A 2022-08-24 2022-08-24 Charge pump circuit, chip and electronic equipment Active CN115224932B (en)

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CN106208681A (en) * 2016-07-19 2016-12-07 天津大学 Low-voltage low ripple multi stage charge pump
CN108418418A (en) * 2018-03-06 2018-08-17 芯海科技（深圳）股份有限公司 A kind of adaptive bi-directional charge pump dynamic regulator for this body bias of metal-oxide-semiconductor

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US9634559B2 (en) * 2014-02-07 2017-04-25 The Hong Kong University Of Science And Technology Charge pumping apparatus for low voltage and high efficiency operation
US10033271B1 (en) * 2016-12-30 2018-07-24 Texas Instruments Incorporated Multi-stage charge pump
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CN104205594A (en) * 2012-03-23 2014-12-10 Soitec公司 Charge pump circuit comprising multiple - gate transistors and method of operating the same
CN106208681A (en) * 2016-07-19 2016-12-07 天津大学 Low-voltage low ripple multi stage charge pump
CN108418418A (en) * 2018-03-06 2018-08-17 芯海科技（深圳）股份有限公司 A kind of adaptive bi-directional charge pump dynamic regulator for this body bias of metal-oxide-semiconductor

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