CN112564673B - Clock duty cycle adjusting circuit - Google Patents

Clock duty cycle adjusting circuit Download PDF

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Publication number
CN112564673B
CN112564673B CN202011476192.5A CN202011476192A CN112564673B CN 112564673 B CN112564673 B CN 112564673B CN 202011476192 A CN202011476192 A CN 202011476192A CN 112564673 B CN112564673 B CN 112564673B
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tube
resistor
pmos
nmos
clock signal
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CN112564673A (en
Inventor
陈雷
李智
李学武
孙华波
张健
林彦君
王科迪
杨铭谦
付勇
杨佳奇
单程奕
吕小龙
陈宇峥
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention relates to a clock duty ratio adjusting circuit, which belongs to the field of design of an FPGA internal clock network; comprising a buffer B100, 2 coarse tuning circuits B110 and a fine tuning circuit B120; the invention has a larger adjusting range by adopting a mode of combining a coarse adjusting circuit and a fine adjusting circuit, and can adjust a harsher initial clock signal; the clock duty cycle adjustment circuit is specially designed for being applied to an FPGA device, has a larger duty cycle adjustment range compared with other DCC circuits, and can adjust a very severe clock (the duty cycle is less than 20% or more than 80%).

Description

Clock duty cycle adjusting circuit
Technical Field
The invention belongs to the field of design of an FPGA internal clock network, and relates to a clock duty ratio adjusting circuit.
Background
With the increase of the complexity of the electronic system, the working speed of the system is higher and higher, and higher requirements are put on an on-chip clock network. As the on-chip clock path lengthens, timing constraints tighten, performance losses or further functional errors due to deviations from the ideal (50%) clock duty cycle have become unacceptable. A special clock duty cycle adjustment circuit (Duty Cycle Corrector, DCC for short) is designed to adjust the duty cycle of the clock.
There have been many studies on DCC with high speed and high accuracy, and different designs have different adjustment ranges, adjustment accuracies, and adjustment times. In general, DCCs can be divided into 3 types: analog DCC, digital DCC, and mixed signal DCC. Generally speaking, the analog DCC uses a feedback structure, which has the highest adjustment accuracy but the longest adjustment time; the digital DCC does not use a feedback structure, has the highest adjustment speed, but has the worst adjustment precision; the mixed signal DCC has moderate adjustment accuracy and adjustment speed. The DCCs of the various types may have different structures and different adjustment ranges, and typically may process clocks having duty cycles between 20% and 80%.
An adjustment range of 20% to 80% is sufficient for an ASIC, but not enough for a Field Programmable Gate Array (FPGA). An FPGA is a special integrated circuit whose specific implementation functions are defined by software. Unlike the ASIC-customized clock network, the FPGA is internally designed with a large number of global clock networks that are used to transfer clocks throughout the FPGA. Since the user of the FPGA may also use an external clock source that is not PLL processed, the duty cycle of the initial clock may already deviate from the ideal value. A large number of buffers are inserted in a longer clock path, and the buffers usually have only a small influence on the clock duty ratio, but when a large number of clock buffers are connected in series in the same path, the clock duty ratio is caused to deviate from an ideal value seriously. These factors result in very severe duty cycle distortion of the global clock network within the FPGA.
Disclosure of Invention
The invention solves the technical problems that: the defect of the prior art is overcome, and the clock duty ratio adjusting circuit is provided, so that a larger duty ratio adjusting range is used, and a worse initial input clock duty ratio can be tolerated.
The solution of the invention is as follows:
a clock duty cycle adjusting circuit comprises a buffer B100, 2 coarse adjusting circuits B110 and a fine adjusting circuit B120;
wherein the buffer B100 receives the input clock signals clkp_in and clkn_in; buffering the input clock signal clkp_in to generate a buffered clock signal clkp_b; buffering the input clock signal clkn_in to generate a buffered clock signal clkn_b; transmitting the buffered clock signal clkp_b to 1 of the coarse tuning circuits B110; transmitting the buffered clock signal clkn_b to another coarse tuning circuit B110;
coarse tuning circuit B110: receiving the buffered clock signal clkp_b or the buffered clock signal clkn_b from the buffer B100; coarsely adjusting the duty ratio of the buffered clock signal clkp_b or the buffered clock signal clkn_b to generate a clock signal clkp_c and a clock signal clkn_c; and sends clock signal clkp_c and clock signal clkn_c to fine tuning circuit B120;
fine-tuning circuit B120: receiving the clock signal clkp_c and the clock signal clkn_c from the 2 coarse tuning circuits B110; the duty ratios of the clock signals clkp_c and clkn_c are finely adjusted to generate output clock signals clkp_out and clkn_out.
In the above-mentioned clock duty cycle adjusting circuit, the buffer B100 includes a differential comparator a; the positive input end of the differential comparator A receives a clock signal CLKP_IN; the negative input of the differential comparator A receives the clock signal CLKN_IN; buffering the clock signal clkp_in to generate a buffered clock signal clkp_b; outputting the buffered clock signal clkp_b to 1 of the coarse tuning circuits B110 through the positive output terminal; buffering the clock signal clkn_in to generate a buffered clock signal clkn_b; the buffered clock signal clkn_b is output to the other coarse tuning circuit B110 through the negative output terminal.
In the above-mentioned clock duty cycle adjustment circuit, the coarse adjustment circuit B110 includes a PMOS transistor P200, a PMOS transistor P201, a PMOS transistor P202, a PMOS transistor P203, an NMOS transistor N210, an NMOS transistor N211, an NMOS transistor N212, an NMOS transistor N213, a resistor R220, a resistor R221, a resistor R222, a resistor R223, a resistor R224, a resistor R225, a resistor R226, a resistor R227, a resistor R228, a resistor R229, a capacitor C230, a capacitor C231, a capacitor C232, an operational amplifier a240, and an operational amplifier a241;
the input port of the coarse tuning circuit B110 is CLK_B, and the output port is CLK_C; the grid electrode of the PMOS tube P200 is connected with the input port CLK_B and is simultaneously connected with the grid electrode of the NMOS tube N210; the source electrode of the PMOS tube P200 is connected with the drain electrode of the PMOS tube P201; the drain electrode of the PMOS tube P200 is connected with the output end CLK_C, and is simultaneously connected with the source electrode of the PMOS tube P203, the drain electrode of the NMOS tube N210, the source electrode of the NMOS tube N213, the first end of the capacitor C232, the inverting input end of the operational amplifier A240 and the inverting input end of the operational amplifier A241; the grid electrode of the PMOS tube P201 is connected with the drain electrode of the PMOS tube P202, the first end of the resistor R220 and the first end of the capacitor C230; the source electrode of the PMOS tube P201 is connected with a power supply; the grid electrode of the PMOS tube P202 is connected with the output end of the operational amplifier A240; the source electrode of the PMOS tube P202 is connected with a power supply; the grid electrode of the PMOS tube P203 is connected with the second end of the resistor R228 and the first end of the resistor R229; the drain electrode of the PMOS tube P203 is connected with the ground; the source electrode of the NMOS tube N210 is connected with the drain electrode of the NMOS tube N211; the grid electrode of the NMOS tube N211 is connected with the drain electrode of the NMOS tube N212, the second end of the resistor R221 and the second end of the capacitor C231; the source electrode of the NMOS tube N211 is connected with the ground; the grid electrode of the NMOS tube N212 is connected with the output end of the operational amplifier A241; the source electrode of the NMOS tube N212 is connected with the ground; the grid electrode of the NMOS tube N213 is connected with the second end of the resistor R226 and the first end of the resistor R227; the drain electrode of the NMOS tube N213 is connected with a power supply; a second end of the resistor R220 is connected with ground; a first end of the resistor R221 is connected with a power supply; the first end of the resistor R222 is connected with a power supply; the second end of the resistor R222 is connected with the first end of the resistor R223 and the non-inverting input end of the operational amplifier A240; the second end of the resistor R223 is connected with the first end of the resistor R224; the second end of the resistor R224 is connected with the first end of the resistor R225 and the non-inverting input end of the operational amplifier A241; the second end of the resistor R225 is connected with ground; the first end of the resistor R226 is connected with a power supply; the second end of the resistor R227 is connected with ground; a first end of the resistor R228 is connected with a power supply; a second terminal of resistor R229 is connected to ground; the second end of the capacitor C230 is connected with the ground; the first end of the capacitor C231 is connected with a power supply; the second terminal of the capacitor C232 is connected to ground.
In the above-mentioned clock duty cycle adjusting circuit, the fine adjusting circuit B120 includes a PMOS transistor P400, a PMOS transistor P401, a PMOS transistor P402, a PMOS transistor P403, a PMOS transistor P404, a PMOS transistor P405, a PMOS transistor P406, a PMOS transistor P407, a PMOS transistor P408, a PMOS transistor P409, an NMOS transistor N410, an NMOS transistor N411, an NMOS transistor N412, an NMOS transistor N413, an NMOS transistor N414, an NMOS transistor N415, an NMOS transistor N416, an NMOS transistor N417, an NMOS transistor N418, an NMOS transistor N419, a resistor R420, a capacitor C430, a capacitor C431, an inverter G440, an inverter G441, an inverter G442, an inverter G443, an inverter G444, and an inverter G445;
the input ports of the fine tuning circuit B120 are clkn_c and clkp_c; the output ports are CLKN_OUT and CLKP_OUT;
the grid electrode of the PMOS tube P400 is connected with the grid electrode of the PMOS tube P401, the drain electrode of the PMOS tube P402, the grid electrode of the PMOS tube P403 and the drain electrode of the NMOS tube N410; the source electrode of the PMOS tube P400 is connected with a power supply; the drain electrode of the PMOS tube P400 is connected with the drain electrode of the NMOS tube N412 and the input end of the NOT gate G440; the source electrode of the PMOS tube P401 is connected with a power supply; the grid electrode of the PMOS tube P402 is connected with the drain electrode of the PMOS tube P403, the grid electrode of the PMOS tube P404, the drain electrode of the PMOS tube P404, the grid electrode of the PMOS tube P405 and the drain electrode of the NMOS tube N411; the source electrode of the PMOS tube P402 is connected with a power supply; the source electrode of the PMOS tube P403 is connected with a power supply; the source electrode of the PMOS tube P404 is connected with a power supply; the source electrode of the PMOS tube P405 is connected with a power supply; the drain of the PMOS tube P405 is connected with the drain of the NMOS tube N415 and the input end of the NOT gate G441; the grid electrode of the PMOS tube P406 is connected with the grid electrode of the PMOS tube P409, the drain electrode of the PMOS tube P409 and the first end of the resistor R420; the source electrode of the PMOS tube P406 is connected with a power supply; the drain electrode of the PMOS tube P406 is connected with the source electrode of the PMOS tube P407 and the source electrode of the PMOS tube P408; the grid electrode of the PMOS tube P407 is connected with the grid electrode of the NMOS tube N416, the output end of the NOT gate G441, the output end of the NOT gate G442, the input end of the NOT gate G443 and the input end of the NOT gate G445; the drain electrode of the PMOS tube P407 is connected with the grid electrode of the NMOS tube N412, the grid electrode of the NMOS tube N413, the drain electrode of the NMOS tube N416, the grid electrode of the NMOS tube N418 and the first end of the capacitor C430; the grid of the PMOS tube P408 is connected with the grid of the NMOS tube N417, the output end of the NOT gate G440, the input end of the NOT gate G442, the output end of the NOT gate G443 and the input end of the NOT gate G444; the drain electrode of the PMOS tube P408 is connected with the grid electrode of the NMOS tube N414, the grid electrode of the NMOS tube N415, the drain electrode of the NMOS tube N417, the grid electrode of the NMOS tube N419 and the first end of the capacitor C431; the source electrode of the PMOS tube P409 is connected with a power supply; the gate of the NMOS transistor N410 is connected to the input port clkn_c; the source end of the NMOS tube N410 is connected with the source electrode of the NMOS tube N411, the drain electrode of the NMOS tube N413 and the drain electrode of the NMOS tube N414; the gate of the NMOS transistor N411 is connected with an input port CLKP_C; the source electrode of the NMOS tube N412 is connected with the ground; the source electrode of the NMOS tube N413 is connected with the ground; the source electrode of the NMOS tube N414 is connected with the ground; the source electrode of the NMOS tube N415 is connected with the ground; the source electrode of the NMOS tube N416 is connected with the drain electrode of the NMOS tube N418; the source electrode of the NMOS tube N417 is connected with the drain electrode of the NMOS tube N419; the source electrode of the NMOS tube N418 is connected with the ground; the source electrode of the NMOS tube N419 is connected with the ground; the second end of the resistor R420 is connected with ground; the second end of the capacitor C430 is connected to ground; a second end of the capacitor C431 is connected with the ground; the output end of the NOT gate G444 is connected with an output port CLKN_OUT; the output terminal of the not gate G445 is connected to the output port clkp_out.
Compared with the prior art, the invention has the beneficial effects that:
(1) The clock duty cycle adjusting circuit of the invention uses a larger duty cycle adjusting range, and can endure a worse initial input clock duty cycle.
Drawings
FIG. 1 is a schematic diagram of a duty cycle adjustment circuit according to the present invention;
FIG. 2 is a schematic diagram of a coarse tuning circuit B110 according to the present invention;
FIG. 3 is a schematic diagram of a fine-tuning circuit B120 according to the present invention;
FIG. 4 is a schematic diagram of the input/output waveforms of the coarse tuning circuit according to the present invention;
FIG. 5 is a schematic diagram of the input/output waveforms of the fine-tuning circuit according to the present invention.
Detailed Description
The invention is further illustrated below with reference to examples.
The clock duty cycle adjusting circuit is specially designed for being applied to an FPGA device, has a larger duty cycle adjusting range compared with other DCC circuits, and can adjust very bad clocks (the duty cycle is smaller than 20% or larger than 80%).
The clock duty cycle adjusting circuit, as shown in fig. 1, includes a buffer B100, 2 coarse adjusting circuits B110, and a fine adjusting circuit B120; the 2 coarse tuning circuits B110 are identical in structure and parameters.
Wherein the buffer B100 receives the input clock signals clkp_in and clkn_in; buffering the input clock signal clkp_in to generate a buffered clock signal clkp_b; buffering the input clock signal clkn_in to generate a buffered clock signal clkn_b; transmitting the buffered clock signal clkp_b to 1 of the coarse tuning circuits B110; transmitting the buffered clock signal clkn_b to another coarse tuning circuit B110;
coarse tuning circuit B110: receiving the buffered clock signal clkp_b or the buffered clock signal clkn_b from the buffer B100; coarsely adjusting the duty ratio of the buffered clock signal clkp_b or the buffered clock signal clkn_b to generate a clock signal clkp_c and a clock signal clkn_c; and sends clock signal clkp_c and clock signal clkn_c to fine tuning circuit B120;
fine-tuning circuit B120: receiving the clock signal clkp_c and the clock signal clkn_c from the 2 coarse tuning circuits B110; the duty ratios of the clock signals clkp_c and clkn_c are finely adjusted to generate output clock signals clkp_out and clkn_out.
As shown in fig. 1, the buffer B100 includes a differential comparator a; the positive input end of the differential comparator A receives a clock signal CLKP_IN; the negative input of the differential comparator A receives the clock signal CLKN_IN; buffering the clock signal clkp_in to generate a buffered clock signal clkp_b; outputting the buffered clock signal clkp_b to 1 of the coarse tuning circuits B110 through the positive output terminal; buffering the clock signal clkn_in to generate a buffered clock signal clkn_b; the buffered clock signal clkn_b is output to the other coarse tuning circuit B110 through the negative output terminal.
As shown in fig. 2, the coarse tuning circuit B110 includes a PMOS transistor P200, a PMOS transistor P201, a PMOS transistor P202, a PMOS transistor P203, an NMOS transistor N210, an NMOS transistor N211, an NMOS transistor N212, an NMOS transistor N213, a resistor R220, a resistor R221, a resistor R222, a resistor R223, a resistor R224, a resistor R225, a resistor R226, a resistor R227, a resistor R228, a resistor R229, a capacitor C230, a capacitor C231, a capacitor C232, an operational amplifier a240, and an operational amplifier a241;
the input port of the coarse tuning circuit B110 is CLK_B, and the output port is CLK_C; the grid electrode of the PMOS tube P200 is connected with the input port CLK_B and is simultaneously connected with the grid electrode of the NMOS tube N210; the source electrode of the PMOS tube P200 is connected with the drain electrode of the PMOS tube P201; the drain electrode of the PMOS tube P200 is connected with the output end CLK_C, and is simultaneously connected with the source electrode of the PMOS tube P203, the drain electrode of the NMOS tube N210, the source electrode of the NMOS tube N213, the first end of the capacitor C232, the inverting input end of the operational amplifier A240 and the inverting input end of the operational amplifier A241; the grid electrode of the PMOS tube P201 is connected with the drain electrode of the PMOS tube P202, the first end of the resistor R220 and the first end of the capacitor C230; the source electrode of the PMOS tube P201 is connected with a power supply; the grid electrode of the PMOS tube P202 is connected with the output end of the operational amplifier A240; the source electrode of the PMOS tube P202 is connected with a power supply; the grid electrode of the PMOS tube P203 is connected with the second end of the resistor R228 and the first end of the resistor R229; the drain electrode of the PMOS tube P203 is connected with the ground; the source electrode of the NMOS tube N210 is connected with the drain electrode of the NMOS tube N211; the grid electrode of the NMOS tube N211 is connected with the drain electrode of the NMOS tube N212, the second end of the resistor R221 and the second end of the capacitor C231; the source electrode of the NMOS tube N211 is connected with the ground; the grid electrode of the NMOS tube N212 is connected with the output end of the operational amplifier A241; the source electrode of the NMOS tube N212 is connected with the ground; the grid electrode of the NMOS tube N213 is connected with the second end of the resistor R226 and the first end of the resistor R227; the drain electrode of the NMOS tube N213 is connected with a power supply; a second end of the resistor R220 is connected with ground; a first end of the resistor R221 is connected with a power supply; the first end of the resistor R222 is connected with a power supply; the second end of the resistor R222 is connected with the first end of the resistor R223 and the non-inverting input end of the operational amplifier A240; the second end of the resistor R223 is connected with the first end of the resistor R224; the second end of the resistor R224 is connected with the first end of the resistor R225 and the non-inverting input end of the operational amplifier A241; the second end of the resistor R225 is connected with ground; the first end of the resistor R226 is connected with a power supply; the second end of the resistor R227 is connected with ground; a first end of the resistor R228 is connected with a power supply; a second terminal of resistor R229 is connected to ground; the second end of the capacitor C230 is connected with the ground; the first end of the capacitor C231 is connected with a power supply; the second terminal of the capacitor C232 is connected to ground.
As shown in fig. 3, the fine adjustment circuit B120 includes a PMOS transistor P400, a PMOS transistor P401, a PMOS transistor P402, a PMOS transistor P403, a PMOS transistor P404, a PMOS transistor P405, a PMOS transistor P406, a PMOS transistor P407, a PMOS transistor P408, a PMOS transistor P409, an NMOS transistor N410, an NMOS transistor N411, an NMOS transistor N412, an NMOS transistor N413, an NMOS transistor N414, an NMOS transistor N415, an NMOS transistor N416, an NMOS transistor N417, an NMOS transistor N418, an NMOS transistor N419, a resistor R420, a capacitor C430, a capacitor C431, an inverter G440, an inverter G441, an inverter G442, an inverter G443, an inverter G444, and an inverter G445;
the input ports of the fine tuning circuit B120 are clkn_c and clkp_c; the output ports are CLKN_OUT and CLKP_OUT;
the grid electrode of the PMOS tube P400 is connected with the grid electrode of the PMOS tube P401, the drain electrode of the PMOS tube P402, the grid electrode of the PMOS tube P403 and the drain electrode of the NMOS tube N410; the source electrode of the PMOS tube P400 is connected with a power supply; the drain electrode of the PMOS tube P400 is connected with the drain electrode of the NMOS tube N412 and the input end of the NOT gate G440; the source electrode of the PMOS tube P401 is connected with a power supply; the grid electrode of the PMOS tube P402 is connected with the drain electrode of the PMOS tube P403, the grid electrode of the PMOS tube P404, the drain electrode of the PMOS tube P404, the grid electrode of the PMOS tube P405 and the drain electrode of the NMOS tube N411; the source electrode of the PMOS tube P402 is connected with a power supply; the source electrode of the PMOS tube P403 is connected with a power supply; the source electrode of the PMOS tube P404 is connected with a power supply; the source electrode of the PMOS tube P405 is connected with a power supply; the drain of the PMOS tube P405 is connected with the drain of the NMOS tube N415 and the input end of the NOT gate G441; the grid electrode of the PMOS tube P406 is connected with the grid electrode of the PMOS tube P409, the drain electrode of the PMOS tube P409 and the first end of the resistor R420; the source electrode of the PMOS tube P406 is connected with a power supply; the drain electrode of the PMOS tube P406 is connected with the source electrode of the PMOS tube P407 and the source electrode of the PMOS tube P408; the grid electrode of the PMOS tube P407 is connected with the grid electrode of the NMOS tube N416, the output end of the NOT gate G441, the output end of the NOT gate G442, the input end of the NOT gate G443 and the input end of the NOT gate G445; the drain electrode of the PMOS tube P407 is connected with the grid electrode of the NMOS tube N412, the grid electrode of the NMOS tube N413, the drain electrode of the NMOS tube N416, the grid electrode of the NMOS tube N418 and the first end of the capacitor C430; the grid of the PMOS tube P408 is connected with the grid of the NMOS tube N417, the output end of the NOT gate G440, the input end of the NOT gate G442, the output end of the NOT gate G443 and the input end of the NOT gate G444; the drain electrode of the PMOS tube P408 is connected with the grid electrode of the NMOS tube N414, the grid electrode of the NMOS tube N415, the drain electrode of the NMOS tube N417, the grid electrode of the NMOS tube N419 and the first end of the capacitor C431; the source electrode of the PMOS tube P409 is connected with a power supply; the gate of the NMOS transistor N410 is connected to the input port clkn_c; the source end of the NMOS tube N410 is connected with the source electrode of the NMOS tube N411, the drain electrode of the NMOS tube N413 and the drain electrode of the NMOS tube N414; the gate of the NMOS transistor N411 is connected with an input port CLKP_C; the source electrode of the NMOS tube N412 is connected with the ground; the source electrode of the NMOS tube N413 is connected with the ground; the source electrode of the NMOS tube N414 is connected with the ground; the source electrode of the NMOS tube N415 is connected with the ground; the source electrode of the NMOS tube N416 is connected with the drain electrode of the NMOS tube N418; the source electrode of the NMOS tube N417 is connected with the drain electrode of the NMOS tube N419; the source electrode of the NMOS tube N418 is connected with the ground; the source electrode of the NMOS tube N419 is connected with the ground; the second end of the resistor R420 is connected with ground; the second end of the capacitor C430 is connected to ground; a second end of the capacitor C431 is connected with the ground; the output end of the NOT gate G444 is connected with an output port CLKN_OUT; the output terminal of the not gate G445 is connected to the output port clkp_out.
The basic working process of the clock duty ratio adjusting circuit is as follows: the buffer B100 buffers the input clock signals clkp_in and clkn_in to generate clock signals clkp_b and clkn_b. The coarse tuning circuit B110 receives the clock signal clkp_b, performs coarse tuning on the duty cycle thereof, and generates an internal clock signal clkn_c; the other coarse tuning circuit B110 receives the clock signal clkn_b, and performs coarse tuning on the duty cycle thereof to generate a clock signal clkp_c. After the coarse tuning circuit, the duty cycle of the internal clock signals clkp_c and clkn_c is close to the ideal value of 50%, but is not accurate, and the use requirement is still not satisfied. The fine tuning circuit B120 receives the internal clock signals clkp_c and clkn_c, further precisely adjusts the duty cycle to an ideal value of 50%, and finally generates the output clock signals clkp_out and clkn_out. The invention has the advantages that the adjustment range of the duty ratio of the coarse adjustment circuit clock is very large, but the adjustment precision is not enough; the fine-tuning circuit clock has a small duty cycle adjustment range, and only can finely adjust the duty cycle, but the adjustment accuracy is high. The invention firstly uses the coarse adjustment circuit to initially adjust the duty ratio, and then uses the fine adjustment circuit to adjust the duty ratio, so that on one hand, the whole adjustment range can reach the adjustment range of the coarse adjustment circuit, and on the other hand, the adjustment precision can reach the adjustment precision of the fine adjustment circuit.
In the coarse tuning circuit, an NMOS tube N213, a resistor R226, and a resistor R227 form a clamp circuit. When the level of the output clock signal clk_c is lower than a certain voltage vc_l (lower than 1/4 of the power supply voltage), the NMOS transistor N213 is turned on, so that the level of the output clock signal clk_c cannot be further reduced, and the level thereof is clamped on vc_l. The resistance ratio of resistor R226 to resistor R227 needs to satisfy the following relationship, where V VDD Is the power supply voltage, V THN Is the threshold voltage of the NMOS tube.
In the coarse tuning circuit, the PMOS transistor P203, the resistor R228, and the resistor R229 form another clamping circuit. When the level of the output clock signal clk_c is higher than a certain voltage vc_h (3/4 higher than the power supply voltage), the PMOS transistor P203 is turned on, so that the level of the output clock signal clk_c cannot continue to rise, and the level thereof is clamped on vc_h. The resistance ratio of resistor R228 to resistor R229 needs to satisfy the relationship, where V VDD Is the power supply voltage, V THP Is the threshold voltage of the PMOS tube.
The resistor R222, the resistor R223, the resistor R224 and the resistor R225 form a voltage-generating network, and the four resistors have the same resistance value and generate two bias voltages: one is the power supply voltage V VDD 3/4 of the sum, is fed to the non-inverting input of op-amp A240; the other is the power supply voltage V VDD 1/4 of (a) is fed to the non-inverting input of the operational amplifier a 241.
The PMOS tube P200, the PMOS tube P201, the NMOS tube N210, the NMOS tube N201 and the capacitor C232 form a charge pump. When the input clock signal clk_b is at a high level, the NMOS transistor N210 is turned on, and the NMOS transistor N211 discharges the capacitor C232 to decrease the level of the output clock signal clk_c; when the input clock signal clk_b is at a low level, the PMOS transistor P200 is turned on, and the PMOS transistor P201 charges the capacitor C232 to increase the output clock signal clk_c.
The working principle of the circuit is respectively described from the three states of starting working, adjusting and stabilizing working:
a) Starting to work: when the power is on, no charge is stored in the capacitor C230 and the capacitor C231, so that the PMOS tube P201 and the NMOS tube N211 are in a complete conduction state, the charge and discharge currents of the capacitor C232 are very large, and the rising and falling speeds of the level of the output clock signal CLK_C are very fast. As shown in fig. 4, when the input clock signal clk_b is at a high level, the output clock signal clk_c will fall rapidly until its level is clamped to vc_l by the NMOS transistor N213; when the input clock signal clk_b is low, the output clock signal clk_c will rise rapidly until its level is clamped to vc_h by the PMOS transistor P203. The waveform is shown in fig. 4.
b) In the adjustment process: how the circuit operates in two cases, namely, the high level and the low level of the input clock signal are respectively described as follows: 1) When the input clock signal CLK_B is high, the CLK_C level falls, when the CLK_C level is lower than the supply voltage V VDD At 1/4 of the time, the operational amplifier A241 generates a high level to turn on the NMOS transistor N212. The NMOS transistor N212 charges the capacitor C231, so that the gate level of the NMOS transistor N211 decreases, and the on-current of the NMOS transistor N211 decreases, thereby decreasing the rate of decrease of the level of the output clock signal clk_c. The above process will continue until the output clock signal CLK_C is exactly equal to the supply voltage V when the input clock signal CLK_B goes low VDD 1/4 of (C). b) When the input clock signal CLK_B is low, the CLK_C level rises and when the CLK_C level is higher than the supply voltage V VDD At 3/4 of the time, the operational amplifier A240 generates a low level to turn on the PMOS transistor P202. The PMOS transistor P202 charges the capacitor C230, so that the gate level of the PMOS transistor P201 increases, and the on-current of the PMOS transistor P201 decreases, thereby decreasing the rising speed of the output clock signal clk_c level. The above process will continue until the output clock signal CLK_C is exactly equal to the supply voltage V when the input clock signal CLK_B goes high VDD 3/4 of (C).
c) Stable operation: the resistor R220 discharges the capacitor C230, so that the gate potential of the PMOS transistor P201 decreases, the on current increases, and the rising speed of the output clock signal clk_c increases. When the level of CLK_C appears higher than the supply voltage V VDD In the 3/4 state, the operational amplifier A240 generates a low level to charge the capacitor C230 through the PMOS tube P202, and counteracts the discharge effect of the resistor R220 on the capacitor C230. Resistor R221 discharges capacitor C231 to raise the gate potential of NMOS tube P211, increase its on-current, and output clock signal CLK_C levelThe descent speed is accelerated. When the level of CLK_C appears lower than the supply voltage V VDD In the 1/4 state, the operational amplifier A241 generates a high level, charges the capacitor C231 through the NMOS transistor N212, and counteracts the influence of the resistor R220 on the discharging of the capacitor C230. In a steady state, the output clock signal CLK_C will become a triangular wave whose level is at the supply voltage V VDD 1/4 of (V) to the power supply voltage VDD Within 3/4 of the above, the waveform is shown in FIG. 4. The function of resistor R220 and resistor R221 is twofold: 1) The PMOS tube P201 and the NMOS tube N211 are ensured to be in a complete conduction state in the initial working state of the circuit; 2) The parasitic currents of the PMOS transistor P202 and the NMOS transistor N212 are offset to charge the capacitor C230/C231.
From the above analysis, the duty cycle of the output clock signal clk_c will be very close to 50% when the coarse tuning circuit is operating stably, but the duty cycle cannot be maintained exactly at 50% because the circuit is in the state of operation balance. Thus requiring further adjustment of the duty cycle of the clock signal by the fine tuning circuit.
The circuit structure of the fine-tuning circuit is shown in fig. 3. The method comprises the following steps: PMOS tube P400, PMOS tube P401, PMOS tube P402, PMOS tube P403, PMOS tube P404, PMOS tube P405, PMOS tube P406, PMOS tube P407, PMOS tube P408, PMOS tube P409, NMOS tube N410, NMOS tube N411, NMOS tube N412, NMOS tube N413, NMOS tube N414, NMOS tube N415, NMOS tube N416, NMOS tube N417, NMOS tube N418, NMOS tube N419, resistor R420, capacitor C430, capacitor C431, NOT G440, NOT G441, NOT G442, NOT G443, NOT G444, NOT G445.
In the fine tuning circuit, a differential comparator is formed by a PMOS transistor P400, a PMOS transistor P401, a PMOS transistor P402, a PMOS transistor P403, a PMOS transistor P404, a PMOS transistor P405, an NMOS transistor N410, an NMOS transistor N411, an NMOS transistor N412, an NMOS transistor N413, an NMOS transistor N414, an NMOS transistor N415, an inverter gate G440, and an inverter gate G441. The difference between the differential comparator and the traditional differential comparator is that the grid connection modes of the NMOS tube N412, the NMOS tube N413, the NMOS tube N414 and the NMOS tube N415 are different. In the fine tuning circuit of the present invention, the gates of the NMOS transistors N412 and N413 are connected to one bias voltage (vb_l), the gates of the NMOS transistors N414 and N415 are connected to the other bias voltage (vb_r), and the voltages may be different when the vb_l and vb_r are in the dynamic tuning state. In a conventional differential comparator, VB_L and VB_R will be connected together and the output will change state when the input signals CLKN_C and CLKP_C are equal. In the invention, because VB_L and VB_R are different, controllable offset is introduced in the comparison of the input signals CLKN_C and CLKP_C, namely the output changes state when the CLKN_C is slightly larger or slightly smaller than the CLKP_C, thereby achieving the purpose of adjusting the duty ratio. The following analysis shows that VB_L is equal to VB_ R, VB _L and VB_ R, VB _L is smaller than VB_R. For convenience of description, the node connected to the drain of the PMOS transistor P400, the drain of the NMOS transistor N412, and the input of the not gate G440 is denoted as LL, and the node connected to the drain of the PMOS transistor P450, the drain of the NMOS transistor N415, and the input of the not gate G441 is denoted as RR.
a) When VB_L is equal to VB_R: the circuit is in a fully symmetrical state, and clkn_c and clkp_c are equal when node LL and node RR are equal in level. When clkn_c and clkp_c levels change, the node LL and node RR levels will follow the change. It can be seen that when VB_L and the like say VB_R, the level change time between the node LL and the node RR is when CLKN_C is equal to CLKP_C.
b) When VB_L is greater than VB_R: the circuit is in an asymmetric state. Clkn_c and clkp_c are not equal when node LL and node RR are equal in level. Since VB_L is greater than VB_R, the current of NMOS transistor N412 is greater and the current of NMOS transistor N415 is smaller, if the level of node LL and node RR are to be equal, the current of PMOS transistor P400 must be greater than the current of PMOS transistor P405, and then CLKN_C must be greater than CLKP_C. It can be seen that when VB_L is greater than VB_R, node LL and node RR change level at times CLKN_C slightly greater than CLKP_C.
c) When VB_L is less than VB_R: the circuit is in an asymmetric state. Similarly to the case where vb_l is smaller than vb_r, in this case, when the level change time of the node LL and the node RR is clkn_c slightly smaller than clkp_c.
By adjusting the magnitudes of VB_L and VB_R, the differential comparator can adjust the moment when the circuit changes state, namely, the relative time of high and low output levels is adjusted, so that the purpose of adjusting the duty ratio is achieved.
The NOT gates G442 and G443 form a Latch structure, which shapes the output of the differential comparator and generates clock signals CLKN_N and CLKP_N.
The PMOS tube P406, the PMOS tube P407, the PMOS tube P408, the PMOS tube P409, the NMOS tube N416, the NMOS tube N417, the NMOS tube N418, the NMOS tube N419 and the resistor R420 form a bias generating circuit, and bias voltages VB_L and VB_R are controlled according to states of clock signals CLKN_N and CLKP_N to control adjustment of clock duty ratio. Resistor R420 and PMOS tube P409 are used to determine the current in PMOS tube P406, denoted IREF. When clkn_n is low and clkp_n is high, the capacitor C430 is charged through the PMOS transistor P407, and the capacitor C431 is discharged through the NMOS transistors N417 and N419; when clkn_n is high and clkp_n is low, the capacitor C430 is discharged through the NMOS transistor N416, the NMOS transistor N418, and the capacitor C431 is charged through the PMOS transistor P408. Assuming that the clock cycle is T and clkp_n is higher than the proportion P of clkn_n, the charge amount for charging the capacitor C430 per cycle is:
Q＝IREF×T×P％
the amount of charge discharged to capacitor C430 per cycle is:
wherein mu is N Carrier mobility of NMOS tube, C ox The gate oxide capacitance per unit area of the HMOS transistor,is the width-to-length ratio of the NMOS tube. When the circuit works in a stable state, charge and discharge charges are equal, and the relationship between VB_L and P can be obtained as follows:
in the same way, the relationship between VB_R and P can be obtained as follows:
it can be seen that: when P is equal to 50, vb_l is equal to vb_r; when P is greater than 50, VB_L is greater than VB_R; when P is less than 50, VB_L is less than VB_R. It can be seen that VB_L and VB_R are adjusted as the duty cycle of the difference clock signals CLKN_N and CLKP_N changes.
The operation principle of the fine-tuning circuit is described below by analyzing the specific waveform, and the operation waveform of the fine-tuning circuit can be shown in fig. 5. As shown in fig. 5 (a), the three cases where the split duty ratio is equal to 50%, the split duty ratio is greater than 50%, and the split duty ratio is less than 50% are explained according to the duty ratio of the input clock:
a) The input clock duty cycle is equal to 50%: the internal clock signal clkn_n and clkp_n have the same high and low level time, the circuit is completely symmetrical, and vb_l and vb_r are equal. At this time, the output clock starts to change state when clkn_c and clkp_c are completely equal, as shown in fig. 5 (b).
b) The input clock duty cycle is less than 50%: the time duty cycle P% of the internal clock signal clkp_n below clkn_n will be less than 50%, where vb_l is less than vb_r, and the circuit will change state when clkn_c is slightly less than clkp_c, as shown in fig. 5 (C). At this time, the fine-tuning circuit increases the duty ratio of the clock.
c) The input clock duty cycle is greater than 50%: the time duty cycle P% of the internal clock signal clkp_n above clkn_n will be greater than 50%, where vb_l is greater than vb_r, and the circuit will change state when clkn_c is slightly greater than clkp_c, as shown in fig. 5 (d). At this time, the fine-tuning circuit reduces the duty ratio of the clock.
From the above analysis, the fine tuning circuit can adjust according to the clock state: the fine-tuning circuit reduces its duty cycle as long as the high level state in the current clock cycle exceeds 50%; the fine-tuning circuit increases its duty cycle as long as the high state is less than 50% in the current clock cycle.
Although the present invention has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the methods and technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present invention are within the scope of the technical matters of the present invention.

Claims (1)

1. A clock duty cycle adjustment circuit, characterized by: comprising a buffer B100, 2 coarse tuning circuits B110 and a fine tuning circuit B120;
wherein the buffer B100 receives the input clock signals clkp_in and clkn_in; buffering the input clock signal clkp_in to generate a buffered clock signal clkp_b; buffering the input clock signal clkn_in to generate a buffered clock signal clkn_b; transmitting the buffered clock signal clkp_b to 1 of the coarse tuning circuits B110; transmitting the buffered clock signal clkn_b to another coarse tuning circuit B110;
coarse tuning circuit B110: receiving the buffered clock signal clkp_b or the buffered clock signal clkn_b from the buffer B100; coarsely adjusting the duty ratio of the buffered clock signal clkp_b or the buffered clock signal clkn_b to generate a clock signal clkp_c and a clock signal clkn_c; and sends clock signal clkp_c and clock signal clkn_c to fine tuning circuit B120;
fine-tuning circuit B120: receiving the clock signal clkp_c and the clock signal clkn_c from the 2 coarse tuning circuits B110; fine-tuning the duty cycle of the clock signals clkp_c and clkn_c to generate output clock signals clkp_out and clkn_out;
the buffer B100 includes a differential comparator a; the positive input end of the differential comparator A receives a clock signal CLKP_IN; the negative input of the differential comparator A receives the clock signal CLKN_IN; buffering the clock signal clkp_in to generate a buffered clock signal clkp_b; outputting the buffered clock signal clkp_b to 1 of the coarse tuning circuits B110 through the positive output terminal; buffering the clock signal clkn_in to generate a buffered clock signal clkn_b; outputting the buffered clock signal clkn_b to the other coarse tuning circuit B110 through the negative output terminal;
the coarse adjustment circuit B110 includes a PMOS transistor P200, a PMOS transistor P201, a PMOS transistor P202, a PMOS transistor P203, an NMOS transistor N210, an NMOS transistor N211, an NMOS transistor N212, an NMOS transistor N213, a resistor R220, a resistor R221, a resistor R222, a resistor R223, a resistor R224, a resistor R225, a resistor R226, a resistor R227, a resistor R228, a resistor R229, a capacitor C230, a capacitor C231, a capacitor C232, an operational amplifier a240, and an operational amplifier a241;
the input port of the coarse tuning circuit B110 is CLK_B, and the output port is CLK_C; the grid electrode of the PMOS tube P200 is connected with the input port CLK_B and is simultaneously connected with the grid electrode of the NMOS tube N210; the source electrode of the PMOS tube P200 is connected with the drain electrode of the PMOS tube P201; the drain electrode of the PMOS tube P200 is connected with the output end CLK_C, and is simultaneously connected with the source electrode of the PMOS tube P203, the drain electrode of the NMOS tube N210, the source electrode of the NMOS tube N213, the first end of the capacitor C232, the inverting input end of the operational amplifier A240 and the inverting input end of the operational amplifier A241; the grid electrode of the PMOS tube P201 is connected with the drain electrode of the PMOS tube P202, the first end of the resistor R220 and the first end of the capacitor C230; the source electrode of the PMOS tube P201 is connected with a power supply; the grid electrode of the PMOS tube P202 is connected with the output end of the operational amplifier A240; the source electrode of the PMOS tube P202 is connected with a power supply; the grid electrode of the PMOS tube P203 is connected with the second end of the resistor R228 and the first end of the resistor R229; the drain electrode of the PMOS tube P203 is connected with the ground; the source electrode of the NMOS tube N210 is connected with the drain electrode of the NMOS tube N211; the grid electrode of the NMOS tube N211 is connected with the drain electrode of the NMOS tube N212, the second end of the resistor R221 and the second end of the capacitor C231; the source electrode of the NMOS tube N211 is connected with the ground; the grid electrode of the NMOS tube N212 is connected with the output end of the operational amplifier A241; the source electrode of the NMOS tube N212 is connected with the ground; the grid electrode of the NMOS tube N213 is connected with the second end of the resistor R226 and the first end of the resistor R227; the drain electrode of the NMOS tube N213 is connected with a power supply; a second end of the resistor R220 is connected with ground; a first end of the resistor R221 is connected with a power supply; the first end of the resistor R222 is connected with a power supply; the second end of the resistor R222 is connected with the first end of the resistor R223 and the non-inverting input end of the operational amplifier A240; the second end of the resistor R223 is connected with the first end of the resistor R224; the second end of the resistor R224 is connected with the first end of the resistor R225 and the non-inverting input end of the operational amplifier A241; the second end of the resistor R225 is connected with ground; the first end of the resistor R226 is connected with a power supply; the second end of the resistor R227 is connected with ground; a first end of the resistor R228 is connected with a power supply; a second terminal of resistor R229 is connected to ground; the second end of the capacitor C230 is connected with the ground; the first end of the capacitor C231 is connected with a power supply; the second end of the capacitor C232 is connected with the ground;
the fine-tuning circuit B120 includes a PMOS pipe P400, a PMOS pipe P401, a PMOS pipe P402, a PMOS pipe P403, a PMOS pipe P404, a PMOS pipe P405, a PMOS pipe P406, a PMOS pipe P407, a PMOS pipe P408, a PMOS pipe P409, an NMOS pipe N410, an NMOS pipe N411, an NMOS pipe N412, an NMOS pipe N413, an NMOS pipe N414, an NMOS pipe N415, an NMOS pipe N416, an NMOS pipe N417, an NMOS pipe N418, an NMOS pipe N419, a resistor R420, a capacitor C430, a capacitor C431, an inverter G440, an inverter G441, an inverter G442, an inverter G443, an inverter G444, and an inverter G445;
the input ports of the fine tuning circuit B120 are clkn_c and clkp_c; the output ports are CLKN_OUT and CLKP_OUT;
the grid electrode of the PMOS tube P400 is connected with the grid electrode of the PMOS tube P401, the drain electrode of the PMOS tube P402, the grid electrode of the PMOS tube P403 and the drain electrode of the NMOS tube N410; the source electrode of the PMOS tube P400 is connected with a power supply; the drain electrode of the PMOS tube P400 is connected with the drain electrode of the NMOS tube N412 and the input end of the NOT gate G440; the source electrode of the PMOS tube P401 is connected with a power supply; the grid electrode of the PMOS tube P402 is connected with the drain electrode of the PMOS tube P403, the grid electrode of the PMOS tube P404, the drain electrode of the PMOS tube P404, the grid electrode of the PMOS tube P405 and the drain electrode of the NMOS tube N411; the source electrode of the PMOS tube P402 is connected with a power supply; the source electrode of the PMOS tube P403 is connected with a power supply; the source electrode of the PMOS tube P404 is connected with a power supply; the source electrode of the PMOS tube P405 is connected with a power supply; the drain of the PMOS tube P405 is connected with the drain of the NMOS tube N415 and the input end of the NOT gate G441; the grid electrode of the PMOS tube P406 is connected with the grid electrode of the PMOS tube P409, the drain electrode of the PMOS tube P409 and the first end of the resistor R420; the source electrode of the PMOS tube P406 is connected with a power supply; the drain electrode of the PMOS tube P406 is connected with the source electrode of the PMOS tube P407 and the source electrode of the PMOS tube P408; the grid electrode of the PMOS tube P407 is connected with the grid electrode of the NMOS tube N416, the output end of the NOT gate G441, the output end of the NOT gate G442, the input end of the NOT gate G443 and the input end of the NOT gate G445; the drain electrode of the PMOS tube P407 is connected with the grid electrode of the NMOS tube N412, the grid electrode of the NMOS tube N413, the drain electrode of the NMOS tube N416, the grid electrode of the NMOS tube N418 and the first end of the capacitor C430; the grid of the PMOS tube P408 is connected with the grid of the NMOS tube N417, the output end of the NOT gate G440, the input end of the NOT gate G442, the output end of the NOT gate G443 and the input end of the NOT gate G444; the drain electrode of the PMOS tube P408 is connected with the grid electrode of the NMOS tube N414, the grid electrode of the NMOS tube N415, the drain electrode of the NMOS tube N417, the grid electrode of the NMOS tube N419 and the first end of the capacitor C431; the source electrode of the PMOS tube P409 is connected with a power supply; the gate of the NMOS transistor N410 is connected to the input port clkn_c; the source end of the NMOS tube N410 is connected with the source electrode of the NMOS tube N411, the drain electrode of the NMOS tube N413 and the drain electrode of the NMOS tube N414; the gate of the NMOS transistor N411 is connected with an input port CLKP_C; the source electrode of the NMOS tube N412 is connected with the ground; the source electrode of the NMOS tube N413 is connected with the ground; the source electrode of the NMOS tube N414 is connected with the ground; the source electrode of the NMOS tube N415 is connected with the ground; the source electrode of the NMOS tube N416 is connected with the drain electrode of the NMOS tube N418; the source electrode of the NMOS tube N417 is connected with the drain electrode of the NMOS tube N419; the source electrode of the NMOS tube N418 is connected with the ground; the source electrode of the NMOS tube N419 is connected with the ground; the second end of the resistor R420 is connected with ground; the second end of the capacitor C430 is connected to ground; a second end of the capacitor C431 is connected with the ground; the output end of the NOT gate G444 is connected with an output port CLKN_OUT; the output terminal of the not gate G445 is connected to the output port clkp_out.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103312299A (en) * 2012-03-05 2013-09-18 联发科技（新加坡）私人有限公司 Signal duty cycle detector and calibration system
CN105811923A (en) * 2016-02-29 2016-07-27 中国电子科技集团公司第五十八研究所 Clock duty ratio adjusting circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103312299A (en) * 2012-03-05 2013-09-18 联发科技（新加坡）私人有限公司 Signal duty cycle detector and calibration system
CN105811923A (en) * 2016-02-29 2016-07-27 中国电子科技集团公司第五十八研究所 Clock duty ratio adjusting circuit

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