CN217307654U - Precision-adjustable frequency doubling circuit structure - Google Patents
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- CN217307654U CN217307654U CN202221210400.1U CN202221210400U CN217307654U CN 217307654 U CN217307654 U CN 217307654U CN 202221210400 U CN202221210400 U CN 202221210400U CN 217307654 U CN217307654 U CN 217307654U
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Abstract
The utility model belongs to the technical field of the frequency doubling circuit design, specifically provide an adjustable two frequency doubling circuit structures of precision, include: the circuit comprises a programmable delay unit, a frequency multiplier, a pseudo inverter and a charge pump; firstly, performing coarse duty ratio adjustment on a clock source signal through a programmable delay unit, then performing signal frequency multiplication through a frequency multiplier to obtain a frequency multiplication clock signal, and finally inputting the frequency multiplication clock signal serving as an input signal to a pseudo inverter; the pseudo inverter is used for processing the input signal and outputting a clock signal with a duty ratio of 50%; the charge pump is connected with the output end of the pseudo-inverter and used for detecting the duty ratio of an input clock signal and adjusting the pseudo-inverter in a feedback mode to assist in adjusting the pseudo-inverter to output a clock signal with the duty ratio of 50%. The scheme has the characteristics of simple structure, wide frequency adjustable range, low power consumption and adjustable duty ratio, and can play an indispensable role in low power consumption, high precision and high speed application.
Description
Technical Field
The utility model relates to a frequency doubling circuit design technical field, more specifically relates to an adjustable two frequency doubling circuit structures of precision.
Background
The Frequency multiplier (Frequency Double) is a main structural form used for multiplying the Frequency of a clock signal at present, is a key component for providing a system clock in an analog system and a digital system, generates an output Frequency multiplication clock with high speed, high precision and wide calibration range based on a reference clock, and can stabilize the duty ratio of the Frequency multiplication clock at 50% by adding and holding a duty ratio regulation loop.
One of the conventional implementations of the frequency multiplier is a phase-locked loop method, which can multiply and amplify the input frequency and has a high integration level, but it is only applied to the frequency doubling of the input frequency, and obviously, the hardware consumption is too large, the IP area is too large, and the power consumption is too large. The other method of frequency multiplication is a harmonic selection method, and the method has the greatest advantage of obtaining phase noise of a frequency reference source, but the method has obvious technical difficulty that the frequency is not easy to be multiplied very much, and active devices such as inductors and the like need to be adopted, so that the method is not suitable for chip design of a traditional microprocessor.
Disclosure of Invention
The utility model discloses the technical problem to the realization mode price/performance ratio low of the traditional frequency multiplier that exists among the prior art.
The utility model provides an adjustable two frequency doubling circuit structures of precision, include: the circuit comprises a programmable delay unit, a frequency multiplier, a pseudo inverter and a charge pump;
firstly, a clock source signal is subjected to coarse duty ratio adjustment through a programmable delay unit, then signal frequency multiplication is carried out through a frequency multiplier to obtain a frequency multiplication clock signal, and finally the frequency multiplication clock signal is input to a pseudo inverter as an input signal;
the pseudo inverter is used for processing the input signal and outputting a clock signal with the duty ratio of 50%;
the charge pump is connected with the output end of the pseudo-inverter and used for detecting the duty ratio of an input clock signal and adjusting the pseudo-inverter in a feedback mode to assist in adjusting the pseudo-inverter to output a clock signal with the duty ratio of 50%.
Preferably, the frequency doubling circuit structure further includes a reverse shunt circuit, the reverse shunt circuit includes a phase inverter and a transmission gate, the clock source signal is divided into two paths, the two paths pass through the phase inverter and the transmission gate respectively, then the duty ratio rough adjustment is performed through the programmable delay unit respectively, and finally the frequency doubling is performed through the frequency multiplier to obtain a frequency doubling clock signal.
Preferably, the pseudo inverter includes a transistor MN1 and a transistor MP 1;
the frequency multiplication clock signals are respectively connected to the gates of the transistor MN1 and the transistor MP1, and the drain of the transistor MN1 is connected with the drain of the transistor MN1 to serve as an output end.
Preferably, the pseudo inverter further comprises a resistor R1 and a resistor R2;
the frequency multiplication clock signals are respectively accessed to the gates of the transistor MN1 and the transistor MP1, the drain of the transistor MN1 is connected with the resistor R2, the source of the transistor MN1 is grounded, the source of the transistor MP1 is connected with the power supply, the drain of the transistor MN1 is connected with the resistor R1, and the resistor R1 is connected with the resistor R2 in parallel and then is respectively connected with the gates of the transistor MN2 and the transistor MP 2.
Preferably, the charge pump employs cascode type current mirrors to mirror the current.
Preferably, the charge pump comprises a transistor MN2 and a transistor MP 2;
the gates of the transistor MN2 and the transistor MP2 are connected to access the output end of the pseudo-inverter, the drain of the transistor MN2 is connected with the drain of the transistor MP2 and then output, the source of the transistor MN2 is grounded, and the source of the transistor MP2 is connected with the power supply.
Preferably, the charge pump further comprises a resistor R3 and a resistor R4;
the drain electrode of the transistor MN2 is connected with the resistor R4, the source electrode of the transistor MN2 is grounded, the source electrode of the transistor MP2 is connected with the power supply, the drain electrode of the transistor MP2 is connected with the resistor R3, and the resistor R3 is connected with the resistor R4 in parallel and then output;
the resistor R1 is connected with the resistor R2 in parallel and then grounded through the capacitor C1, and the resistor R3 is connected with the resistor R4 in parallel and then grounded through the capacitor C2.
Preferably, the frequency doubling circuit structure further comprises a feedback circuit, wherein the feedback circuit comprises a transistor MN0 and a transistor MP0, the source of the transistor MN0 is grounded, the drain of the transistor MN0 is connected with the source of the transistor MN1, the drain of the transistor MP0 is connected with the source of the transistor MP1, and the source of the transistor MP0 is connected with the power supply;
the drain of the transistor MN2 is connected to the drain of the transistor MP2 to form a feedback control voltage signal VC, which is coupled to the gate of the transistor MN0 and the gate of the transistor MP 0.
Preferably, the frequency multiplier is configured to first invert the clock signal that has been coarsely adjusted by the duty ratio and has a delay, and then perform nor operation on the original clock, so as to obtain a delay clock with a frequency twice that of the clock source signal.
Preferably, the duty cycle of the frequency-multiplied clock signal is in the range of 30% to 70%.
Has the beneficial effects that: the utility model provides a pair of adjustable two frequency doubling circuit structures of precision, include: the circuit comprises a programmable delay unit, a frequency multiplier, a pseudo inverter and a charge pump; firstly, performing coarse duty ratio adjustment on a clock source signal through a programmable delay unit, then performing signal frequency multiplication through a frequency multiplier to obtain a frequency multiplication clock signal, and finally inputting the frequency multiplication clock signal serving as an input signal to a pseudo inverter; the pseudo inverter is used for processing the input signal and outputting a clock signal with a duty ratio of 50%; the charge pump is connected with the output end of the pseudo-inverter and used for detecting the duty ratio of an input clock signal and adjusting the pseudo-inverter in a feedback mode to assist in adjusting the pseudo-inverter to output a clock signal with the duty ratio of 50%. The circuit of the first part has no static power consumption, and the circuit of the second part only needs static current for biasing the current mirror of the charge pump, so the total power consumption is lower; the whole circuit structure has smaller scale, so the total area is smaller and the circuit structure is simple; the duty ratio of the output signal is adjusted through digital-analog mixing, so that the output duty ratio can be stabilized at about 50% to meet the application requirement; the processed clock signals are all from crystal oscillators with low phase noise and good stability, so that the frequency of the final output frequency doubling clock is still stable and the phase noise is low.
The scheme adopts the programmable delay unit and the digital logic unit, effectively performs frequency multiplication operation on the input clock signal, and simultaneously performs coarse adjustment on the duty ratio of the frequency multiplication clock signal, thereby quickening the operation time of the analog system to a greater extent and reducing the extra hardware overhead caused by overlarge adjustment range of the duty ratio of the analog system. The frequency-adjustable frequency divider has the characteristics of simple structure, wide adjustable range of frequency, low power consumption and adjustable duty ratio, and can play an indispensable role in low power consumption, high precision and high speed application.
Drawings
Fig. 1 is a schematic diagram of a structural design of a frequency doubling circuit with adjustable precision according to the present invention;
fig. 2 is a functional schematic diagram of the programmable delay unit provided by the present invention;
fig. 3 is a schematic circuit design diagram of the programmable delay unit provided by the present invention;
fig. 4 is a schematic diagram of a digital circuit portion of a frequency multiplier provided by the present invention;
fig. 5 is a structural diagram of a duty ratio adjusting circuit provided by the present invention;
fig. 6 is a schematic diagram of a charge pump in the duty ratio adjusting circuit provided by the present invention;
fig. 7 is a waveform diagram of the programmable delay unit provided by the present invention;
fig. 8 is a waveform diagram of a digital circuit for input clock frequency doubling according to the present invention;
fig. 9 is a waveform diagram illustrating the operation principle of the charge pump circuit provided by the present invention;
fig. 10 is a waveform diagram illustrating the operation principle of the charge pump circuit according to the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples. The following examples are intended to illustrate the invention, but are not intended to limit the scope of the invention.
As shown in fig. 1 to fig. 10, an embodiment of the present invention provides an adjustable-precision frequency doubling circuit structure, including: the circuit comprises a programmable delay unit, a frequency multiplier, a pseudo inverter and a charge pump; firstly, performing coarse duty ratio adjustment on a clock source signal through a programmable delay unit, then performing signal frequency multiplication through a frequency multiplier to obtain a frequency multiplication clock signal, and finally inputting the frequency multiplication clock signal serving as an input signal to a pseudo inverter; the pseudo inverter is used for processing the input signal and outputting a clock signal with a duty ratio of 50%; the charge pump is connected with the output end of the pseudo-inverter and used for detecting the duty ratio of an input clock signal and adjusting the pseudo-inverter in a feedback mode to assist in adjusting the pseudo-inverter to output a clock signal with the duty ratio of 50%. The circuit of the first part has no static power consumption, and only the current mirror bias of the charge pump in the second part needs static current, so the total power consumption is lower; the whole circuit structure has smaller scale, so the total area is smaller and the circuit structure is simple; the duty ratio of the output signal is adjusted through digital-analog mixing, so that the output duty ratio can be stabilized at about 50% to meet the application requirement; the processed clock signals are all from crystal oscillators with low phase noise and good stability, so that the frequency of the final output frequency doubling clock is still stable and the phase noise is low.
Specifically, a clock signal which is subjected to frequency multiplication and has a duty ratio ranging from 30% to 70% is obtained by adopting a digital programmable delay unit and a digital logic circuit (frequency multiplier); sampling the clock with the adjusted duty ratio by using a charge pump cascade filter, and converting the clock into control voltage VC; and precisely adjusting the frequency multiplication clock generated in the last stage by using the pseudo-inverter string and the control voltage VC. Different from the traditional frequency doubling circuit, the circuit is easy to realize, low in power consumption, quick in response time, capable of stably working under the conditions of different temperatures, voltages and manufacturing processes, and high in compatibility and practicability.
The negative feedback system formed by the analog circuit is adopted to further adjust the duty ratio of the output clock, and the duty ratio of the output frequency multiplication clock can be quickly adjusted on the premise of ensuring lower power consumption, so that the application requirements are met.
The scheme adopts the programmable delay unit and the digital logic unit, effectively performs frequency multiplication operation on the input clock signal, and simultaneously performs coarse adjustment on the duty ratio of the frequency multiplication clock signal, thereby quickening the operation time of the analog system to a greater extent and reducing the extra hardware overhead caused by overlarge adjustment range of the duty ratio of the analog system. The frequency-adjustable power supply has the characteristics of simple structure, wide frequency adjustable range, low power consumption and adjustable duty ratio, and can play an indispensable role in low power consumption, high precision and high speed application.
In a preferred embodiment, as shown in fig. 1, the frequency doubling circuit structure further includes a reverse shunt circuit, where the reverse shunt circuit includes a phase inverter and a transmission gate, and divides the clock source signal into two paths, which pass through the phase inverter and the transmission gate respectively, and then perform coarse duty ratio adjustment through the programmable delay unit, and finally perform frequency doubling through the frequency multiplier to obtain a frequency-doubled clock signal.
In a specific implementation scenario, the Frequency multiplier structure adopted by the present invention can be functionally divided into two parts (see fig. 1), wherein the first part of the circuit includes a Frequency multiplication logic circuit And a Duty cycle coarse adjustment circuit (Duty-cycle Adjust), And the second part of the circuit includes a Duty cycle fine adjustment circuit (Duty-cycle Adjust).
The first part of the circuit is mainly responsible for leading an input clock signal to pass through the programmable delay unit and the frequency multiplier in sequence. After the duty ratio of the clock signal is roughly adjusted by the programmable delay unit, the clock signal is frequency-multiplied by the frequency multiplier to obtain a corresponding frequency-multiplied clock signal, and the duty ratio of the frequency-multiplied clock signal is approximately in the range of 30-70%. The frequency multiplication clock signal after the coarse adjustment of the duty ratio can reduce the difficulty of subsequent circuit design.
The second part of the circuit is mainly responsible for further fine-adjusting the duty ratio of the frequency-doubled clock signal after coarse adjustment and frequency doubling of the duty ratio, and finally outputting the clock signal after fine adjustment after driving, thereby completing the whole process. The key processes in these two sections will be explained in detail below.
The first part of fig. 1 can be functionally divided into two circuits, one of which is a programmable delay generating circuit part, i.e. a programmable delay unit, see fig. 2; the other is a digital circuit part with double frequency of the input clock, i.e. a frequency multiplier, see fig. 4. This section will be described in detail below.
In fig. 2, the input port clkin is used to input the clock source signal, and corresponding to points a and B in fig. 1 (the frequencies of points a and B are equal and the directions are opposite), in order to ensure that the frequency drift of the input clock source signal is smaller, the clock jitter is smaller, and the phase noise is smaller, a crystal oscillator is often required to provide a stable frequency. To ensure that the phases of the clock signals at points a and B are close, a transmission gate is inserted between the input and point B in fig. 1 to simulate the delay time of the inverter INV 1. Input control signal DP < X: 0> is written in by a register of a digital part or a storage unit such as FLASH and the like, and is used for determining the access number of the delay units so as to change the final delay time. The output port clkout is the output port of the programmable delay generation circuit part, corresponding to points C and D in fig. 1.
Assuming that the delay time of each delay cell is fixed to "2 ns" the input control signal DP < X: 0> -0000 … 0010, then only DP <1> -1, that is, the switch corresponding to the control bit PD <1> is turned on, and the switches corresponding to the other control bits are turned off, then the number of the delay units connected is 2, and if the delay introduced by the switches and the buffer is neglected, the delay from the input clock signal clkin to the output clock signal clkout is 4 ns. From this, it can be seen that the arrangement control signal DP < X: 0>, the required delay time can be obtained.
In fig. 7, the control signals DP <0>, DP <1> and DP <2> respectively correspond to three different delay times, and if the unit delay time is dt, the delay times corresponding to DP <0> to DP <2> are: dt, 2dt and 3 dt. In an actual circuit, the delay time can be set to be smaller, and the control bit can be set to be finer and used for trimming circuits in different batches of chips.
Under common process progress, the delay time of phase inverter is about 50ps, in order to improve the delay time, the utility model discloses a RC phase inverter realizes the time delay as pseudo-phase inverter (see fig. 3). IN fig. 3, the resistors R1, R2, R3 and R4 and the capacitors C1 and C2 respectively form an RC delay unit, and assuming that the input clock signal CLK _ IN is converted from high level to low level, the transistor MN1 is turned off at this time, the transistor MP1 is turned on, the capacitor C1 and the parasitic capacitor exist IN the node a, the potential cannot suddenly change, so the node a still keeps low potential, and the transistor MP1 should operate IN a saturation region at this time, the maximum value of the current flowing from the power supply through the transistor MP1 and the resistor R1 to the node a at this time is equal to
Due to the introduction of the resistor R1, the charging current is reduced. As the potential of the node a gradually increases, the VGS voltage of the transistor MN2 gradually increases, and the VGS voltage of the transistor MP2 gradually decreases, the output terminal CLK _ OUT starts to discharge when the pull-down current capability of the transistor MN2 is greater than the pull-up current capability of the transistor MP 2. Compared with the phase inverter without increasing the RC, the utility model discloses the delay time of the phase inverter that adopts is longer, and the influence of delay time along with technology is littleer.
Specifically, the dummy inverter includes a transistor MN1 and a transistor MP 1; the frequency multiplication clock signals are respectively connected to the gates of the transistor MN1 and the transistor MP1, and the drain of the transistor MN1 is connected with the drain of the transistor MN1 to serve as an output end.
More preferably, the pseudo inverter further comprises a resistor R1 and a resistor R2;
the frequency multiplication clock signals are respectively accessed to the gates of the transistor MN1 and the transistor MP1, the drain of the transistor MN1 is connected with the resistor R2, the source of the transistor MN1 is grounded, the source of the transistor MP1 is connected with the power supply, the drain of the transistor MN1 is connected with the resistor R1, and the resistor R1 is connected with the resistor R2 in parallel and then is respectively connected with the gates of the transistor MN2 and the transistor MP 2.
The output clock signal of the programmable delay unit is input to a second stage circuit for processing, the second stage circuit comprises a digital circuit of a frequency multiplier, and a signal waveform diagram of a key node of the digital circuit is shown in fig. 8. As will be explained with reference to fig. 4 and 8, the digital circuit inverts the clock signal that has been delayed by the previous stage circuit, and then performs the nor operation on the original clock to extract the delayed clock, where two points a and b in fig. 4 are the final extracted delayed clock, and the waveform diagram thereof can refer to fig. 8. Because a and b have a phase difference of 180 °, a and b are subjected to phase or, that is, a delayed clock having a frequency twice the frequency of the clock source signal is obtained, and the clock is twice the frequency of the input clock (i.e., the clock source signal). Through the above analysis, it can be known that in the first part, the duty ratio of the frequency-multiplied clock can be determined by the programmable delay generation circuit, and the clock signal with the coarse duty ratio can be realized.
The duty ratio of the frequency-multiplied clock signal is further finely adjusted, and a duty ratio adjusting circuit is abstracted, as shown in fig. 5. Fig. 5 is a pseudo inverter with feedback regulation. The Pseudo-inverter (Pseudo Inv) in fig. 5 is used to adjust the duty cycle, and the Charge Pump is used to detect the duty cycle of the input clock signal, the Charge Pump (Charge Pump) in the present invention, see fig. 6. In order to ensure that the charge current and the discharge current of the charge pump can be equal as much as possible, the designed charge pump selects a cascode current mirror to be used for mirroring the current, so that the current precision is increased, but the power supply voltage is limited, and a part of transistors of the current mirror in the charge pump can work in a linear region due to the excessively low power supply voltage, so that the performance is greatly reduced. The cascode current mirror is a prior art, and the circuit structure of the cascode current mirror is shown in fig. 6, which can be directly reproduced by those skilled in the art.
Specifically, the charge pump includes a transistor MN2 and a transistor MP 2; the gates of the transistor MN2 and the transistor MP2 are connected to access the output end of the pseudo-inverter, the drain of the transistor MN2 is connected with the drain of the transistor MP2 and then output, the source of the transistor MN2 is grounded, and the source of the transistor MP2 is connected with the power supply.
More preferably, the charge pump further comprises a resistor R3 and a resistor R4;
the drain electrode of the transistor MN2 is connected with the resistor R4, the source electrode of the transistor MN2 is grounded, the source electrode of the transistor MP2 is connected with the power supply, the drain electrode of the transistor MP2 is connected with the resistor R3, and the resistor R3 is connected with the resistor R4 in parallel and then output; the resistor R1 is connected with the resistor R2 in parallel and then grounded through the capacitor C1, and the resistor R3 is connected with the resistor R4 in parallel and then grounded through the capacitor C2.
In FIG. 5, the port clk of the Pseudo-inverter Pseudo Inv is the input of the structure for receiving the multiplied clock signal generated by the previous part; the port fclk is an output port of the whole system and is used for outputting a clock signal which is multiplied by frequency and has a duty ratio of 50%.
Preferably, the frequency doubling circuit structure further comprises a feedback circuit, wherein the feedback circuit comprises a transistor MN0 and a transistor MP0, the source of the transistor MN0 is grounded, the drain of the transistor MN0 is connected with the source of the transistor MN1, the drain of the transistor MP0 is connected with the source of the transistor MP1, and the source of the transistor MP0 is connected with the power supply; the drain of the transistor MN2 is connected to the drain of the transistor MP2 to form a feedback control voltage signal VC, which is coupled to the gate of the transistor MN0 and the gate of the transistor MP 0.
Among them, there are three ways of inputting a frequency-multiplied clock signal to the pseudo-inverter, which are simplified waveform diagrams, see fig. 9 and 10.
In fig. 9, in the first case, if the duty ratio of the input frequency-doubled clock signal is lower than the threshold value, so that the P-transistor on-time of the charge pump is longer than the N-transistor on-time, the feedback control voltage VC will continuously decrease, and at the same time, the P-transistor current of the pseudo-inverter in fig. 10 will be larger than the N-transistor current, which will make the duty ratio of the output clock signal of the pseudo-inverter gradually increase and finally approach to 50%; in the second case, if the duty ratio of the input frequency-multiplied clock signal is equal to 50%, the control voltage VC output by the charge pump is VDD/2, and the pseudo inverter is equivalent to a conventional inverter; in the third situation, if the duty ratio of the input frequency-doubled clock signal is high, which causes the conduction time of the P-transistor of the charge pump to be less than the conduction time of the N-transistor, the control voltage VC will continuously rise, and finally the duty ratio will gradually decrease to 50% through the pseudo-inverter.
In the utility model, the circuit of the first part has no static power consumption, and the second part only needs static current for the bias of the current mirror of the charge pump, so the total power consumption is lower; the whole circuit structure has smaller scale, so the total area is smaller and the circuit structure is simple; the duty ratio of the output signal is adjusted through digital-analog mixing, so that the output duty ratio can be stabilized at about 50%, and the application requirement is met; the processed clock signals are all from crystal oscillators with low phase noise and good stability, so that the frequency of the final output frequency doubling clock is still stable and the phase noise is low.
It should be noted that, in the foregoing embodiments, the description of each embodiment has an emphasis, and reference may be made to the related description of other embodiments for a part that is not described in detail in a certain embodiment.
While the preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the appended claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, then the present invention is also intended to include such modifications and variations.
Claims (10)
1. An adjustable-precision frequency doubling circuit structure, comprising: the circuit comprises a programmable delay unit, a frequency multiplier, a pseudo inverter and a charge pump;
firstly, performing coarse duty ratio adjustment on a clock source signal through a programmable delay unit, then performing signal frequency multiplication through a frequency multiplier to obtain a frequency multiplication clock signal, and finally inputting the frequency multiplication clock signal serving as an input signal to a pseudo inverter;
the pseudo inverter is used for processing the input signal and outputting a clock signal with a duty ratio of 50%;
the charge pump is connected with the output end of the pseudo-inverter and used for detecting the duty ratio of an input clock signal and adjusting the pseudo-inverter in a feedback mode to assist in adjusting the pseudo-inverter to output a clock signal with the duty ratio of 50%.
2. The tunable-precision frequency-doubling circuit structure of claim 1, wherein the frequency-doubling circuit structure further comprises a reverse shunt circuit, the reverse shunt circuit comprises a phase inverter and a transmission gate, a clock source signal is divided into two paths and respectively passes through the phase inverter and the transmission gate, then duty ratio rough adjustment is respectively performed through a programmable delay unit, and finally signal frequency doubling is performed through the frequency multiplier to obtain a frequency-doubled clock signal.
3. The tunable precision frequency doubling circuit structure according to claim 1, wherein the pseudo-inverter comprises a transistor MN1 and a transistor MP 1;
the frequency multiplication clock signals are respectively connected to the gates of the transistor MN1 and the transistor MP1, and the drain of the transistor MN1 is connected with the drain of the transistor MN1 to serve as an output end.
4. The tunable precision frequency doubling circuit structure according to claim 3, wherein the pseudo-inverter further comprises a resistor R1 and a resistor R2;
the frequency multiplication clock signals are respectively accessed to the gates of the transistor MN1 and the transistor MP1, the drain of the transistor MN1 is connected with the resistor R2, the source of the transistor MN1 is grounded, the source of the transistor MP1 is connected with the power supply, the drain of the transistor MN1 is connected with the resistor R1, and the resistor R1 is connected with the resistor R2 in parallel and then is respectively connected with the gates of the transistor MN2 and the transistor MP 2.
5. The tunable precision frequency doubling circuit structure according to claim 3, wherein the charge pump employs a cascode current mirror to mirror the current.
6. The adjustable precision frequency doubling circuit structure according to claim 5, wherein the charge pump comprises a transistor MN2 and a transistor MP 2;
the gates of the transistor MN2 and the transistor MP2 are connected to access the output end of the pseudo-inverter, the drain of the transistor MN2 is connected with the drain of the transistor MP2 and then output, the source of the transistor MN2 is grounded, and the source of the transistor MP2 is connected with the power supply.
7. The tunable precision frequency doubling circuit structure according to claim 6, wherein the charge pump further comprises a resistor R3 and a resistor R4;
the drain electrode of the transistor MN2 is connected with the resistor R4, the source electrode of the transistor MN2 is grounded, the source electrode of the transistor MP2 is connected with the power supply, the drain electrode of the transistor MP2 is connected with the resistor R3, and the resistor R3 is connected with the resistor R4 in parallel and then output;
the resistor R1 is connected with the resistor R2 in parallel and then grounded through the capacitor C1, and the resistor R3 is connected with the resistor R4 in parallel and then grounded through the capacitor C2.
8. The tunable precision frequency doubling circuit structure of claim 6, further comprising a feedback circuit, wherein the feedback circuit comprises a transistor MN0 and a transistor MP0, a source of the transistor MN0 is grounded, a drain of the transistor MN0 is connected to a source of the transistor MN1, a drain of the transistor MP0 is connected to a source of the transistor MP1, and a source of the transistor MP0 is connected to a power supply;
the drain of the transistor MN2 is connected to the drain of the transistor MP2 to form a feedback control voltage signal VC, which is coupled to the gate of the transistor MN0 and the gate of the transistor MP 0.
9. The adjustable-precision frequency doubling circuit structure of claim 1, wherein the frequency multiplier is configured to invert the clock signal that is delayed after the coarse adjustment of the duty cycle, perform nor operation on the original clock, and finally obtain a delayed clock with a frequency twice that of the clock source signal.
10. The adjustable-precision frequency doubling circuit structure according to claim 1, wherein the duty cycle of the frequency doubled clock signal is in the range of 30% to 70%.
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