CN110049263B - High-speed high-precision phase-locked loop circuit for super-large area array CMOS image sensor - Google Patents

High-speed high-precision phase-locked loop circuit for super-large area array CMOS image sensor Download PDF

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CN110049263B
CN110049263B CN201910469549.8A CN201910469549A CN110049263B CN 110049263 B CN110049263 B CN 110049263B CN 201910469549 A CN201910469549 A CN 201910469549A CN 110049263 B CN110049263 B CN 110049263B
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transistor
terminal
stage
oscillation unit
drain
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CN110049263A (en
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曹天骄
刘晓轩
袁昕
李婷
李海松
吴龙胜
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Xian Microelectronics Technology Institute
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/30Transforming light or analogous information into electric information
    • H04N5/335Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
    • H04N5/357Noise processing, e.g. detecting, correcting, reducing or removing noise
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/30Transforming light or analogous information into electric information
    • H04N5/335Transforming light or analogous information into electric information using solid-state image sensors [SSIS]
    • H04N5/369SSIS architecture; Circuitry associated therewith
    • H04N5/374Addressed sensors, e.g. MOS or CMOS sensors

Abstract

The invention discloses a high-speed high-precision phase-locked loop circuit for an oversized area array CMOS image sensor, and belongs to the technical field of image sensors. In the phase-locked loop circuit, three-stage cross-coupling complementary oscillation units are sequentially reversely cascaded; the grid end of NM5 is connected with PD signal, the drain end of NM5, the grid end of NM2, the grid end of NM3 and the grid end of NM4 are all connected with input voltage end, the source end of NM2, the source end of NM3 and the source end of NM4 are all connected with NM5 source end, the drain end of NM2 outputs Ictrl1,Ictrl1Inputting the current as a frequency regulation current to a first stage; drain output Ictrl of NM32,Ictrl2Inputting the current as a frequency adjusting current into the second stage; drain output Ictrl of NM43,Ictrl3The current is input to the third stage as a frequency adjustment current. The phase-locked loop circuit improves the frequency adjusting range of a voltage-controlled oscillator in the phase-locked loop and can adjust the central frequency of an oscillator of the phase-locked loop.

Description

High-speed high-precision phase-locked loop circuit for super-large area array CMOS image sensor
Technical Field
The invention belongs to the technical field of CMOS image sensors, and particularly relates to a high-speed high-precision phase-locked loop circuit for an ultra-large area array CMOS image sensor.
Background
In a large-scale CMOS image sensor, a high-speed reading circuit is mainly used for carrying out functional amplification, noise reduction and driving processing on weak current signals output by a planar array under the guidance of time sequence control, and simultaneously realizing processing such as black level correction, column FPN correction and the like on performance, thereby realizing high-quality output of image signals.
The phase-locked loop circuit is used as a high-speed clock generator, and the main function of the phase-locked loop circuit in the CMOS image sensor is to provide a clock meeting the working requirements of each module. With the increase of pixels and frame frequency of the CMOS image sensor, the modules in the readout circuit also have a higher frequency clock requirement, which requires a phase locked loop with higher frequency, larger locking range and higher stability. The voltage-controlled oscillator is used as the most important part of a phase-locked loop circuit, is responsible for clock generation and frequency real-time adjustment, and plays a decisive role in the locking range, the quality and the reliability of an output clock of the phase-locked loop.
The output noise of the clock generator circuit is mostly from the noise of the voltage-controlled oscillator, and the main sources of the noise of the voltage-controlled oscillator are thermal noise and power and ground induced noise, and the latter is the main source of the noise of the voltage-controlled oscillator. The ability of the voltage controlled oscillator to suppress power supply ground noise is also an important part of the design.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a high-speed high-precision phase-locked loop circuit for a super-large area array CMOS image sensor.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
a high-speed high-precision phase-locked loop circuit for an ultra-large area array CMOS image sensor comprises a reset tube NM5, a transistor NM2, a transistor NM3, a transistor NM4, a first-stage cross-coupled complementary oscillation unit, a second-stage cross-coupled complementary oscillation unit and a third-stage cross-coupled complementary oscillation unit;
the first-stage cross-coupling complementary oscillation unit, the second-stage cross-coupling complementary oscillation unit and the third-stage cross-coupling complementary oscillation unit are sequentially in reverse cascade connection;
the gate terminal of the reset tube NM5 is connected with a PowerDown signal, the drain terminal of the reset tube NM5, the gate terminal of the transistor NM2, the gate terminal of the transistor NM3 and the gate terminal of the transistor NM4 are all connected with an input voltage terminal, the source terminal of the transistor NM2, the source terminal of the transistor NM3, the source terminal of the transistor NM4 and the source terminal of the reset tube NM5 are all grounded, and the drain terminal of the transistor NM2 outputs Iictrl1,Ictrl1Inputting the current as frequency regulation current into a first-stage cross-coupling complementary oscillation unit;
drain output Ictrl of transistor NM32,Ictrl2Inputting the current as frequency adjusting current into a second-stage cross-coupled complementary oscillation unit;
drain output Ictrl of transistor NM43,Ictrl3And the frequency adjusting current is input into the third-stage cross-coupling complementary oscillation unit.
Further, the first-stage cross-coupled complementary oscillation unit includes a transistor PM0, a transistor PM2, a transistor PM3, a transistor PM4, a transistor PM5, a transistor NM0, and a transistor NM 1;
the drain terminal and the gate terminal of the transistor PM0 are in short circuit, and the drain terminal and the gate terminal are both input into Ictrl1The gate terminal of the transistor PM0 is also connected with the gate terminal of the transistor PM2 and the gate terminal of the transistor PM3, the source terminal of the transistor PM0, the source terminal of the transistor PM2, the source terminal of the transistor PM3, the source terminal of the transistor PM4 and the source terminal of the transistor PM5 are all connected with power supply terminals, the drain terminal of the transistor PM3 is connected with the drain terminal of the transistor PM5 and then connected with an output terminal, the gate terminal of the transistor PM4 is connected with the drain terminal of the transistor NM1 and then connected with an output terminal, and the output terminal is used for outputting an output signal VOUT1 +;
the drain terminal of the transistor PM 2is connected with the drain terminal of the transistor PM4 and then connected with the output terminal, the gate terminal of the transistor PM5 is connected with the drain terminal of the transistor NM0 and then connected with the output terminal, and the output terminal is used for outputting an output signal VOUT 1-;
the source terminal of the transistor NM0 and the source terminal of the transistor NM1 are both grounded.
Furthermore, the circuit structures of the second-stage cross-coupling complementary oscillation unit and the third-stage cross-coupling complementary oscillation unit are the same as the circuit structure of the first-stage cross-coupling complementary oscillation unit;
output signals VOUT 1-VOUT 1+ of the first-stage cross-coupled complementary oscillation unit are respectively used as input signals VIN2+ and VIN 2-of the second-stage cross-coupled complementary oscillation unit;
the output signals VOUT 2-VOUT 2+ of the second-stage cross-coupled complementary oscillation unit are respectively used as the input signals VIN3+ and VIN 3-of the third-stage cross-coupled complementary oscillation unit.
Furthermore, the output ends of the first-stage cross-coupling complementary oscillation unit, the second-stage cross-coupling complementary oscillation unit and the third-stage cross-coupling complementary oscillation unit are respectively provided with a configurable central frequency adjusting module for adjusting the load capacitance of the oscillation unit.
Further, the configurable center frequency adjusting module comprises a switch M0, a switch M1, a switch M2, a switch M3, a PMOS capacitor M4, a PMOS capacitor M5, an NMOS capacitor M6 and an NMOS capacitor M7, wherein the switch M0 and the switch M3 are both NMOS, and the switch M1 and the switch M2 are both PMOS;
the source end of the switch M0 and the source end of the switch M1 are connected with the output end of the cross-coupling complementary oscillation unit, the gate end of the switch M0 and the gate end of the switch M1 are connected with configuration signals, the drain end of the switch M0 and the drain end of the switch M1 are connected with the gate end of the PMOS capacitor M4, the gate end of the NMOS capacitor M6, the source end of the switch M2 and the source end of the switch M3 respectively, the gate end of the switch M2 and the gate end of the switch M3 are connected with configuration signals, the drain end of the switch M2 and the drain end of the switch M3 are connected with the gate end of the PMOS capacitor M5 and the gate end of the NMOS capacitor M7 respectively, the source end and the drain end of the PMOS capacitor M4 are connected with power supply ends, the source end and the drain end of the PMOS capacitor M source end 5 are connected with power supply ends, the drain end and the drain end of the NMOS capacitor M6 are grounded, and the drain;
when the configuration signal TR <1:0> is 00 or 10, the switches M0, M1, M2 and M3 are all in an off state;
when the configuration signal TR <1:0> is 01, the switches M0 and M1 are in an open state, and the switches M2 and M3 are in a closed state;
when the configuration signal TR <1:0> is 11, the switches M0, M1, M2 and M3 are all in the on state.
Compared with the prior art, the invention has the following beneficial effects:
a high-speed high-precision phase-locked loop circuit for an ultra-large area array CMOS image sensor realizes real-time adjustment of the oscillation center frequency of an output clock through a configurable signal on the basis of meeting the frame frequency and time sequence requirements of the CMOS image sensor, and improves the frequency adjustment range of a voltage-controlled oscillator in the phase-locked loop; in addition, aiming at different input clock frequencies of the CMOS image sensor, the bandwidth of the phase-locked loop is adjusted through a configurable signal so as to meet the stability requirements of the clock generator under different working conditions; the phase-locked loop has the advantages of high-frequency output, flexibility and adjustability, large locking range, low noise, high reliability and the like, can be widely applied to high-speed low-noise reading circuits, and meets the requirements of various on-chip clock generators.
Drawings
FIG. 1 is a block diagram of a first type of voltage controlled oscillation unit;
FIG. 2is a diagram of a second type of VCO unit;
FIG. 3 is a circuit diagram of a high-speed high-precision phase-locked loop for a super-large area array CMOS image sensor according to the present invention;
FIG. 4 is a circuit configuration diagram of a differential cross-coupled complementary oscillation unit in the present invention;
fig. 5 is a circuit structure diagram of a configurable center frequency adjustment module in the present invention.
Wherein PMx denotes an xth PMOS transistor;
NMx denotes an xth NMOS transistor.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The invention is described in further detail below with reference to the accompanying drawings:
referring to fig. 1, fig. 1 is a structural diagram of a first type of voltage controlled oscillation unit; fig. 1 is a structural diagram of a one-stage cross-coupled complementary oscillation unit of a conventional voltage-controlled oscillator, wherein controlled transistors M3 and M4 work in a deep linear region, and the output swing of the circuit is greatly changed in the whole frequency adjustment range. When the circuit is completely switched, the differential output swing of each stage reaches 2IssRon3,4, the output frequency range is small, and the performance requirement on a phase-locked loop in a CMOS image sensor is not met.
Referring to fig. 2, fig. 2is a structural diagram of a second type voltage-controlled oscillation unit; FIG. 2is a structural diagram of another one-stage cross-coupled complementary oscillation unit of a voltage-controlled oscillator, compared with the structural diagram of a traditional oscillation unit, the circuit shown in FIG. 2 changes the magnitude of tail current Iss by controlling voltage, controls the on-resistances of M3 and M4 to track the on-resistance of M5, and changes oscillation frequency by adjusting I1 and Iss simultaneously. If M3, M4, M5 are all the same size, I1 and Iss are equal size current mirrors, when M1 and M2 control the tail current to switch from one side to the other side, Vo + and Vo-change from VDD to VDD-Vref, so that the output amplitude change is reduced. However, the bandwidth of the operational amplifier a1 in fig. 2 affects the stability of this type of phase-locked loop, and the power supply noise suppression capability of this type of phase-locked loop is poor.
Referring to fig. 3, fig. 3 is a circuit structure diagram of a high-speed high-precision phase-locked loop for a super-large area array CMOS image sensor according to the present invention; the input voltage Vctrl is added to the grid ends of the transistor NM2, the transistor NM3 and the transistor NM4 to generate three mirror image currents Ictrl positively correlated with Vctrl1,2,3Namely, the frequency regulating current of each stage of the cross-coupled complementary oscillation unit, the process is as follows: and the signal turning speed of the oscillation unit is adjusted to achieve the purpose of adjusting the output frequency.
Referring to fig. 4, fig. 4 is a circuit configuration diagram of a differential cross-coupled complementary oscillation unit in the present invention; in the first stage of the cross-coupled complementary oscillation unit, when VIN1+ changes from low to high and VIN 1-changes from high to low, VOUT1+ changes from high to low and VOUT 1-changes from low to high; when VIN1+ changes from low to high and VIN 1-changes from high to low, VOUT1+ changes from high to highLow, VOUT 1-goes from low to high; if Ictrl1 is increased, Ictrl1 is mirrored to transistor PM2 and transistor PM3 through transistor PM0, which results in increased leakage current flowing through transistor PM2 and transistor PM3, so that VOUT1+ or VOUT 1-pull-up current is increased from low to high, and the turnover speed is faster; if Isctrl1Reduction, Ictrl1The mirror image of the transistor PM0 to the transistor PM2 and the transistor PM3 causes the leakage current flowing through the transistor PM2 and the transistor PM3 to be reduced, so that the pull-up current of VOUT1+ or VOUT 1-is reduced from low to high, and the turnover speed is slower. The speed of the signal turnover of the oscillation unit determines the output clock frequency of the voltage-controlled oscillator which is the clock generation module.
The three cross-coupled complementary oscillation units have the same circuit structure and are in reverse cascade relation, and in the second-stage oscillation unit, input ends VIN2+ and VIN 2-are VOUT1+ and VOUT1+ of the first-stage oscillation unit respectively; when VIN2+ changes from low to high and VIN 2-changes from high to low, VOUT2+ changes from high to low and VOUT 2-changes from low to high; when VIN2+ changes from low to high and VIN 2-changes from high to low, VOUT2+ changes from high to low and VOUT 2-changes from low to high; if Isctrl2Increase, Ictrl2The transistor PM2 and the transistor PM3 are mirrored through the transistor PM0, so that the leakage current flowing through the transistor PM2 and the transistor PM3 is increased, the pull-up current of VOUT2+ or VOUT 2-is increased from low to high, and the turnover speed is higher; if Isctrl2Reduction, Ictrl2The mirror image of the transistor PM0 to the transistor PM2 and the transistor PM3 causes the leakage current flowing through the transistor PM2 and the transistor PM3 to be reduced, so that the pull-up current of VOUT2+ or VOUT 2-is reduced from low to high, and the turnover speed is slower.
In the third-stage oscillation unit, input ends VIN3+ and VIN 3-are VOUT2+ and VOUT2+ of the second-stage oscillation unit respectively; if Isctrl3Increase, Ictrl3The transistor PM2 and the transistor PM3 are mirrored through the transistor PM0, so that the leakage current flowing through the transistor PM2 and the transistor PM3 is increased, the pull-up current of VOUT3+ or VOUT 3-is increased from low to high, and the turnover speed is higher; if Isctrl3Reduction, Ictrl3Mirroring to the transistor PM2 and the transistor PM3 through the transistor PM0 results in a reduction in leakage current flowing through the transistor PM2 and the transistor PM3,so that VOUT3+ or VOUT 3-is reduced from low to high pull-up current, and the turnover speed is slower. VOUT3+, VOUT 3-are connected to VIN1-, VIN1+ again, and the overturning speed is controlled continuously through a loop. Through the structure of the directional cascade of the three-level oscillation units, the accurate control of the control current Ictrl on the output clock frequency can be realized, namely the positive correlation between the control voltage and the output clock frequency.
Referring to fig. 5, fig. 5 is a circuit configuration diagram of a configurable center frequency adjustment module in the present invention; each stage of the cross-coupled oscillation unit output end is provided with a configurable central frequency adjusting module; when the configuration signal TR <1:0> is 00 or 10, all the switching tubes M0, M1, M2 and M3 in the circuit are turned off, and the central frequency adjusting module does not work; when the configuration signal TR <1:0> is 01, the switching tubes M0 and M1 are opened, the switching tubes M2 and M3 are closed, the PMOS capacitors M4 and M6 start to act, the load capacitance of each stage of oscillation unit is increased, namely, the time constant is increased, and the central frequency of the PLL is reduced; when the configuration signal TR <1:0> is 11, the switching tubes M0, M1, M2 and M3 are all turned on, the MOS capacitors M4, M5, M6 and M7 start to act, the load capacitance of each stage of oscillating unit is increased, and the center frequency of the PLL is further reduced.
The invention relates to a high-speed high-precision phase-locked loop circuit for an oversized area array CMOS (complementary metal oxide semiconductor) image sensor, which comprises a voltage-controlled oscillator formed by cascading three levels of cross-coupled oscillator units, wherein the input voltage Vcrtl of the voltage-controlled oscillator can be converted into Ictrl, and the Ictl adjusts the signal turning speed of an oscillation unit through a mirror current source so as to achieve the purpose of adjusting the output frequency; after the control voltage is converted into extra reverse current, the adjustable range of the working frequency of the oscillator is greatly increased; secondly, the controlled current source can effectively inhibit the influence of power ground noise, a three-level cross coupling complementary structure is adopted, and the sizes of the NMOS differential pair and the PMOS differential pair are properly adjusted to keep the rising edge and the falling edge of the oscillation signal consistent, so that the influence of the output waveform on the phase noise is reduced. In addition, the output swing is close to the power supply voltage, and the phase noise can be reduced.
Furthermore, a configurable central oscillation frequency adjusting circuit is used for a clock generator of the CMOS image sensor to adjust the self output clock frequency according to the change of the frame frequency, so that the addition of the configurable central oscillation frequency adjusting circuit in a phase-locked loop clock generating module is necessary; the specific implementation mode is that a capacitor with adjustable size is added to the differential output end of each stage of cross-coupled oscillator unit, so that the overturning load of each stage of oscillation unit is adjusted, and the purpose of adjusting the frequency of an output clock is achieved.
The low-pass filter of the phase-locked loop circuit adopts a capacitor and a resistor which can be configured and adjusted, and aims to dynamically adjust the bandwidth of the phase-locked loop circuit according to different input clocks and frequency dividing ratios, namely different working frequencies of a voltage-controlled oscillator, thereby greatly improving the stability and reliability of a clock generator.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.

Claims (2)

1. A high-speed high-precision phase-locked loop circuit for an oversized area array CMOS image sensor is characterized by comprising a reset tube NM5, a transistor NM2, a transistor NM3, a transistor NM4, a first-stage cross-coupling complementary oscillation unit, a second-stage cross-coupling complementary oscillation unit and a third-stage cross-coupling complementary oscillation unit;
the first-stage cross-coupling complementary oscillation unit, the second-stage cross-coupling complementary oscillation unit and the third-stage cross-coupling complementary oscillation unit are sequentially in reverse cascade connection;
the gate terminal of the reset tube NM5 is connected with a PowerDown signal, the drain terminal of the reset tube NM5, the gate terminal of the transistor NM2, the gate terminal of the transistor NM3 and the gate terminal of the transistor NM4 are all connected with an input voltage terminal, the source terminal of the transistor NM2, the source terminal of the transistor NM3, the source terminal of the transistor NM4 and the source terminal of the reset tube NM5 are all grounded, and the drain terminal of the transistor NM2 outputs Iictrl1,Ictrl1Inputting the current as frequency regulation current into a first-stage cross-coupling complementary oscillation unit;
drain output Ictrl of transistor NM32,Ictrl2Inputting the current as frequency adjusting current into a second-stage cross-coupled complementary oscillation unit;
drain output Ictrl of transistor NM43,Ictrl3Inputting the current as frequency regulation current into a third-stage cross-coupling complementary oscillation unit;
the first-stage cross-coupled complementary oscillation unit includes a transistor PM0, a transistor PM2, a transistor PM3, a transistor PM4, a transistor PM5, a transistor NM0, and a transistor NM 1;
the drain terminal and the gate terminal of the transistor PM0 are in short circuit, and the drain terminal and the gate terminal are both input into Ictrl1The gate terminal of the transistor PM0 is also connected with the gate terminal of the transistor PM2 and the gate terminal of the transistor PM3, the source terminal of the transistor PM0, the source terminal of the transistor PM2, the source terminal of the transistor PM3, the source terminal of the transistor PM4 and the source terminal of the transistor PM5 are all connected with power supply terminals, the drain terminal of the transistor PM3 is connected with the drain terminal of the transistor PM5 and then connected with an output terminal, the gate terminal of the transistor PM4 is connected with the drain terminal of the transistor NM1 and then connected with an output terminal, and the output terminal is used for outputting an output signal VOUT1 +;
the drain terminal of the transistor PM 2is connected with the drain terminal of the transistor PM4 and then connected with the output terminal, the gate terminal of the transistor PM5 is connected with the drain terminal of the transistor NM0 and then connected with the output terminal, and the output terminal is used for outputting an output signal VOUT 1-;
the source end of the transistor NM0 and the source end of the transistor NM1 are both grounded;
the circuit structures of the second-stage cross-coupling complementary oscillation unit and the third-stage cross-coupling complementary oscillation unit are the same as the circuit structure of the first-stage cross-coupling complementary oscillation unit;
the output ends of the first-stage cross-coupling complementary oscillation unit, the second-stage cross-coupling complementary oscillation unit and the third-stage cross-coupling complementary oscillation unit are respectively provided with a configurable central frequency adjusting module for adjusting the load capacitance of the oscillation unit;
the configurable center frequency adjusting module comprises a switch M0, a switch M1, a switch M2, a switch M3, a PMOS capacitor M4, a PMOS capacitor M5, an NMOS capacitor M6 and an NMOS capacitor M7, wherein the switch M0 and the switch M3 are both NMOS, and the switch M1 and the switch M2 are both PMOS;
the source end of the switch M0 and the source end of the switch M1 are connected with the output end of the cross-coupling complementary oscillation unit, the gate end of the switch M0 and the gate end of the switch M1 are connected with configuration signals, the drain end of the switch M0 and the drain end of the switch M1 are connected with the gate end of the PMOS capacitor M4, the gate end of the NMOS capacitor M6, the source end of the switch M2 and the source end of the switch M3 respectively, the gate end of the switch M2 and the gate end of the switch M3 are connected with configuration signals, the drain end of the switch M2 and the drain end of the switch M3 are connected with the gate end of the PMOS capacitor M5 and the gate end of the NMOS capacitor M7 respectively, the source end and the drain end of the PMOS capacitor M4 are connected with power supply ends, the source end and the drain end of the PMOS capacitor M source end 5 are connected with power supply ends, the drain end and the drain end of the NMOS capacitor M6 are grounded, and the drain;
when the configuration signal TR <1:0> is 00 or 10, the switches M0, M1, M2 and M3 are all in an off state;
when the configuration signal TR <1:0> is 01, the switches M0 and M1 are in an open state, and the switches M2 and M3 are in a closed state;
when the configuration signal TR <1:0> is 11, the switches M0, M1, M2 and M3 are all in the on state.
2. The high-speed high-precision phase-locked loop circuit for the ultra-large area array CMOS image sensor as claimed in claim 1, wherein output signals VOUT1-, VOUT1+ of the first stage cross-coupled complementary oscillation unit are respectively used as input signals VIN2+ and VIN 2-of the second stage cross-coupled complementary oscillation unit;
the output signals VOUT 2-VOUT 2+ of the second-stage cross-coupled complementary oscillation unit are respectively used as the input signals VIN3+ and VIN 3-of the third-stage cross-coupled complementary oscillation unit.
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JP6439367B2 (en) * 2014-10-10 2018-12-19 富士通株式会社 Delay circuit, phase synchronization circuit having delay circuit, and processor having phase synchronization circuit
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Publication number Priority date Publication date Assignee Title
CN101521498A (en) * 2008-02-29 2009-09-02 北京芯慧同用微电子技术有限责任公司 Voltage controlled oscillator
CN202617065U (en) * 2012-02-28 2012-12-19 无锡芯骋微电子有限公司 Low voltage voltage-controlled oscillator capable of restraining power supply noise
CN102843132A (en) * 2012-02-28 2012-12-26 无锡芯骋微电子有限公司 Low-voltage voltage-controlled oscillator capable of inhibiting power noise

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