CN114388017A - Oscillation circuit and memory - Google Patents

Oscillation circuit and memory Download PDF

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Publication number
CN114388017A
CN114388017A CN202111641263.7A CN202111641263A CN114388017A CN 114388017 A CN114388017 A CN 114388017A CN 202111641263 A CN202111641263 A CN 202111641263A CN 114388017 A CN114388017 A CN 114388017A
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China
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charge
pmos tube
tube
discharge
module
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Chinese (zh)
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陈斌
孙英
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China Flash Co Ltd
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China Flash Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits

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Abstract

The invention provides an oscillation circuit and a memory, comprising: a reference current generating module generating a reference current irrelevant to the power voltage; a reference voltage generating module generating a reference voltage linearly related to the power supply voltage; the charging and discharging module is used for charging and discharging two same charging and discharging channels based on the reference current and the reference voltage, wherein the charging and discharging states of the two charging and discharging channels are opposite, and the discharging time is irrelevant to the power voltage; the feedback module is used for generating a charging and discharging control signal of the charging and discharging module based on an output signal of the charging and discharging module; and the clock output module generates a clock signal based on the charge and discharge control signal. The oscillating circuit can generate a clock signal which has low power consumption, is irrelevant to power supply voltage, has stable and adjustable frequency and 50 percent of duty ratio, and has wide application range; in the NOR FLASH memory, a high-quality clock signal can be provided for a high-voltage generation module of the NOR FLASH memory, and the working performance of the memory is improved.

Description

Oscillation circuit and memory
Technical Field
The present invention relates to the field of semiconductor memory technology, and in particular, to an oscillation circuit and a memory.
Background
At present, the reading, writing and erasing of data of the NOR FLASH require a high-voltage system to generate corresponding voltage, and an essential circuit in the high-voltage system comprises an oscillating circuit; the power consumption and the output frequency of the oscillating circuit are important design parameters, and the output frequency can directly influence the output performance of the high-voltage system.
The purpose of the oscillator circuit is to generate a stable clock for the system, and the conventional structure is a loop oscillator, which is implemented by an odd number of inverters connected end to end, as shown in fig. 1. Each inverter takes a certain time to completely convert the waveform of the input signal into the corresponding waveform of the output signal, and this time is referred to herein as the delay time of the inverter. Assuming that the delay time of each inverter is T _ D, the delay of 2N +3(N ≧ 0, N ∈ N) stages of inverters is (2N +3) T _ D. IN fig. 1, it is assumed that the IN is switched from a low level '0' to a high level '1', the OUT point is pulled to a low level '0' after the delay of (2n +3) T _ D time, and the OUT point is pulled to a high level '1' after the delay of (2n +3) T _ D time, forming a cycle inversion, and repeatedly switching between high and low levels for a certain time to form a clock. The fixed time is the clock period T of the loop oscillator, which is 2(2n +3) T _ D, and finally the frequency is converted into the frequency by the formula f-1/T, where T is the clock period of the oscillator and f is the clock frequency of the oscillator.
The main parameter related to the frequency of the loop oscillator is the delay time T _ D of the inverter, but the time varies with the supply voltage, and generally, the higher the supply voltage, the faster the clock frequency will be, and the clock frequency will directly affect the performance of the charge pump (charge pump) in the high voltage system. The relationship between the clock frequency f and the efficiency η in the charge pump system is shown in fig. 2, where the efficiency increases with the clock frequency in a certain frequency range, and the efficiency decreases with the increase of the clock frequency after exceeding a certain frequency. The fastest clock frequency in practical charge pump system designs generally does not exceed the optimal frequency point f2, and the typical case design will consider placing it at the frequency point f 1. When the fluctuation range of the clock frequency is large, the efficiency point is low under some conditions. For these reasons, a relatively stable clock is critical, and conventional structures tend to fluctuate with fluctuations in the supply voltage, over a wide range of operating voltages, resulting in some loss of performance with increased design difficulty.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides an oscillating circuit and a memory, which are used to solve the problem that the output frequency of the oscillating circuit is affected by the power supply voltage in the prior art.
To achieve the above and other related objects, the present invention provides an oscillation circuit, comprising at least:
the reference current generating module is used for generating reference current irrelevant to power supply voltage;
the reference voltage generating module is used for generating a reference voltage linearly related to the power supply voltage;
the charging and discharging module is connected to the output ends of the reference current generating module and the reference voltage generating module and is used for charging and discharging two same charging and discharging channels based on the reference current and the reference voltage, wherein the charging and discharging states of the two charging and discharging channels are opposite, and the discharging time is irrelevant to the power supply voltage;
the feedback module is connected to the output end of the charge-discharge module and generates charge-discharge control signals of the charge-discharge module based on the output signals of the charge-discharge module; and the number of the first and second groups,
and the clock output module is connected to the output end of the feedback module and generates a clock signal based on the charge and discharge control signal.
Optionally, the reference current generating module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a resistor;
one end of the resistor is grounded, and the other end of the resistor is connected with the source electrode of the first NMOS tube; the drain electrode of the first NMOS tube is connected with the drain electrode and the grid electrode of the first PMOS tube; the source electrode of the first PMOS tube is connected with the power supply voltage; the source electrode of the second PMOS tube is connected with the power supply voltage, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is connected with the drain electrode and the grid electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded; and the source electrode of the third PMOS tube is connected with the power supply voltage, the grid electrode of the third PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the third PMOS tube outputs the reference current.
Optionally, the reference voltage generating module includes a fourth PMOS transistor, a fifth PMOS transistor, and a first current source;
the source electrode of the fourth PMOS tube is connected with the power supply voltage, and the grid electrode and the drain electrode of the fourth PMOS tube are connected with the source electrode of the fifth PMOS tube; the grid electrode and the drain electrode of the fifth PMOS tube are connected with the first current source; and the drain electrode of the fifth PMOS tube outputs the reference voltage.
More optionally, the first current source is obtained by mirroring the reference current through a current mirror.
Optionally, the charge and discharge module includes a first charge and discharge path and a second charge and discharge path;
the first charge-discharge path comprises a sixth PMOS tube, a seventh PMOS tube, a third NMOS tube, a second current source and a first capacitor; the source electrode of the sixth PMOS tube is connected with the power supply voltage, the grid electrode of the sixth PMOS tube receives a first charge-discharge control signal, and the drain electrode of the sixth PMOS tube is connected with the upper polar plate of the first capacitor; the lower polar plate of the first capacitor is grounded; the source electrode of the seventh PMOS tube is connected with the upper polar plate of the first capacitor, the grid electrode of the seventh PMOS tube is connected with the reference voltage, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the third NMOS tube and outputs a first charge-discharge signal; the grid electrode of the third NMOS tube receives the first charge-discharge control signal, and the source electrode of the third NMOS tube is connected with the second current source;
the second charge-discharge path comprises an eighth PMOS (P-channel metal oxide semiconductor) tube, a ninth PMOS tube, a fourth NMOS (N-channel metal oxide semiconductor) tube, a third current source and a second capacitor; the source electrode of the eighth PMOS tube is connected with the power supply voltage, the grid electrode of the eighth PMOS tube receives a second charge and discharge control signal, and the drain electrode of the eighth PMOS tube is connected with the upper polar plate of the second capacitor; the lower polar plate of the second capacitor is grounded; the source electrode of the ninth PMOS tube is connected with the upper polar plate of the second capacitor, the grid electrode of the ninth PMOS tube is connected with the reference voltage, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the fourth NMOS tube and outputs a second charge-discharge signal; the grid electrode of the fourth NMOS tube receives the second charge and discharge control signal, and the source electrode of the fourth NMOS tube is connected with the third current source;
the first charge and discharge control signal and the second charge and discharge control signal are opposite-phase signals.
More optionally, the duty ratio of the first charge and discharge control signal and the second charge and discharge control signal is 50%.
More optionally, the second current source and the third current source are obtained by mirroring the reference current through a current mirror.
More optionally, the period of the clock signal satisfies:
TCLK＝(2C*VTHP)/(K*Ibias)；
wherein, TCLKIs a clock period, VTHPThe threshold voltage of the PMOS device is C, the capacitance value of the first capacitor and the second capacitor is C, Ibias is the reference current, and K is a mirror image multiple of the second current source and the third current source.
More optionally, the feedback module includes an RS latch, an and logic unit, and an or logic unit; a first input end of the RS latch receives the first charge-discharge signal, and a second input end of the RS latch receives the second charge-discharge signal; the first input end of the AND logic unit is connected with an enable signal, the second input end of the AND logic unit is connected with the first output end of the RS latch, and the second charge and discharge control signal is output; and a first input end of the OR logic unit is used for outputting the inverted signal of the enable signal, and a second input end of the OR logic unit is connected with a second output end of the RS trigger and outputs the first charge and discharge control signal.
More optionally, the RS latch includes a first nand logic unit and a second nand logic unit, a first input end of the first nand logic unit is connected to the first charge and discharge signal, a second end of the first nand logic unit is connected to an output end of the second nand logic unit, and an output end of the first nand logic unit is used as a first output end of the RS latch; and the first input end of the second NAND logic unit is connected with the second charge-discharge signal, the second end of the second NAND logic unit is connected with the output end of the first NAND logic unit, and the output end of the second NAND logic unit is used as the second output end of the RS latch.
Optionally, the clock output module includes a first driving unit and a second driving unit; the first driving unit receives the second charge-discharge control signal and generates a first clock signal; the second driving unit receives the first charge-discharge control signal and generates a second clock signal; the first clock signal and the second clock signal are inverse signals.
To achieve the above and other related objects, the present invention provides a memory, comprising at least: in the above oscillating circuit, the oscillating circuit provides a clock signal for the memory circuit.
Optionally, the oscillation circuit provides a clock signal for a high voltage generation module in the memory.
More optionally, the memory is NOR FLASH.
As described above, the oscillation circuit and the memory according to the present invention have the following advantageous effects:
the oscillating circuit can generate a clock signal which has low power consumption, is irrelevant to power supply voltage, has stable and adjustable frequency and 50 percent of duty ratio, and has wide application range; in the NOR FLASH memory, a high-quality clock signal can be provided for a high-voltage generation module of the NOR FLASH memory, and the working performance of the memory is improved.
Drawings
Fig. 1 is a schematic diagram of a prior art ring oscillator.
Fig. 2 is a graph showing the relationship between clock frequency and charge pump efficiency.
Fig. 3 is a schematic diagram of an oscillating circuit according to the present invention.
Fig. 4 is a schematic structural diagram of a reference current generating module according to the present invention.
FIG. 5 is a schematic diagram of a reference voltage generating module according to the present invention.
FIG. 6 is a schematic diagram of an embodiment of a reference voltage generating module according to the present invention.
Fig. 7 is a schematic structural diagram of a charge-discharge module according to the present invention.
FIG. 8 is a schematic diagram of a feedback electrical module according to the present invention.
FIG. 9 is a timing diagram illustrating the operation of the oscillating circuit according to the present invention.
Description of the element reference numerals
1 oscillating circuit
11 reference current generating module
12 reference voltage generating module
13 charge-discharge module
131 first charge-discharge path
132 second charge and discharge path
14 feedback module
141 RS latch
141a first nand logic cell
141b second nand logic cell
142 and logic unit
143 or logic cell
15 clock output module
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 3 to fig. 9. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
As shown in fig. 3, the present embodiment provides an oscillation circuit 1 with low power consumption and without output frequency drift with power supply voltage variation, where the oscillation circuit 1 includes:
the device comprises a reference current generating module 11, a reference voltage generating module 12, a charging and discharging module 13, a feedback module 14 and a clock output module 15.
As shown in fig. 3, the reference current generating module 11 is configured to generate a stable reference current Ibias independent of the power supply voltage.
Specifically, as shown in fig. 4, the reference current generating module 11 includes, as an example, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a first NMOS transistor N1, a second NMOS transistor N2, and a resistor R1. One end of the resistor R1 is grounded, and the other end of the resistor R1 is connected with the source electrode of the first NMOS transistor N1; the drain electrode of the first NMOS transistor N1 is connected to the drain electrode and the gate electrode of the first PMOS transistor P1; the source electrode of the first PMOS pipe P1 is connected with the power supply voltage VDD; the source electrode of the second PMOS tube P2 is connected with the power supply voltage VDD, the grid electrode of the second PMOS tube P3578 is connected with the grid electrode of the first PMOS tube N1, and the drain electrode of the second PMOS tube P2 is connected with the drain electrode and the grid electrode of the second NMOS tube N2; the grid electrode of the second NMOS transistor N2 is connected with the grid electrode of the first NMOS transistor N1, and the source electrode is grounded; the source electrode of the third PMOS tube P3 is connected with the power supply voltage VDD, the grid electrode of the third PMOS tube P3 is connected with the grid electrode of the first PMOS tube P3, and the drain electrode of the third PMOS tube P3 outputs the reference current Ibias.
It should be noted that any circuit configuration capable of generating the reference current Ibias regardless of the power supply voltage is applicable to the present invention, and is not limited to this embodiment.
As shown in fig. 3, the reference voltage generation module 12 is configured to generate a reference voltage Vbias linearly related to a power supply voltage.
Specifically, in the present embodiment, the reference voltage generation module 12 generates the reference voltage Vbias based on the reference current Ibias. As shown in fig. 5, the reference voltage generating module 12 includes, as an example, a fourth PMOS transistor P4, a fifth PMOS transistor P5, and a first current source Ibias 1. The source electrode of the fourth PMOS tube P4 is connected with the power supply voltage VDD, and the grid electrode and the drain electrode are connected with the source electrode of the fifth PMOS tube P5; the grid electrode and the drain electrode of the fifth PMOS pipe P5 are connected with the first current source Ibias 1; the drain of the fifth PMOS transistor P5 outputs the reference voltage Vbias. As an implementation of this example, the first current source Ibias1 is mirrored by a current mirror from the reference current Ibias; as shown in fig. 6, the drain and the gate of the fifth NMOS transistor N5 receive the reference current Ibias, and the source is grounded; the source electrode of the sixth NMOS transistor N6 is grounded, the grid electrode of the sixth NMOS transistor N5 is connected with the grid electrode of the fifth NMOS transistor N5 to receive the bias voltage Vbn, and the drain electrode of the sixth NMOS transistor N5 is connected with the drain electrode of the fifth PMOS transistor N5; adjusting the current flowing through the sixth NMOS transistor N6 based on the bias voltage Vbn to obtain the first current source Ibias 1; the adjustment of the magnitude of the first current source Ibias1 can be realized by adjusting the proportional relationship, which is not described herein in detail.
Specifically, when the reference voltage generating module 12 is in operation, the power supply voltage VDD passes through the fourth PMOS transistor P4 and the fifth PMOS transistor P5 of the diode structure, and the reference voltage Vbias is generated under the action of the weak current Ibias1, and the voltage value of the reference voltage Vbias is VDD-2V because the voltage passing through the forward conducting diode structure will be reduced by a threshold voltage VthTHPWherein V isTHPIs the threshold voltage of the fourth PMOS transistor P4 and the fifth PMOS transistor P5.
As shown in fig. 3, the charge/discharge module 13 is connected to the output ends of the reference current generation module 11 and the reference voltage generation module 12, and charges/discharges two identical charge/discharge paths based on the reference current Ibias and the reference voltage Vbias, where the charge/discharge states of the two charge/discharge paths are opposite, and the discharge time is unrelated to the power supply voltage VDD.
Specifically, in this embodiment, the charge and discharge module 13 includes a first charge and discharge path 131 and a second charge and discharge path 132. The first charge/discharge path 131 includes a sixth PMOS transistor P6, a seventh PMOS transistor P7, a third NMOS transistor N3, a second current source Ibias2, and a first capacitor C1. The source electrode of the sixth PMOS transistor P6 is connected to the power supply voltage VDD, the gate electrode of the sixth PMOS transistor P6 receives a first charge-discharge control signal CS1, and the drain electrode of the sixth PMOS transistor P6 is connected to the upper plate of the first capacitor C1; the lower plate of the first capacitor C1 is grounded; a source electrode of the seventh PMOS transistor P7 is connected to an upper electrode plate of the first capacitor C1, a gate electrode of the seventh PMOS transistor P7 is connected to the reference voltage Vbias, and a drain electrode of the seventh PMOS transistor P7 is connected to a drain electrode of the third NMOS transistor N3 and outputs a first charge/discharge signal Vd 1; the gate of the third NMOS transistor N3 receives the first charge and discharge control signal CS1, and the source is connected to the second current source Ibias 2. The second charge-discharge path 132 includes an eighth PMOS transistor P8, a ninth PMOS transistor P9, a fourth NMOS transistor N4, a third current source Ibias3, and a second capacitor C2; the source electrode of the eighth PMOS transistor P8 is connected to the power supply voltage VDD, the gate electrode of the eighth PMOS transistor P8 receives a second charge and discharge control signal CS2, and the drain electrode of the eighth PMOS transistor P8 is connected to the upper plate of the second capacitor C2; the lower plate of the second capacitor C2 is grounded; a source electrode of the ninth PMOS transistor P9 is connected to an upper electrode plate of the second capacitor C2, a gate electrode of the ninth PMOS transistor P9 is connected to the reference voltage Vbias, and a drain electrode of the ninth PMOS transistor P9 is connected to a drain electrode of the fourth NMOS transistor N4 and outputs a second charge/discharge signal Vd 2; the gate of the fourth NMOS transistor N4 receives the second charge and discharge control signal CS2, and the source is connected to the third current source Ibias 3; the first charge and discharge control signal CS1 and the second charge and discharge control signal CS2 are inverted signals.
Specifically, as an example, the second current source Ibias2 and the third current source Ibias3 are obtained by mirroring the reference current Ibias through a current mirror, which is shown in fig. 6 and is not described herein again.
Specifically, as another example, the duty ratio of the first charge and discharge control signal CS1 to the second charge and discharge control signal CS2 is 50%; in actual use, the duty ratio can be set as required, and is not limited to the embodiment.
It should be noted that the first charge-discharge path 131 and the second charge-discharge path 132 have the same structure, the sixth PMOS transistor P6 and the eighth PMOS transistor P8 have the same size, the seventh PMOS transistor P7 and the ninth PMOS transistor P9 have the same size, the third NMOS transistor N3 and the fourth NMOS transistor N4 have the same size, the first capacitor C1 and the second capacitor C2 have the same capacitance, and the second current source Ibias2 and the third current source Ibias3 have the same size.
Specifically, taking the first charge/discharge path 131 as an example, when the first charge/discharge path 131 operates, the sixth PMOS transistor P6 and the third NMOS transistor N3 are controlled by the first charge/discharge control signal CS 1. When saidWhen the first charge-discharge control signal CS1 is '0', the sixth PMOS transistor P6 is turned on, the third NMOS transistor N3 is turned off, the first capacitor C1 is charged through the sixth PMOS transistor P6, and finally the node Vc1 and the node Vd1 are charged to VDD, that is, to '1'. When the first charge-discharge control signal CS1 is '1', the sixth PMOS transistor P6 is turned off, the third NMOS transistor N3 is turned on, the first capacitor C1 discharges through the seventh PMOS transistor P7 and the third NMOS transistor N3, and the discharge current is Ibias 2. However, since the Gate voltage of the seventh PMOS transistor P7 is Vbias, and the PMOS turn-on condition is VGS>VTHPTherefore, the node Vc1 can be discharged to VDD-V finallyTHPHowever, the node Vd1 will discharge to GND, i.e., to '0'. When the first charge/discharge control signal CS1 is discharged at '1', the discharge voltage is discharged from VDD to VDD-V at the node Vc1THPThe voltage difference is fixed to be delta V, the threshold voltage of the PMOS device is fixed to be delta V, the second current source Ibias2 is not changed along with the change of the power supply voltage, and the discharge time T is shortCSatisfies the following conditions: t isC(C × Δ V)/Ibias2, where C is the capacitance of the first capacitor C1 and Ibias2 is the current value of the second current source, and the discharge time T is knownCWill not vary with the supply voltage.
Specifically, the principle of the second charge and discharge path 132 is the same, except that the charge and discharge state is opposite to that of the first charge and discharge path 131, which is not described herein again. The first and second charge/ discharge paths 131 and 132 are repeatedly charged and discharged to output a clock signal with a period of 2 × TC。
As shown in fig. 3, the feedback module 14 is connected to an output end of the charge and discharge module 13, and generates a charge and discharge control signal of the charge and discharge module 13 based on an output signal of the charge and discharge module 13.
Specifically, in the present embodiment, the feedback module 14 includes an RS latch 141, an and logic unit 412, and an or logic unit 143. A first input end IN1 of the RS latch 141 receives the first charge and discharge signal Vd1, and a second input end IN2 receives the second charge and discharge signal Vd 2; a first input end of the and logic unit 142 is connected to an enable signal EN, a second input end of the and logic unit is connected to the first output end Q of the RS latch 141, and the second charge and discharge control signal CS2 is output; a first input end of the or logic unit 143 is connected to the inverted signal ENb of the enable signal, and a second input end thereof is connected to the second output end Qb of the RS flip-flop 141, so as to output the first charge and discharge control signal CS 1. As an example, the RS latch 141 is implemented by a nand logic unit, as shown in fig. 8, the RS latch 141 includes a first nand logic unit 141a and a second nand logic unit 141b, a first input end of the first nand logic unit 141a is connected to the first charge/discharge signal Vd1, a second end of the first nand logic unit 141a is connected to an output end of the second nand logic unit 141b, and an output end of the first nand logic unit 141a is used as a first output end of the RS latch 141; a first input end of the second nand logic unit 141b is connected to the second charge and discharge signal Vd2, a second end of the second nand logic unit 141b is connected to an output end of the first nand logic unit 141a, and an output end of the second nand logic unit 141b is used as a second output end of the RS latch 141. In practical use, different devices can be selected as needed to implement the RS latch 141, which is not limited to this embodiment.
Specifically, a feedback system is required for discharging the second charge-discharge path 132 after the discharge of the first charge-discharge path 131 is completed, and the feedback is realized by using two states of opposite input signals in the RS latch 141, as shown in the following table: when the first input terminal IN1 is '1' and the second input terminal IN2 is '0', the first output terminal Q is '0' and the second output terminal Qb is '1'; when the first input terminal IN1 becomes '0' and the second input terminal IN2 becomes '1', the first output terminal Q is '1' and the second output terminal Qb is '0'.
IN1 IN2 Q Qb
0 0 1 1
0 1 1 0
1 0 0 1
1 1 Holding Holding
As shown in fig. 3, the clock output module 15 is connected to an output end of the feedback module 14, and generates a clock signal based on the charge and discharge control signal.
Specifically, the clock output module 15 includes a first driving unit and a second driving unit (not shown); the first driving unit receives the second charge and discharge control signal CS2 and generates a first clock signal CK. The second driving unit receives the first charge-discharge control signal CS1 and generates a second clock signal CKb; the first clock signal CK and the second clock signal CKb are inverse signals. As an example, the first driving unit and the second driving unit each include odd-numbered stages of inverters connected in series, including but not limited to 1-stage or 3-stage inverters, and the driving capability is enhanced by the inverters.
It should be noted that, in practical use, any driving unit structure capable of enhancing the driving capability is applicable to the present invention, and is not limited to this embodiment.
As shown in fig. 9, an operation timing chart of the oscillation circuit 1 is shown, where EN is a circuit enable signal, and as an example, high level is active. When the enable signal EN is changed from '0' to '1', the first charge-discharge control signal CS1 is changed from '1' to '0', the first capacitor C1 is charged through the sixth PMOS transistor P6, and the node Vd1 is charged through the sixth PMOS transistor P6 and the seventh PMOS transistor P7; meanwhile, the second charge and discharge control signal CS2 is changed from '0' to '1', the second capacitor C2 is discharged to the ninth PMOS transistor P9 through the ninth PMOS transistor P9 and the fourth NMOS transistor N4 with a small current Ibias3 and is turned off, and the node Vd2 is rapidly discharged to '0' because the second capacitor C2 is isolated by the ninth PMOS transistor P9.
When the node Vd2 discharges to '0', the first charge/discharge control signal CS1 changes from '0' to '1' due to the feedback of the RS latch 141, the first capacitor C1 discharges to the seventh PMOS P7 with a small current Ibias2 through the seventh PMOS P7 and the third NMOS N3, and at this time, the node Vd1 discharges to '0' quickly because the first capacitor C1 is isolated by the seventh PMOS P7.
When the node Vd1 discharges to '0', the second capacitor C2 is discharged again, so that two signals CS1 and CS2 with opposite phases are formed, and the clock signals CK and CKb are finally output through the clock output module.
The invention obtains the reference voltage relevant to the power supply through the specific structure, fully utilizes the conduction characteristic of the PMOS device, eliminates the influence of the power supply to obtain the fixed voltage difference irrelevant to the power supply, and realizes the oscillating circuit irrelevant to the output frequency and the power supply voltage by matching with the reference current generation scheme and the RS latch structure. The period of the clock signal of the invention satisfies the following relation:
TCLK＝(2C*VTHP)/(K*Ibias)；
wherein, TCLKIs a clock period, VTHPIs the threshold voltage of a PMOS device, C isThe capacitance values of the first capacitor and the second capacitor, Ibias is a reference current, and K is a mirror image multiple of the second current source Ibias2 and the third current source Ibias 3; without parameters related to the supply voltage VDD. The desired clock period can be obtained by adjusting any of the variables of the capacitance, the reference current, and the image multiple.
Example two
The present embodiment provides a memory, which at least includes: the oscillation circuit 1 according to the first embodiment, wherein the oscillation circuit 1 provides a clock signal for the memory.
As an example, the oscillation circuit 1 provides a clock signal to a high voltage generation module in the memory to ensure output performance of the high voltage generation module. The high voltage generating module provides a high voltage signal for the memory.
It should be noted that the memory includes but is not limited to NOR FLASH, and any device that needs to output a high-quality clock signal with a frequency that does not vary with the power supply voltage is suitable for the present invention, and is not described herein.
In summary, the present invention provides an oscillating circuit and a memory, including: the reference current generating module is used for generating reference current irrelevant to power supply voltage; the reference voltage generating module is used for generating a reference voltage linearly related to the power supply voltage; the charging and discharging module is connected to the output ends of the reference current generating module and the reference voltage generating module and is used for charging and discharging two same charging and discharging channels based on the reference current and the reference voltage, wherein the charging and discharging states of the two charging and discharging channels are opposite, and the discharging time is irrelevant to the power supply voltage; the feedback module is connected to the output end of the charge-discharge module and generates charge-discharge control signals of the charge-discharge module based on the output signals of the charge-discharge module; and the clock output module is connected to the output end of the feedback module and generates a clock signal based on the charge and discharge control signal. The oscillating circuit can generate a clock signal which has low power consumption, is irrelevant to power supply voltage, has stable and adjustable frequency and 50 percent of duty ratio, and has wide application range; in the NOR FLASH memory, a high-quality clock signal can be provided for a high-voltage generation module of the NOR FLASH memory, and the working performance of the memory is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (14)

1. An oscillating circuit characterized in that it comprises at least:
the reference current generating module is used for generating reference current irrelevant to power supply voltage;
the reference voltage generating module is used for generating a reference voltage linearly related to the power supply voltage;
the charging and discharging module is connected to the output ends of the reference current generating module and the reference voltage generating module and is used for charging and discharging two same charging and discharging channels based on the reference current and the reference voltage, wherein the charging and discharging states of the two charging and discharging channels are opposite, and the discharging time is irrelevant to the power supply voltage;
the feedback module is connected to the output end of the charge-discharge module and generates charge-discharge control signals of the charge-discharge module based on the output signals of the charge-discharge module; and the number of the first and second groups,
and the clock output module is connected to the output end of the feedback module and generates a clock signal based on the charge and discharge control signal.
2. The oscillation circuit of claim 1, wherein: the reference current generation module comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube and a resistor;
one end of the resistor is grounded, and the other end of the resistor is connected with the source electrode of the first NMOS tube; the drain electrode of the first NMOS tube is connected with the drain electrode and the grid electrode of the first PMOS tube; the source electrode of the first PMOS tube is connected with the power supply voltage; the source electrode of the second PMOS tube is connected with the power supply voltage, the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the second PMOS tube is connected with the drain electrode and the grid electrode of the second NMOS tube; the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube, and the source electrode of the second NMOS tube is grounded; and the source electrode of the third PMOS tube is connected with the power supply voltage, the grid electrode of the third PMOS tube is connected with the grid electrode of the first PMOS tube, and the drain electrode of the third PMOS tube outputs the reference current.
3. The oscillation circuit of claim 1, wherein: the reference voltage generating module comprises a fourth PMOS tube, a fifth PMOS tube and a first current source;
the source electrode of the fourth PMOS tube is connected with the power supply voltage, and the grid electrode and the drain electrode of the fourth PMOS tube are connected with the source electrode of the fifth PMOS tube; the grid electrode and the drain electrode of the fifth PMOS tube are connected with the first current source; and the drain electrode of the fifth PMOS tube outputs the reference voltage.
4. The oscillation circuit of claim 3, wherein: the first current source is obtained by mirroring the reference current through a current mirror.
5. The oscillation circuit of claim 1, wherein: the charge and discharge module comprises a first charge and discharge path and a second charge and discharge path;
the first charge-discharge path comprises a sixth PMOS tube, a seventh PMOS tube, a third NMOS tube, a second current source and a first capacitor; the source electrode of the sixth PMOS tube is connected with the power supply voltage, the grid electrode of the sixth PMOS tube receives a first charge-discharge control signal, and the drain electrode of the sixth PMOS tube is connected with the upper polar plate of the first capacitor; the lower polar plate of the first capacitor is grounded; the source electrode of the seventh PMOS tube is connected with the upper polar plate of the first capacitor, the grid electrode of the seventh PMOS tube is connected with the reference voltage, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the third NMOS tube and outputs a first charge-discharge signal; the grid electrode of the third NMOS tube receives the first charge-discharge control signal, and the source electrode of the third NMOS tube is connected with the second current source;
the second charge-discharge path comprises an eighth PMOS (P-channel metal oxide semiconductor) tube, a ninth PMOS tube, a fourth NMOS (N-channel metal oxide semiconductor) tube, a third current source and a second capacitor; the source electrode of the eighth PMOS tube is connected with the power supply voltage, the grid electrode of the eighth PMOS tube receives a second charge and discharge control signal, and the drain electrode of the eighth PMOS tube is connected with the upper polar plate of the second capacitor; the lower polar plate of the second capacitor is grounded; the source electrode of the ninth PMOS tube is connected with the upper polar plate of the second capacitor, the grid electrode of the ninth PMOS tube is connected with the reference voltage, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the fourth NMOS tube and outputs a second charge-discharge signal; the grid electrode of the fourth NMOS tube receives the second charge and discharge control signal, and the source electrode of the fourth NMOS tube is connected with the third current source;
the first charge and discharge control signal and the second charge and discharge control signal are opposite-phase signals.
6. The oscillation circuit of claim 5, wherein: the duty ratio of the first charge and discharge control signal to the second charge and discharge control signal is 50%.
7. The oscillation circuit of claim 5, wherein: the second current source and the third current source are obtained by mirroring the reference current through a current mirror.
8. The oscillation circuit of claim 7, wherein: the period of the clock signal satisfies:
TCLK＝(2C*VTHP)/(K*Ibias)；
wherein, TCLKIs a clock period, VTHPThe threshold voltage of the PMOS device is C, the capacitance value of the first capacitor and the second capacitor is C, Ibias is the reference current, and K is a mirror image multiple of the second current source and the third current source.
9. The oscillation circuit according to any one of claims 5 to 8, wherein: the feedback module comprises an RS latch, an AND logic unit and an OR logic unit; a first input end of the RS latch receives the first charge-discharge signal, and a second input end of the RS latch receives the second charge-discharge signal; the first input end of the AND logic unit is connected with an enable signal, the second input end of the AND logic unit is connected with the first output end of the RS latch, and the second charge and discharge control signal is output; and a first input end of the OR logic unit is used for outputting the inverted signal of the enable signal, and a second input end of the OR logic unit is connected with a second output end of the RS trigger and outputs the first charge and discharge control signal.
10. The oscillation circuit of claim 9, wherein: the RS latch comprises a first NAND logic unit and a second NAND logic unit, wherein a first input end of the first NAND logic unit is connected with the first charge-discharge signal, a second end of the first NAND logic unit is connected with an output end of the second NAND logic unit, and an output end of the first NAND logic unit is used as a first output end of the RS latch; and the first input end of the second NAND logic unit is connected with the second charge-discharge signal, the second end of the second NAND logic unit is connected with the output end of the first NAND logic unit, and the output end of the second NAND logic unit is used as the second output end of the RS latch.
11. The oscillation circuit of claim 1, wherein: the clock output module comprises a first driving unit and a second driving unit; the first driving unit receives the second charge-discharge control signal and generates a first clock signal; the second driving unit receives the first charge-discharge control signal and generates a second clock signal; the first clock signal and the second clock signal are inverse signals.
12. A memory, characterized in that the memory comprises at least: an oscillating circuit according to any one of claims 1 to 11, the oscillating circuit providing a clock signal to the memory.
13. The memory of claim 11, wherein: the oscillation circuit provides a clock signal for a high voltage generation module in the memory.
14. The memory according to claim 11 or 12, wherein: the memory is NOR FLASH.
CN202111641263.7A 2021-12-29 2021-12-29 Oscillation circuit and memory Pending CN114388017A (en)

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