WO2015037252A1 - Oscillation circuit, semiconductor integrated circuit device using same, and rotational angle detection device - Google Patents

Oscillation circuit, semiconductor integrated circuit device using same, and rotational angle detection device

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Publication number
WO2015037252A1
WO2015037252A1 PCT/JP2014/052389 JP2014052389W WO2015037252A1 WO 2015037252 A1 WO2015037252 A1 WO 2015037252A1 JP 2014052389 W JP2014052389 W JP 2014052389W WO 2015037252 A1 WO2015037252 A1 WO 2015037252A1
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WO
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Prior art keywords
terminal
circuit
output
capacitor
transistor
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PCT/JP2014/052389
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French (fr)
Japanese (ja)
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奥津 光彦
一朗 大坂
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日立オートモティブシステムズ株式会社
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01CMEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
    • G01C19/00Gyroscopes; Turn-sensitive devices using vibrating masses; Turn-sensitive devices without moving masses; Measuring angular rate using gyroscopic effects
    • G01C19/56Turn-sensitive devices using vibrating masses, e.g. vibratory angular rate sensors based on Coriolis forces
    • G01C19/5776Signal processing not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231Astable circuits
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K4/00Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06Generating pulses having essentially a finite slope or stepped portions having triangular shape

Abstract

The objective of the invention is to provide an oscillation circuit that ensures oscillation frequency precision against parameter variations, such as temperature variations, even for a relatively high frequency band. The oscillation circuit comprises: a first capacitor which is charge-driven by a current and the terminal voltage of which linearly changes in a first direction; and a second capacitor which is discharge-driven by a current in parallel with the charge-driving of the first capacitor and the terminal voltage of which linearly changes in a second direction that is opposite to the first direction. The oscillation circuit is configured to form an oscillation period on the basis of a first timing at which the terminal voltages of the first and second capacitors cross each other.

Description

Oscillating circuit, the semiconductor integrated circuit device and a rotation angle detecting apparatus using the same

The present disclosure relates to an oscillation circuit, it can be applied to the oscillating circuit to form a oscillation cycle by utilizing the charge and discharge time constant of the capacitor.

By utilizing the charge and discharge time constant of the capacitor oscillator circuit forming the oscillation period, for example, disclosed in Japanese 2001-127592 (Patent Document 1). The oscillation circuit compares a constant current generator for generating a constant current in proportion to any voltage, a capacitor is charged by the constant current generated by the constant current generation unit, a reference voltage the charging voltage of the capacitor and generates a discharge signal when the charging voltage exceeds the reference voltage, and a discharge portion for discharging the electric charge of the capacitor by the discharge signal, takes out the discharge signal generated by the discharge unit as an oscillating output It has become way.

JP 2001-127592 JP

As shown in FIG. 2 of Patent Document 1, the oscillation period (TS) is the plus discharge signal width (TP) to the charging time (T), in Patent Document 1, the discharge signal width (TP) is about 1/1000 of the charging time (T), practically be regarded as the oscillation period of charging time (T) (TS) has no problem. However, it would cause problems, particularly in applications requiring an oscillation output of the high frequency.

Always finite time width to discharge the capacitor (C) is required, this assuming approximately 10 ns (= discharge signal width (TP)), the oscillation frequency is 100 KHz (the oscillation period (TS) = 10μs) in extent practical problem if there is considered to be that there is no. However, for example 20MHz in the case of obtaining the oscillation frequency of the order of (oscillation period (TS) = 50 ns), the discharge signal width (TP) becomes to occupy 20% of the ratio for the period (TS), can not be ignored component of the discharge signal width (TP) in terms of oscillation frequency accuracy ensured. Specifically discharge time, i.e. the discharge signal width (TP) is dependent on the on-resistance of the NMOS transistor (N1) shown in FIG. 1 of Patent Document 1, the output of the temperature and the comparator (21) "H" level (= the power supply voltage (VCC potential of)), it becomes possible to vary further the influence of process parameters variations, such as, for example, over a 20 MHz ± 5% degree of accuracy of the oscillation frequency in a wide range of temperature range and Operating voltage to try to ensure Te is extremely difficult.

Further, in FIG. 2 of Patent Document 1, is inverted to output an "H" level of the comparator (21) when the charging voltage of the capacitor (C) reaches the reference voltage (VIN), the detection of the comparator (21) delay has been described as not. However, in practice, there is the detection delay time, which is also an obstacle to the oscillation frequency accuracy ensured in the high frequency range. More specifically, the output of the comparator (21) is inverted to "H" level, the potential difference between the inverting and non-inverting input, the comparator (21) must be opened to a level that can be sensitive. However, in order to depends on the gm of the MOS transistors constituting the input differential pair of the comparator (21) also its sensitivity level still will be affected by the parameter variation. Consequently detection response time of the comparator (21) by the parameter variations such as temperature variation also becomes possible to cause a variation, the failure in achieving the oscillation frequency accuracy ensured.

The present disclosure, it is an object to be in a high frequency band of several tens MHz to provide an oscillation circuit having an oscillation frequency accuracy.

The other problems and novel features will become apparent from the description and the accompanying drawings of the present disclosure.

Of the present disclosure will be briefly described typical ones are as follows.
That is, the oscillation circuit includes a first capacitor and a first parallel by the current in the discharge driven its terminal voltage charge driver of the capacitor to which the terminal voltage is charged driven by a current linearly changes in a first direction There comprises a second capacitor varies linearly in a second direction reverse to the first direction. The terminal voltages of the first and second capacitors is adapted to form an oscillation period based on first Tamingu crossing.

According to the oscillation circuit, it is possible to ensure the accuracy of the oscillation frequency.

It is a circuit diagram showing a configuration of an oscillation circuit according to the first embodiment. Is a waveform diagram showing the operation of the oscillation circuit according to the first embodiment. It is a circuit diagram showing a configuration of an oscillation circuit according to a first modification. Is a circuit diagram showing the configuration of a bias circuit according to a second modification. Is a circuit diagram showing a configuration of an oscillation circuit according to the second embodiment. Is a waveform diagram showing the operation of the oscillation circuit. Is a circuit diagram showing a configuration of an oscillation circuit according to a third modification. It is a circuit diagram showing a configuration of an oscillation circuit according to a fourth modification. It is a block diagram showing a configuration of a semiconductor integrated circuit device according to the third embodiment. Is a waveform diagram showing the operation of the semiconductor integrated circuit device according to the third embodiment. It is a circuit diagram of the two-phase clock generation circuit according to the third embodiment. Is a block diagram showing the configuration of a rotation angle detecting apparatus according to the fourth embodiment.

<Embodiment>
Among the embodiments will be briefly described typical ones are as follows.
(1) oscillation circuit,
Is charged driven by a current, a first capacitor whose terminal voltage is linearly changed in a first direction (C1),
Is discharged driven by a first current with the charging driving the capacitor (C1), and a second capacitor that terminal voltage from the first direction that linearly changes in a second direction opposite direction (C3),
Equipped with,
The terminal voltages of the first and second capacitors (C1, C3) is to form an oscillation period based on first Tamingu crossing (D).
Oscillation circuit (2) (1) above,
Based on the first timing (D), the first terminal voltage of the capacitor (C1) and a pull-down or pull-up in a second direction, pull the second terminal voltage of the capacitor (C3) in a first direction up or pull-down.
(3) the oscillation circuit of the above (2),
A third capacitor whose terminal voltage is charged driven linearly changes in a first direction (C2) by a current,
Is discharged driven by a current with charge driver of the third capacitor, a fourth capacitor whose terminal voltage is linearly changed in the second direction (C4),
Equipped with,
The terminal voltages of the third and fourth capacitors (C2, C4) is reversed the oscillation output on the basis of the second Tamingu crossing (C, C ').
(4) oscillation circuit (3) above,
Based on the second timing (C, C '), the third terminal voltage of the capacitor (C2) and a pull-down or pull-up in a second direction, the fourth terminal voltage of the capacitor (C4) first the pull-up or pull-down in the direction.
Oscillation circuit (5) (4) above,
The first direction is the direction of the potential of the first power supply terminal (VD1), the second direction is the direction of the reference potential,
First trimming circuit for adjusting the voltage value of the first power supply terminal (VD1) and (RL4,4,5),
And the current value of the current (I8, I9) of the terminals of the first and third capacitor (C1, C2) to charge driving, the second and fourth capacitor terminal (C3, C4) a current discharge driving (I10 , second trimming circuit (M20, M211, M212, M21i adjusting the current value of I11), and 7,8 and),
Comprising a.
(6) The semiconductor integrated circuit device,
Oscillation circuit (5) and (10),
A nonvolatile memory module for storing the trimming data of the first and second trimming circuit (12),
A logic circuit (15) controlled by a system clock generated from the oscillation output pulse of the oscillation circuit,
Comprising a.
(7) the rotation angle detecting device,
One of the oscillation circuit 5 from the 1 (22),
A servo (23) which is controlled by the oscillation output pulse clock oscillation circuit (22),
Angular velocity detecting element which receives a drive signal from the servo (23) and (24),
Comprising a.
(8) oscillation circuit,
A first power supply terminal (VD1),
First, having a second terminal, a first capacitor connected to said first terminal to a reference potential (C1),
The first constant current source provided between the first second terminal (N1) and the first power supply terminal of the capacitor (C1) (VD1) and (M8),
A first short circuit for shorting (M10) between the first second to the reference potential terminal (N1) of the capacitor (C1) based on the first control signal,
First, having a second terminal, and a second capacitor connected to said first terminal to a reference potential (C3),
Second second constant current source provided between the second terminal of the capacitor (C3) and (N3) and the reference potential and (M14),
The first short-circuiting between the second terminal (N3) and the first power supply terminal of the second capacitor based on a second control signal having the inverted polarity (C3) to the control signal (VD1) second short circuit to (M12),
First, having a second terminal, a third capacitor connected to said first terminal to a reference potential (C2),
Third third constant current source provided between the second terminal of the capacitor (C2) and (N2) and the first power supply terminal (VD1) and (M9),
Third capacitors third short circuit for short-circuiting between the second reference potential terminal (N2) of the (C2) (M11) on the basis of the second control signal,
First, having a second terminal, and a fourth capacitor connected to said first terminal to a reference potential (C4),
Fourth constant current source provided between a second reference potential terminal (N4) of the fourth capacitor (C4) and (M15),
The fourth short circuit for short-circuiting between the second terminal (N4) and the first power supply terminal of the fourth capacitor based on the first control signal (C4) (VD1) (M13),
A first comparator for comparing the second terminal potential of the first second terminal potential and the second capacitor of the capacitor (C1) (C3) (CMP1, CMP3),
A second comparator for comparing the second terminal potential of the third second terminal potential and the fourth capacitor of the capacitor (C2) (C4) (CMP2, CMP4),
Logic circuit for generating a first comparator (CMP1, CMP3) first control signal and second control signal based on the comparison output of the comparison output and the second comparator (CMP2, CMP3) of (L1, L2) and ,
Equipped with,
Logic circuit (L1, L2) is
From comparison output inversion first comparator (CMP1, CMP3) is form by detecting the intersection of the second terminal potential of the second terminal voltage and a second capacitor of the first capacitor (C1) (C3) to a second comparator (CMP2, CMP4) comparison output inversion which form by detecting the intersection of the second terminal potential of the third second terminal potential and the fourth capacitor of the capacitor (C2) (C4) within the period, the first control signal at a first polarity, also respectively output the second control signal at a second polarity,
From the second comparator (CMP2, CMP4) comparison output inversion which form by detecting the intersection of the second terminal potential of the third second terminal potential and the fourth capacitor of the capacitor (C2) (C4) first comparator (CMP1, CMP3) comparison output to the reversing that form by detecting the intersection of the second terminal potential of the second terminal voltage and a second capacitor of the first capacitor (C1) (C3) within the period, the first control signal in a second polarity, also constitute a second control signal to output respectively the first polarity,
The first short circuit (M10) is activated with a first polarity of the first control signal,
The second short circuit (M12) is activated with a second polarity of the second control signal,
The third short circuit (M11) is activated with a first polarity of the second control signal,
With the fourth short circuit (M13) is configured to activate a second polarity of the first control signal, utilizing the first or the second control signal as an oscillation output.

In this disclosure, a constant current or a constant current source, the current value is a current or a current source which is substantially constant, allowing the variation of the current value. As a result, for example, those oscillation frequency accuracy is allowed to change to the extent that within a predetermined range (± 5%).

Hereinafter, embodiments and modification will be described with reference to the drawings. However, in the following description, the explanation of repeating the same reference numerals are the same elements will be omitted.

Example 1, in the oscillation circuit which forms the oscillation period by utilizing the charging time of the capacitor by constant current, to suppress variations in oscillation period due to temperature variations, several tens of MHz (20 MHz ~ about 60 MHz) and relatively even in a high frequency range is to provide an oscillation circuit capable of ensuring the accuracy of the oscillation frequency.

Figure 1 is a circuit diagram showing a configuration of an oscillation circuit according to the first embodiment. Figure 2 is a waveform diagram showing the operation of the oscillation circuit according to the first embodiment.
(Constitution)
Oscillating circuit 10A according to the first embodiment includes an oscillator circuit core unit OSC1 and constant current generating circuit 1 and the comparison reference voltage generation circuit 2.
Constant current generating circuit 1 includes a PMOS transistor M1 and the operational amplifier (differential amplifier) ​​A1 and the resistor R1. In the PMOS transistor M1, the GND and the drain terminal through a resistor R1, its source terminal to the power supply terminal VCC, respectively connected. In the operational amplifier A1, the inverting input terminal (-) to the reference voltage input terminal VREF, its non-inverting input terminal (+) to the connection point of the drain terminal and the resistor R1 of the PMOS transistor M1 (node ​​N7), the output terminal the gate terminal of the PMOS transistor M1, is connected. In the constant current generation circuit 1, and a bias output terminal G0 of the connection point of the gate terminal of the output terminal and the PMOS transistor M1 of the operational amplifier A1. Operational amplifier A1 operates between potential and GND power supply terminal VCC.

Comparison reference voltage generation circuit 2 includes a PMOS transistor M2 and the resistor R2. In PMOS transistors M2, its drain terminal to the GND via the resistor R2, the source terminal to the power supply terminal VCC, its gate terminal to the bias output terminal G0 of the constant current generation circuit 1, is connected. In comparison reference voltage generating circuit 2, and the output terminal VR comparison reference voltage connection point between the drain terminal and the resistor R2 of the PMOS transistor M2.

Oscillator core portion OSC1 includes a PMOS transistor (first conductivity type MOS transistor) M3 and the NMOS transistor (second conductivity type MOS transistor) M5 and a PMOS transistor M4 and the NMOS transistor M6 and the logic circuit L1 and the comparator CMP1 a comparator CMP2 and the capacitors C1 and C2. In the PMOS transistor M3, the drain terminal to the capacitor C1, the source terminal to the power supply terminal VCC, its gate terminal to the bias output terminal G0, is connected. In NMOS transistors M5, its drain terminal to the drain terminal of the PMOS transistor M3, reference to the source terminal potential (hereinafter, referred to as GND) is connected to. In the PMOS transistor M4, the drain terminal to the capacitor C2, the source terminal to the power supply terminal VCC, its gate terminal to the bias output terminal GO, respectively connected. In NMOS transistors M6, the drain terminal to the drain terminal of the PMOS transistor M4, the source terminal to GND, and connected respectively. Logic circuit L1 has a set signal input terminal S and a reset signal input terminal R and the output terminal Q and the inverting output terminal QB. Logic circuit L1 is a period from the input of a rising edge to the set signal input terminal S to a rising edge is input to a reset signal input terminal R performs high (High) level signal output to the output terminal Q, a reset period from the signal input terminal R is input rising edge to rising edge is input to the set signal input terminal S performs signal output row (Low) level to the output terminal Q. The logic circuit L1 performs signal output polarity obtained by inverting the signal output from the output terminal Q to the inverted output terminal QB. The comparator CMP1, the non-inverting input terminal (+) to the connection point between the drain terminal of the capacitor C1 and the PMOS transistor M3 (node ​​N1), the inverting input terminal (-) to the output terminal VR and logic circuits its output L1 to the set signal input terminal S, respectively connected. The comparator CMP2, its non-inverting input terminal (+) of the connection point between the drain terminal of the capacitor C2 and the PMOS transistor M4 (node ​​N2), the inverting input terminal (-) to the output terminal VR and logic circuit L1 and the output a reset signal input terminal R, respectively connected. The gate terminal of the output oscillation output terminal Q terminal OUT and the NMOS transistor M5 of the logic circuit L1, also the inverted output terminal QB to the gate terminal of the NMOS transistor M6, are connected, respectively. It is also possible to take out the oscillation output from the output terminal QB of the logic circuit L1. Comparators CMP1, CMP2 and the logic circuit L1 is operating between the potential and the GND of the power supply terminal VCC.

In FIG. 1, any one end of the capacitor C1 and the capacitor C2 are connected to the GND, it is not limited thereto, for example, may be connected to the power supply terminal VCC instead GND.

The comparator CMP1, the inverting input of the comparator CMP2 (-), the connection order and the non-inverting input (+), the set signal input terminal S of the logic circuit L1, the convenience of construction also describes signal polarity of the reset signal input terminal R only, if the operation function is obtained as described below, not limited to this configuration.

(Operation)
The operation of this embodiment will be described with reference to the waveform diagram of FIG. Potential in FIG. 2 (a) of the capacitor C1 terminals (node ​​N1), the potential of FIG. (B) The terminal of the capacitor C2 (node ​​N2), FIG (c) is the output voltage of the comparator CMP1, FIG (d ) is the output voltage of the comparator CMP2, the voltage of FIG. (e) an output terminal Q of the logic circuit L1 (oscillation output terminal OUT), FIG. (f) illustrates the voltage of the inverted output terminal QB of the logic circuit L1 .

First, in the constant current generating circuit 1, the non-inverting input (+) terminal voltage of the connected resistor R1 to the operational amplifier A1 has an inverting input (-) to so as to be equal to the voltage applied to the reference voltage terminal VREF to be connected It is feedback-controlled. Therefore the current value of the current I1 flowing through the resistor R1 and the PMOS transistor M1 When I 1,
I 1 = V REF / R 1 ··· (1)
Denoted. Here, the V REF applied voltage of the reference voltage input terminal VREF, R 1 is the resistance value of the resistor R1.

The current value of the current I1 is a constant current which does not depend on the voltage applied to the power supply terminal VCC As is apparent from equation (1). Further, the PMOS transistor M2 of the comparison reference voltage in generator 2, because there the PMOS transistor M1 and the current mirror relationship of the constant current in the generator 1, is also a constant current drain current I2 of the PMOS transistor M2. Therefore the potential drop across the resistor R2 is also constant voltage. That is, the output terminal VR certain comparison reference voltage is output. The comparison reference voltage V R, the resistance value R 2 of the resistor R2, the current value of the drain current I2 if I 2,
V R = I 2 × R 2 = α × I 1 × R 2 = α × V REF × R 2 / R 1 ··· (2)
Denoted. Here, alpha is the mirror ratio of the PMOS transistor M1 and a PMOS transistor M2.

Also, because there the PMOS transistor M3 and the PMOS transistor M4 also PMOS transistor M1 and the current mirror relationship of the constant current in the generator 1, which functions as a constant current source. When the current value of the drain current I3, I4 of the PMOS transistor M3 and a PMOS transistor M4 and I 3, I 4, respectively,
I 3 (= I 4) = β × I 1 = β × V REF / R 1 ··· (3)
Denoted. Here, beta is the mirror ratio of the PMOS transistor M1 and the PMOS transistor M3 and a PMOS transistor M4.

It will now be described oscillating operation.
(A) timing A ~ timing B
Now, the output terminal Q of the logic circuit L1 is at the same time as a transition to the Low level, the inverted output terminal QB is a transition to the High level. At this time NMOS transistor M5, upon a change its gate terminal to the Low level, the transition from the ON state to the OFF state. Further, NMOS transistors M6, by its gate terminal is changed to High level, the transition from the OFF state to the ON state. Here, what the current driving capability of the NMOS transistor M5 is sufficiently large compared to the drain current I3 of the PMOS transistor M3, in its on-state, which may function as a short circuit to substantially the same potential between both terminals of the capacitor C1 to. Incidentally, similarly to the NMOS transistor M6 may NMOS transistor M5 in the capacitor C2 side, has a sufficiently large current driving capability as compared to the drain current I4 of the PMOS transistor M4, which can function as a short circuit of a capacitor C2 to.

Therefore, at the time when the NMOS transistor M5 as described above is changed from the ON state to the OFF state, the potential of the terminal of the capacitor C1 (node ​​N1) is approximately GND, the charging current to the capacitor C1 by the PMOS transistor M3 from the state supply is started. This corresponds to the state of the timing A in the waveform diagram of FIG. 2, since the drain current I3 of the PMOS transistor M3 is a constant current as described above, the potential of the terminal of the timing A subsequent capacitor C1 (node ​​N1) is 2 so that increases linearly as described in (a). Here, "rises linearly" means that the rise time between the predetermined potential is substantially constant.

On the other hand, in the capacitor C2 side, NMOS transistor M6 is transited to the ON state, short circuit between both terminals of the capacitor C2, the capacitor C2 is discharged. Potential of this the terminal of the drain current I4 capacitor C2 has been charged by the PMOS transistor M4 just before (the node N2) is to be lowered toward the GND (0V) as shown in the timing A later view 2 (b) become. Then, in the capacitor C2 side, until the output of at least the comparator CMP1 is inverted to High level, the inverted output terminal QB of the logic circuit L1 are output High level, whereby is maintained the on state of the NMOS transistor M6 , the potential of the terminal of the capacitor C2 (node ​​N2) is fixed to approximately GND.

(B) timing B ~ timing A '
Then, when the potential of the terminal of the capacitor C1 (node N1) reaches the comparison reference voltage (V R), the output of the comparator CMP1 as timing B in FIG. 2 is inverted to High level, the logic circuit L1 receives it output terminal Q is also inverted to High level. Further, NMOS transistor M5 is shifted from the OFF state to the ON state by receiving it, thereby short-circuiting between both terminals of the capacitor C1, the potential of the discharge has been the terminal (node ​​N1) is toward the GND (0V) rapidly decreases, the comparator CMP1 outputs returns to Low level. Here, as described in FIG. 2 (a), the output of the output and the logic circuit L1 of the comparator CMP1 from reaching the terminal of the capacitor C1 voltage comparison reference voltage (node N1) (V R) is reversed By the time, it requires a certain finite delay time (td1). However, generally the response of the configured logic circuit L1 in a CMOS logic gate is sufficiently faster than the response of the comparator CMP1, therefore most of the delay time (td1) will be occupied by the response time of the comparator CMP1.

On the other hand, in the capacitor C2 side, at timing B, the output of the comparator CMP1 is inverted to High level, Invert the output terminal Q is High level of the logic circuit L1, the inverted output terminal QB is the Low level since the inverted output inverted. Thus the NMOS transistor M6 is transited to the off state, the charging of the capacitor C2 is started by the drain current I4 of the PMOS transistor M4 simultaneously. Since the drain current I4 of the PMOS transistor M4 is constant current, the potential of the terminal (node ​​N2) after timing B capacitor C2 will also rises linearly.

'When the potential of the subsequent eventually capacitor C2 terminal (node N2) reaches the comparison reference voltage (V R), the timing A in FIG. 2' (c) Timing A output of the comparator CMP2 as is inverted to High level, it to Low level output terminal Q of the logic circuit L1 receives the inverted output terminal QB is inverted respectively to the High level. Further, NMOS transistors M6 changes from the OFF state to the ON state by receiving it, thereby short-circuiting between both terminals of the capacitor C2, the potential of the discharge has been the terminal (node ​​N2) is toward the GND (0V) rapidly decreases, the comparator CMP2 outputs returns to Low level. Here, the comparator CMP2 is the same circuit configuration as the comparator CMP1 is taken. Further, it is assumed that the PMOS transistors constants like the drain current I3, I4 of the PMOS transistor M3 and the PMOS transistor M4 is the same current is set. That way, before the output of the output and the logic circuit L1 of the comparator CMP2 from reaching the potential comparison reference voltage terminal of the capacitor C2 (node N2) (V R) is reversed, the same delay and the comparator CMP1 side it takes time (td2).

On the other hand, in the timing A ', in the capacitor C1 side, the NMOS transistor M5 is changed to the off state receives the inversion of the Low level of the output terminal Q of the logic circuit L1, again by the drain current I3 of the PMOS transistor M3 capacitor charging of C1 is started. Its state is equivalent to the state of the timing A, since the short-circuiting of the charging the capacitor C2 of the capacitor C1 as described above, and that the charging of the short-circuiting the capacitor C2 of the capacitor C1, the operation is repeated alternately Become.

In the present embodiment, by taking out the oscillation output from the output terminal Q of the logic circuit L1, the oscillation period (T) from the comparator CMP1 output inversion of the capacitor C1 side to the next comparator CMP1 output inversion, or a capacitor C2 the one corresponding to the period of from the side of the comparator CMP2 outputs reversed until the next comparator CMP2 output inversion. And FIG. 2 (a), the as (b), the charging period of the charging period (Tc2) + a half cycle of oscillation period (T) by the delay time (td2), also the capacitor C1 of the capacitor C2 (Tc1) + forms the remaining half cycle by the delay time (td1), the NMOS transistor M5, the capacitor C1 by NMOS transistors M6, discharge time due to a short circuit of the capacitor C2 is not affecting the oscillation period (T). Further, the same value the capacitance of capacitors C1 and C2, also to set the PMOS transistor M3 and the PMOS transistor M4 to the same constant, and if those comparators CMP1 and CMP2 is composed of a circuit similar to a capacitor charging period of the charging period (Tc1) and the capacitor C2 of the C1 (Tc2) becomes approximately equal, and the output inverted involved delay time of the comparator CMP1 (td1) and the output inverted involved delay time of the comparator CMP2 (td2) is also substantially equal. Therefore the charging period of the capacitor C2 to form a half cycle of oscillation period (T) (Tc2) + delay time (td2), charging period (Tc1) of the capacitor C1 + delay time (td1) to a time approximately equal and can.

Here, the delay time td (= td1 = td2), capacitor C1 (and the capacitor C2) C the capacitance value of the comparison reference voltage (V R) to the charging time (charging period) T C (= Tc1 = Tc2 ) and putting,
T C = C × V R / I 3 ··· (4)
Expressed as, further the above formula (2), Equation (3) by substituting the above equation (4) T C = C × (α × V REF × R 2 / R 1) / (β × V REF / R 1)
= (Α / β) × C × R 2 ··· (5)
Obtained. Therefore, the oscillation period (T) is,
T = 2 × (T C + td)
= 2 × {(α / β ) × C × R 2 + td} ··· (6)
It is expressed as, a form that does not depend on the reference voltage input terminal VREF of the voltage (V REF).

As described above, according to this embodiment, in the oscillation circuit using a charging time constant of the capacitor, the time component involved in the discharge can be prevented from affecting the oscillation period, even at relatively high frequency region can suppress the fluctuation of the oscillation period for the parameter variations such as temperature variations, can be obtained advantage oscillation circuit on Assurance of oscillation frequency accuracy.

Further, by the control signal for charging and discharging are alternately two capacitors and an oscillation output can be obtained oscillation pulses of approximately 50% duty (duty). Here, the duty of the oscillation pulses (duty), refers to the ratio of the High level period of the oscillating pulse for the oscillation period (T).

Further, utilized as shown in equation (6), since the oscillation period in a form that is independent of the voltage of the reference voltage input terminal VREF is obtained, for example, some reference voltage output such as a band gap circuit configured on the same semiconductor substrate even when, even if there is a variation due to variations and temperature in the reference voltage output, it is possible to obtain a suitable oscillation circuit to ensure the accuracy of the oscillation frequency it is possible to cancel the effect.

<Modification 1>
In Modification 1, an example of an oscillator circuit and further it can adjust the setting of the oscillation frequency.
Figure 3 is a circuit diagram showing a configuration of an oscillation circuit according to a first modification. Oscillator circuit according to the modification 1 10B is obtained by replacing the reference voltage generating circuit 2 and the constant current generation circuit 1 of the oscillation circuit 10A according to the first embodiment to the bias circuit 3. That is, the oscillation circuit core of the oscillation circuit 10B has the same configuration as the oscillator circuit core portion OCS1 of the oscillation circuit 10A. However, a bias output terminal G0 of the gate terminals of the PMOS transistor M3, the PMOS transistor M4 is connected, the output terminal VR delivering a comparison reference voltage VR are all provided by the bias circuit 3.

Bias circuit 3 includes a ladder resistor RL2 and the PMOS transistor M7 and the operational amplifier A2 and the analog switch circuit 4 and the decoder circuit 5, a. Bias circuit 3 has a function of a constant current generating circuit and the reference voltage generating circuit. Ladder resistor RL2 and the analog switch circuit 4 and the decoder circuit 5 constitute a trimming circuit for adjusting the reference voltage value. That is, the bias circuit 3 has a trimming function of the reference voltage. Ladder resistor RL2 is a unit resistor as well as a plurality of series-connected connecting one end of the unit resistance lowermost to GND, and configured to retrieve the divided output from any connection points of the unit resistors. In the PMOS transistor M7, the drain terminal to the uppermost end of the unit resistance of the ladder resistor RL2, the source terminal to the power supply terminal VCC, respectively connected. In the operational amplifier A2, the inverting input terminal (-) to the reference voltage input terminal VREF, the resistance value viewed from the GND be any divided output of the ladder resistor RL2 its non-inverting input terminal (+) is R 3 to the connection point (node ​​N5), the output terminal to the gate terminal of the PMOS transistor M7, is connected. In the bias circuit 3, and a bias output terminal G0 of the connection point of the gate terminal of the output terminal and the PMOS transistor M7 of the operational amplifier A2. The analog switch circuit 4 sends out the divided output of the ladder resistor RL2 to selectively output terminal VR. Decoder circuit 5, a frequency trimming signal input terminals T1 ~ Tn of n bits, and controls the switches on and off the analog switch circuit 4 in response to the input signal of the frequency trimming signal input terminals T1 ~ Tn.

(Operation)
Hereinafter, an operation of the first modification.
The voltage at the non-inverting input (+) of the operational amplifier A2 has an inverting input (-) reference voltages applied voltage terminal VREF to be connected to a feedback control be equal to, thus the current value of the current I5 that flows through the PMOS transistor M7 I When 5,
I 5 = V REF / R 3 ··· (7)
Denoted. Here, the V REF applied voltage of the reference voltage terminal VREF, R 3 is the resistance from the GND of the ladder resistor to the non-inverting input of the operational amplifier A2 (+) connection point (node N5).

Current I5 As is apparent from equation (7), like the current I1 of the first embodiment, the voltage applied to the power supply terminal VCC is a constant current which is independent.

Further to the output terminal VR, one of the switches of the analog switch circuit 4 is selectively turned on by the input signal of the frequency trimming signal input terminals T1 ~ Tn, min ladder resistor RL2 to the selected switch is connected pressure output is sent. Voltage delivered to the output terminal VR includes a comparator CMP1, becomes a comparison reference voltage of the comparator CMP2, a capacitor C1, determines the charging time of the capacitor C2 (T C). Now the ladder resistor RL2 GND R 4 the resistance to selection switch connection points of the analog switch circuit 4 from the, voltage V R of the output terminal VR, the current value of the current I5 When I 5,
V R = I 5 × R 4 = V REF × R 4 / R 3 ··· (8)
Denoted.

The oscillating operation of this modification, similarly to Example 1, the PMOS transistor M3, a capacitor C1 by the PMOS transistor M4, and utilizes the charging time of the capacitor C2, the operation outline is shown in the waveform diagram of FIG. 2 is the same as the stuff.

The charging time of the capacitor C1 (T C) but is expressed by Equation (4), equation (7) to the equation (4), by substituting Equation (8),
T C = C × V R / I 3 = C × V R / (γ × I 5)
= C × (V REF × R 4 / R 3) / (γ × V REF / R 3)
= (1 / γ) × C × R 4 ··· (9)
Obtained. Here γ represents the mirror ratio of the PMOS transistor M7 and a PMOS transistor M3. Further oscillation period (T) includes a comparator CMP1, when the response delay time of the comparator CMP2 and td,
T = 2 × (T C + td)
= 2 × {(1 / γ ) × C × R 4 + td} ··· (10)
Next, resulting in a form that is independent of the voltage (V REF) likewise the reference voltage input terminal VREF as in Example 1.

Here, by switching the selection switch of the analog switch circuit 4 by the input signal of the frequency trimming input signal terminal T1 ~ Tn becomes the adjusting the resistance value R 4 in the above equation (10), whereby the oscillation frequency adjustment is possible.

Thus, like the case of mounting an oscillator circuit on a semiconductor substrate, the capacitance value of the capacitor was determined in the design stage, and when such resistance is formed on a semiconductor substrate, the expected value oscillation frequency variations occur in even deviated, adjusted by trimming the input signal can be corrected.

According to this modification, in addition to the effects of Embodiment 1, it is possible to obtain an oscillation circuit which enables adjustment of the oscillation frequency.

The function related to the frequency trimming input signal terminal T1 ~ Tn shown in this embodiment is not limited to the configuration of this embodiment, for example, provided that the comparison reference voltage generating circuit 2 in Example 1 of FIG. 1 it is also possible. In that case, it may be configured to resistor R2 in the form of a ladder resistor.

<Modification 2>
Figure 4 is a diagram showing a configuration of a bias circuit according to a second modification. Also for the constitution of the bias circuit 3, is not limited to the configuration shown in FIG. 3, it may be configured for example as shown in FIG.

Vice circuit 3A according to the second modification includes a NMOS transistor M30 and PMOS transistor M31 and PMOS transistor M32 and the ladder resistor RL2 and the analog switch circuit 4 and the decoder circuit 5 and the operational amplifier A30. In NMOS transistor M30, and its source terminal to GND, and its drain terminal to the drain terminal of the PMOS transistor M31, the gate terminal to the output of the operational amplifier A30, it is connected. In the PMOS transistor M31, its source terminal to the power supply terminal VCC, its drain terminal to the drain terminal of the NMOS transistor M30, respectively connected, a short circuit connecting the gate terminal to the drain terminal. In the PMOS transistor M32, its source terminal to the power supply terminal VCC, its gate terminal to the gate terminal of the PMOS transistor M31, connected respectively, constituting the PMOS transistor M31 and the current mirror. In the ladder resistor RL2, one end with a unit resistance of the uppermost end to a plurality of series-connected unit resistor to the drain terminal of the PMOS transistor M32, connected to one end of the unit resistance of the lowermost to GND, and any connection of the unit resistors It is configured to retrieve the divided output from the point. Analog switch circuit 4 sends out the divided output of the ladder resistor to selectively output terminal VR. Decoder circuit 5, a frequency trimming signal input terminals T1 ~ Tn of n bits, and controls the switches on and off the analog switch circuit 4 in response to the input signal of the frequency trimming signal input terminals T1 ~ Tn. In the operational amplifier A30, the non-inverting input terminal (+) to the reference voltage input terminal VREF, the inverting input terminal (-) of the resistance as seen from the GND be any divided output of the ladder resistor is R 3 connected point (node ​​N5), respectively connecting the output terminal to the gate terminal of the NMOS transistor M30. Inverting input of the operational amplifier A30 (-) voltage, so it is feedback controlled so that the applied voltage of the reference voltage terminal VREF to be connected to non-inverting input (+) and is equal, the current flowing to the ladder resistor RL2 and the PMOS transistor M32 is , becomes equal to I 5 in the formula (7). Thus the voltage of the bias output terminal G0 is set to the identification number of the PMOS transistor M7 of the PMOS transistor M32 in FIG. 3 becomes equal to that in the bias circuit 3. That is, the bias circuit 3A has the same function as the bias circuit 3, it is possible replacement. Operational amplifier A30 is operating between the potential and the GND of the power supply terminal VCC.

Configuration of the bias circuit 3A, the voltage applied to the reference voltage terminal VREF is the case such that a relatively low voltage such as about 1.2V typical bandgap voltage, the configuration of the operational amplifier A30, the common mode input the use of differential pairs by PMOS transistors for voltage range ensuring contemplated. The case where the operational amplifier A30 by stage amplifier including the PMOS transistor differential pair, the output voltage range is limited to a certain range from the GND potential can not shake the output voltage to the supply voltage. Therefore it is not possible to directly control the gate terminal of the PMOS transistor connected to the power supply terminal VCC and the source terminal as the PMOS transistor M7 of the bias circuit 3, configured through the NMOS transistor M30 as the bias circuit 3A is suitable there.

Note that the configuration of the bias circuit 3A also only one configuration example of a bias circuit, but is not limited thereto.

Example 2 is the relatively high frequency region of several tens of MHz same as in Example 1, but further provide advantages oscillator to the oscillation frequency accuracy ensured.

Figure 5 is a circuit diagram showing a configuration of an oscillation circuit according to the second embodiment. 6 is a waveform diagram showing the operation of the oscillation circuit.

Oscillation circuit 10C according to the second embodiment includes a power supply terminal VD1, a constant current bias source IB0, an oscillation circuit core unit OSC2, a. Oscillator core portion OSC2 includes a PMOS transistor M16, the PMOS transistor M17, an NMOS transistor M18, a. In the PMOS transistor M16, its source terminal to the power supply terminal VD1, its drain terminal to the constant current bias source IB0, respectively connected, a short circuit connecting the gate terminal and the drain terminal. In the PMOS transistor M17, its source terminal to the power supply terminal VD1, its gate terminal to the gate terminal of the PMOS transistor M16, connected respectively. In NMOS transistor M18, and its drain terminal to the drain terminal of the PMOS transistor M17, its source terminal to GND, and each connected to a short circuit connecting the gate terminal to the drain terminal. The oscillation circuit core unit OSC2 includes a PMOS transistor M8, M9, and NMOS transistors M14, M15, and capacitors C1, C2, C3, C4, and. In the PMOS transistor M8, the drain terminal to the capacitor C1, the source terminal to the power supply terminal VD1, respectively connecting the gate terminal to the gate terminal of the PMOS transistor M16. In the PMOS transistor M9, the drain terminal to the capacitor C2, the source terminal to the power supply terminal VD1, its gate terminal to the gate terminal of the PMOS transistor M16, connected respectively. NMOS transistors M14 fraud and mitigating risk its drain terminal to the capacitor C3, the source terminal to GND, and its gate terminal to the gate terminal of the NMOS transistor M18, connected respectively. In NMOS transistor M15, and its drain terminal to the capacitor C4, the source terminal to GND, and its gate terminal to the gate terminal of the NMOS transistor M18, connected respectively.

Furthermore, a oscillating circuit core unit OSC2 includes NMOS transistors M10, M11, the PMOS transistor M12, M13, and the logic circuit L1, a comparator CMP1, comparator CMP2, a. In NMOS transistor M10, and its drain terminal to the drain terminal of the PMOS transistor M8, the source terminal to GND, and respectively connecting a gate terminal to the output terminal Q of the logic circuit L1. In NMOS transistors M11, the drain terminal to the drain terminal of the PMOS transistor M9, its source terminal to GND, and respectively connecting a gate terminal to the inverting output terminal QB of the logic circuit L1. In the PMOS transistor M12, the drain terminal to the drain terminal of the NMOS transistor M14, and its source terminal to the power supply terminal VD1, respectively connecting the gate terminal to the inverting output terminal QB of the logic circuit L1. PMOS transistor M13 fraud and mitigating risk its drain terminal to the drain terminal of the NMOS transistor M15, and its source terminal to the power supply terminal VD1, respectively connecting the gate terminal to the output terminal Q of the logic circuit L1. The comparator CMP1, the non-inverting input terminal (+) to the connection point between the drain terminal and the capacitor C1 of the PMOS transistor M8 (node ​​N1), its inverting input terminal (-) and the drain terminal and the capacitor C3 of the NMOS transistor M14 a connection point (node ​​N3), its output terminal to the set signal input terminal S of the logic circuit L1, is connected. The comparator CMP2, its non-inverting input terminal (+) to the connection point between the drain terminal and the capacitor C2 of the PMOS transistor M9 (node ​​N2), its inverting input terminal (-) and the drain terminal and the capacitor C4 of the NMOS transistor M15 a connection point (node ​​N4), respectively connecting the output terminal to the reset signal input terminal R of the logic circuit L1. Connecting the output terminal Q of the logic circuit L1 to the oscillation output terminal OUT. It is also possible to take out the oscillation output from the output terminal QB of the logic circuit L1. Here, the first control signal the signal output from the output terminal Q, a signal output from the output terminal QB of the second control signal.

Here, the logic circuit L1 is assumed to have the same functions as those described in Example 1. Further, in FIG. 5, one end of each capacitor is connected to GND, but it is not limited thereto, but may if voltage source such that a constant potential is maintained.

(Operation)
It will be described below with reference to FIG. 6, the operation of this embodiment. 6 (a) shows the potential of the capacitor C1, C3 of the terminal (node ​​N1, N3), the potential of FIG. (B) The terminal of the capacitor C2, C4 (node ​​N2, N4), FIG. (C) a comparator CMP1 output voltage, FIG. (d) shows the output voltage of the comparator CMP2, the voltage of FIG. (e) an output terminal Q of the logic circuit L1 (oscillation output terminal OUT), and FIG. (f) is the inverted output of the logic circuit L1 It shows the voltage of the terminal QB.

First constant voltage (V D1) is assumed to be applied to the power supply terminal VD1. The current I6 flowing through the PMOS transistor M16 by a constant current bias source IB0 is assumed to be a constant current. Further, the current flowing in each of the PMOS transistors M8, PMOS transistors M9 in PMOS transistor M16 and the current mirror relationship I8, I9 is ​​assumed to be a constant current. Current I7 flowing through the PMOS transistor M17 in the PMOS transistor M16 and the current mirror relationship is assumed to be a constant current. This is a drain current of the NMOS transistor M18, is further transmitted to the NMOS transistor M14, NMOS transistor M15 in the NMOS transistor M18 and the current mirror relationship, the current flowing through the respective I10, I11 is assumed to be a constant current.

Further, NMOS transistors M10 and NMOS transistors M11 has a sufficiently large current driving capability than the current I8, I9 of the PMOS transistors M8 and PMOS transistor M9, the capacitor C1 when they are in the ON state shall the potential of the terminal (node ​​N1) and their terminals are short-circuited terminals (nodes N2) to the GND of the capacitor C2 (node ​​N1, N2) can be pulled down to approximately GND. For the PMOS transistor M12 and PMOS transistor M13, as compared to the current I10, I11 in the NMOS transistor M14, NMOS transistor M15 has a sufficiently large current driving capability, the terminal of the capacitor C3 when they are turned on and (node N1) and that can be pulled up to nearly constant voltage (V D1) the potential of a short circuit the terminals of the capacitor C4 (node N2) to the power supply terminal VD1 their terminal (node N2, N4).

For convenience of explanation, capacitors C1, C2, C3, C4 are set equal capacitance value C, also to those current I8, I9, I10, I11 also current mirror ratio such that the same current value setting is set to.

It will now be described oscillating operation.
(A) timing C ~ timing D
Now, the same time inverting output terminal QB when the output terminal Q is changed to the Low level of the logic circuit L1 at timing C has transitioned to the High level in FIG. NMOS transistor M10 is a short circuit of the capacitor C1 side this time, a transition to the OFF state by its gate terminal is shifted to the Low level, the PMOS transistor M12 is also High, the gate terminal is short circuit of a capacitor C3 side again it will transition to the oFF state by a transition to the level. In the just before reaching the timing C, since the NMOS transistor M10 and PMOS transistor M12 are both in the ON state, the potential of the terminal of the capacitor C1 (node ​​N1) to approximately GND (0V), also terminal potential of the capacitor C3 It is fixed to substantially V D1.

Thus from the point of time C, the capacitor C1 becomes the charging by the current I8 is started, the terminal voltage rises linearly towards the V D1. On the other hand, in the capacitor C3 is started discharge by current I10 from that point, the potential of the terminal (node ​​N1) linearly decreases toward the GND (0V). Here, the "linearly decreases" means that reduction time between predetermined potential is substantially constant. Incidentally, the direction of the bias applied to increase potential difference between both terminals of the capacitor is charging, also the discharge merely expresses the bias in the direction of reduction potential difference between both terminals of the capacitor, the current and does not the relationship between the charging and discharging operation of the capacitors is limited to the description of the present embodiment. For example, if it is connected to the one end rather than the power supply terminal VD1 side GND of the capacitor C1, it comes to its terminal voltage capacitor C1 by the current I8 is being "discharged" rises linearly towards the V D1 .

On the other hand, the capacitor C2, the capacitor C4 side, NMOS transistor M11 is a short circuit of the capacitor C2, its gate terminal transitions to the High level to the ON state and the PMOS transistor M13 is a short circuit of the capacitor C4, its gate terminal is also a transition to the oN state transitions to the Low level. Thus after the timing C, the terminal of the capacitor C2 (node N2) is pulled down to GND, the terminal (node N4) of the capacitor C4 is pulled up to V D1.

After timing C in FIG. 6, the potential of the terminal of the capacitor C1 (node N1) continued to rise linearly toward the GND (0V) to V D1, GND from the potential V D1 terminal of the capacitor C3 (node N3) since towards (0V) continues to linearly decrease, the potential of the terminal of the capacitor C1 (node ​​N1), the potential of the terminal (node ​​N3) of the capacitor C3 will either intersect. If current I10 is the discharge current of the current I8 and the capacitor C3 is a charging current of the capacitor C1 are the same current value, the potential of the potential and the capacitor C3 pin terminal of the capacitor C1 (node ​​N1) (node ​​N3) There because the time to transition to a half voltage of V D1 equal, the potential of the terminal of the capacitor C1 (node N1), the potential of the terminal of the capacitor C3 (node N3), each with half the voltage of V D1 It will intersect at the point where the reached. Until the potential of the potential and the capacitor C3 pin terminal of the capacitor C1 (node ​​N1) (node ​​N3) intersects the non-inverting input terminal of the comparator CMP1 (+) side is the inverting input terminal (-) to the lower potential than the side some reason, the comparator CMP1 outputs are outputs Low level. Then from the time when the potential of the capacitor C3 pin terminal of the capacitor C1 (node ​​N1) (node ​​N3) becomes the time of the crossing, i.e. the same potential, the comparator via a response delay time of the comparator CMP1 (td1 ') CMP1 the output is inverted to High level. This corresponds to the state of the timing D in FIG.

Note that although the capacitor C2 and capacitor C4 side until timing D by the short circuit of the NMOS transistors M11 and PMOS transistor M13, the terminals (nodes N2, N4) potential is fixed almost GND and V D1.

(B) Timing D ~ timing C '
At the timing D, the output terminal Q of the logic circuit L1 receives the High level inversion of the comparator CMP1 outputs a transition to the High level, the inverted output terminal QB is shifted to the Low level. Thus transitions NMOS transistor M10 and PMOS transistor M12 to the ON state, the terminal (node ​​N1) of the capacitor C1 is pulled down to GND, the capacitor C3 terminal (node ​​N3) is pulled up to VD1. Thereby, the potential of the terminal of the capacitor C3 (node ​​N3) is rising rapidly with respect to the potential of the terminal of the capacitor C1 (node ​​N1), the comparator CMP1 outputs returns to Low level. And since that time the NMOS transistor M11 and PMOS transistor M13 is changed to the OFF state, the capacitor C2 is started charging by currents I9, the potential of the terminal of the capacitor C2 (node N2) toward the V D1 from GND (0V) rises linearly Te. At the same time, the capacitor C4 is started discharge by current I11, the potential of the terminal of the capacitor C4 (node N4) linearly decreases toward the V D1 to GND (0V). If current I9 and the current I11 is the same current value, the timing C after the capacitor C1, as in the case of the capacitor C3 side terminal of the capacitor C2 and the capacitor C4 at half voltage V D1 (node N2, N4) so that the potential cross.

Potential cross potential and the terminal of the capacitor C4 of the terminal of the capacitor C2 (node ​​N2) (Bruno N4), i.e. when it reaches the same potential, the comparator CMP2 is that, as with the comparator CMP1, the response delay time (td2 ') through the inverting its output to the High level. This corresponds to the timing C 'in FIG.

(C) the timing C '
In this timing C ', receives the inverted to High level of the comparator CMP2 outputs to the inverting output terminal QB side is the High level of the logic circuit L1, the transition to the output terminal Q side is Low level, NMOS transistor M10 and PMOS transistor M12 is turned off transitions to the state, the discharge of the charge and capacitor C3 of the capacitor C1 is started again by the current I8 and the current I10. The transition at the same time NMOS transistor M11 and PMOS transistor M13 to the ON state, the capacitor C2 terminal (node N2) is pulled down to GND, and the capacitor C4 terminal (node N4) is pulled up to V D1, whereby the capacitor C2 pin ( node N2 potential terminal of the capacitor C4 (node ​​N4) with respect to the potential of) the rising rapidly, the comparator CMP2 outputs returns to Low level. This state is equivalent to the state of the timing C described earlier, since, so that the operation described above is repeated.

Note that although the oscillation output terminal OUT, and taken out from the output terminal Q of the logic circuit L1, the comparator CMP1 outputs (or comparator CMP2 outputs) period oscillation period of up to inversion (T from inverted to High level to the next High level ) to be. The High period and Low period of the output terminal Q, the time and about the charging / discharging of the capacitor C1 / capacitor C3, respectively, from being formed by the time and the related charging / discharging of the capacitor C2 / capacitor C4, theoretically equivalent be a time width, Therefore, it is possible to obtain an oscillation pulse of approximately 50% duty.

Here, if those comparators CMP1 and CMP2 is composed of a circuit similar to the response delay time of the comparator CMP1 (td1 ') and the response delay time of the comparator CMP2 (td2') becomes substantially equal. Therefore, the td '= td1' = td2 '. Comparator CMP1, looking at the response delay time of the comparator CMP2 (td '), in order to each comparator output is inverted to High level, the non-inverting input terminal (+) terminal potential of the side-inverting input terminal (-) side of the it is necessary to exceed the terminal voltage and the response delay time until the output inversion as their potential is large will be shortened. In the present embodiment, the potential of the terminal of the capacitor C1 in the raised by the charging (node ​​N1) (or the potential of the terminal (node ​​N2) of the capacitor C2), the capacitor C3 during the descent by the discharge terminal (node ​​N3) because you are configured to compare the potential (or potential of the terminal of the capacitor C4 (node N4)), as compared to when compared with a constant reference voltage as in example 1 (V R), more the input potential difference can be expanded at an early stage, it is possible to shorten the response delay time (td '). Thus Example 1, expression for the oscillation period described in the modification 1 (T) (6), td is a component about the response delay time of the comparator in the formula (10) is compressed, the comparator in the parameter variations such as temperature variations as variations in the response delay time of the occurred also, since it is possible to reduce the ratio of td in the oscillation period (T), it is possible to suppress the oscillation frequency variations than the first embodiment and the like.

According to this embodiment, since it is possible to shorten the response delay time of the comparator, it is possible to obtain the advantage oscillation circuit in achieving the oscillation frequency accuracy ensured.

Incidentally charge driver capacitors C1, C2, also the capacitor C3, PMOS transistor M8 constituting the respective constant current sources to C4 discharging drive, M9 and the NMOS transistors M14, M15 each capacitor terminals either (nodes N1, N2, N3, by a construction which is directly connected to N4), when one of the NMOS transistors M10, M11 and PMOS transistors M12, M13 constituting the short-circuit switch is turned on, the output current of the constant current source is in the oN state It will flow to bypass to short-circuit the switch side. Since this is a reactive current, but is preferable to originally blocked is advantageous in terms of current consumption, if tentatively adopted a structure for blocking this results in the following problems.

In example capacitor C1 parts, in order to cut off the constant current output I8 of the PMOS transistor M8, a cutoff switch provided between the terminal of the drain terminal and the capacitor C1 of the PMOS transistor M8 (node ​​N1), NMOS transistor is short-circuit switch M10 assume the blocking switch to the on state a configuration for exclusive control so that the oFF state. This causes the PMOS transistor provided as the blocking switch, easily can be realized by directly connecting its gate terminal to the gate terminal of the NMOS transistor M10.

In the above configuration, when the NMOS transistor M10 is pulled down terminal of the capacitor C1 in the ON state (node ​​N1) to GND, the current path of the interrupter switch is a PMOS transistor M8 and a transition to the OFF state to the NMOS transistor M10 side It will be shut off. At this time PMOS transistor M8 is always in the ON state, the connection point between the cut-off switch, i.e. the potential of the drain terminal of the PMOS transistor M8 is elevated to the power supply voltage (V D1), which is the drain of the PMOS transistor M8 parasitic capacitance components involved in the terminal means that is charged to the power supply voltage (V D1).

Then when trying to start a charging operation of the capacitor C1, the NMOS transistor M10 to the OFF state, but at the same time will transition each said shut-off switch to the ON state, is the moment, electric charges charged in the parasitic capacitance is distributed to the capacitor C1 side (so-called charge sharing occurs) would varying the potential of the terminal of the capacitor C1 (node ​​N1). Thus detection timing by the comparator CMP1 is changed, which leads to variation in the oscillation period.

Therefore also in this embodiment and other embodiments, a configuration that directly connects the constant current source for each capacitor, adopts a configuration that can suppress the oscillation frequency variation due to the charge sharing.

In addition, the present embodiment, as described above, the charging driving side capacitor that is driven simultaneously with each other, by comparing respective terminal voltages of the discharge driving side capacitor, when compared with a constant reference voltage (V R) compared to, so that twice the rate of change is obtained for the input potential difference of the comparator as long as the same charge and discharge time constant setting. Whereby the response delay time until the comparator output inversion as described above is reduced, leading to oscillation frequency fluctuation suppressing effect.

Here, that in principle be steep charging (or discharging) the voltage change during the operation of the capacitor even when compared with a constant reference voltage (V R) obtained by enlarging the input potential difference of the comparator early it is likely to obtain the same effect as this embodiment. However, if the case, the comparator detects the timing period to obtain the same oscillation period must be the same, after doubling capacitor driving current, charge (or discharge) to double the voltage amplitude itself at the time of driving or the comparison reference voltage (V R) or to double the voltage change width of the comparators detects the timing cycle as the voltage of the power supply terminals VD1 (or GND voltage), the choice of two ways.

However, to simply double the voltage amplitude itself during charging (or discharging) driving, it is difficult in reality and the like the voltage limitation of the power supply terminal VD1. In the case where the comparison reference voltage (V R) the voltage applied to the power supply terminal VD1 (or GND voltage), after the charging (or discharging) the voltage reaches approximately the same potential as the reference voltage (V R), further the potential difference can not be enlarged, thus the input potential difference of the comparator would not provide sufficient potential difference output inversion. The input voltage range capable of maintaining the sensitivity of the comparator must also be taken into consideration.

Therefore, in the structure compared to a constant reference voltage (V R), to obtain the same effect as the present embodiment it is difficult.

<Modification 3>
Modification 3, to allow the adjustment of the oscillation frequency, and provides a more dominant oscillation circuit the oscillation frequency accuracy ensured.

Figure 7 is a circuit diagram showing a configuration of an oscillation circuit according to a third modification.

Oscillator core portion OSC3 oscillation circuit 10D according to Modification 3, except for the logic circuits L2 and comparator CMP3 and the comparator CMP4, is the same as the configuration of the oscillator circuit core portion OSC2 of the oscillation circuit 10C of the second embodiment. The oscillation circuit 10D includes a bias circuit 6. An oscillation circuit 10D and an oscillation circuit 10C will be described below for the different parts.
The bias circuit 6 includes a power supply terminal VCC and the reference voltage input terminal VREF, and an output terminal IB, VD1, VD2. The comparator CMP3, its inverting input terminal (-) to the connection point between the drain terminal and the capacitor C1 of the PMOS transistor M8 (node ​​N1), its non-inverting input terminal (+) and the drain terminal and the capacitor C3 of the NMOS transistor M14 a connection point (node ​​N3), an output terminal to the set signal input terminal S of the logic circuit L2, respectively connected. The comparator CMP4, its inverting input terminal (-) to the connection point between the drain terminal and the capacitor C2 of the PMOS transistor M9 (node ​​N2), its non-inverting input terminal (+) and the drain terminal and the capacitor C4 of the NMOS transistor M15 a connection point (node ​​N4), its output terminal to the reset signal input terminal R of the logic circuit L2, respectively connected. Connecting the output terminal Q of the logic circuit L2 to the oscillation output terminal OUT. It is also possible to take out the oscillation output from the output terminal QB of the logic circuit L2.

The bias circuit 6 includes a ladder resistor RL4, and PMOS transistor M7, an operational amplifier A2, an analog switch circuit 4, a decoder circuit 5, a PMOS transistor M19, an NMOS transistor M20, an NMOS transistor M21, and an operational amplifier A3, PMOS It includes a transistor M22, an operational amplifier A4, a PMOS transistor M23, the. The bias circuit 6, similarly to the bias circuit 3 has a function of a constant current generating circuit and the reference voltage generating circuit. Ladder resistor RL4 and the analog switch circuit 4 and the decoder circuit 5 constitute a trimming circuit for adjusting the reference voltage value. That is, the bias circuit 6 has a trimming function of the reference voltage. In the ladder resistor RL4, the unit resistors connected to GND one end of the unit resistance of the lowermost as well as a plurality of series-connected, be configured to take out the divided output from any connection points of the unit resistors. In the PMOS transistor M7, the drain terminal to the uppermost end of the unit resistance of the ladder resistor RL4 (node ​​N8), the source terminal to the power supply terminal VCC, respectively connected. In the operational amplifier A2, the inverting input terminal (-) to the reference voltage input terminal VREF, the resistance value viewed from the GND be any divided output of the ladder resistor RL4 its non-inverting input terminal (+) is R 5 to the connection point (node ​​N6), respectively connecting the output terminal to the gate terminal of the PMOS transistor M7. Operational amplifier A2, A3, A4 is operating between the potential and the GND of the power supply terminal VCC. Analog switch circuit 4 outputs the divided output of the ladder resistor RL4 selectively. Decoder circuit 5, a frequency trimming signal input terminals T1 ~ Tn of n bits, and controls the switches on and off in the analog switch circuit 4 in response to the input signal of the frequency trimming signal input terminals T1 ~ Tn . In the PMOS transistor M19, its source terminal to the power supply terminal VCC, its gate terminal to the output terminal of the operational amplifier A2, respectively connected, a relationship of the PMOS transistor M7 and a current mirror. In NMOS transistor M20, and its drain terminal to the drain terminal of the PMOS transistor M19, its source terminal to GND, and each connected, a short circuit connecting the gate terminal to the drain terminal. In NMOS transistor M21, to the drain terminal of the output terminal IB, the source terminal to GND, and its gate terminal to the gate terminal of the NMOS transistor M20, respectively connected, the relationship of the NMOS transistor M20 and a current mirror. In the operational amplifier A3, an inverting input terminal (-) to the output of the analog switch circuit 4, the output terminal VD1 its non-inverting input terminal (+), respectively connected. In the PMOS transistor M22, its source terminal to the power supply terminal VCC, its drain terminal to the output terminal VD1, its gate terminal to the output terminal of the operational amplifier A3, respectively connected. In the operational amplifier A4, its inverting input terminal (-) to the connection point between the unit resistance of the uppermost end of the drain terminal and the ladder resistor RL4 of the PMOS transistor M7, the output terminal VD2 its non-inverting input terminal (+), respectively connected to. In the PMOS transistor M23, its source terminal to the power supply terminal VCC, its drain terminal to the output terminal VD2, the gate terminal to the output terminal of the operational amplifier A4, respectively connected.

The logic circuit L2 includes a NAND gate G1, the NAND gate G2, an inverter G3, an inverter G4, a. In the NAND gate G1, one of its input terminals to the set signal input terminal S, its output terminal to the input terminal of the inverter G3, respectively connected. In the NAND gate G2, one of its input terminals to the reset signal input terminal R, the other input terminal to the output terminal of the NAND gate G1, the output terminal to the other input terminal of the NAND gate G1, connected respectively . Inverter G4 is connected to the input terminal to the output terminal of the inverter G3, the output terminal of the inverter G3 and the inverting output terminal QB, and the output terminal of the inverter G4 and the output terminal Q. Thus the logic circuit L2 is the period from the input of the falling edge to the set signal input terminal S to a falling edge to the reset signal input terminal R is inputted performs signal output of High level to the output terminal Q. Further, the logic circuit L2 is the period from the input of the falling edge to the reset signal input terminal R to the falling edge to the set signal input terminal S is inputted performs Low level signal output to the output terminal Q . Further, the inverted output terminal QB polarity signal obtained by inverting the signal output from the output terminal Q is outputted. Here, the first control signal the signal output from the output terminal Q, a signal output from the output terminal QB of the second control signal.

In the oscillation circuit 10D, to connect the respective source terminals of the PMOS transistors M8, M9, M12, M13, M16, M17 the output terminal VD1 of the bias circuit 6, a comparator CMP3, CMP4, and a power supply of the logic circuit L2 is output It has a configuration that gives the terminal VD2. Thus providing the power two systems is not necessarily imperative, for its specific effects will be discussed within the following operation description.

Hereinafter, the operation of this embodiment will be described.
First, the operational amplifier A2, PMOS transistors M7 and ladder resistor RL4 in the bias circuit 6 further analog switch circuit 4, the configuration of the decoder circuit 5, is similar to the bias circuit 3 of the first modification shown in FIG. 3, PMOS transistor M7 current value of the drain current I12 of When I 12, by replacing the resistance R 3 of formula (7) R 5 I 12 = V REF / R 5 ··· (11)
It is expressed as, a constant current which does not also depend on the voltage of the power supply terminal VCC. Note that the their construction, it is of course possible to adopt a configuration of a bias circuit 3A according to the second modification of FIG. 4 in place of the configuration of the bias circuit 3 according to a first modification of FIG.

PMOS transistor M19 is in the PMOS transistor M7 and a current mirror relationship, the drain current I13 is given by the mirror ratio times the drain current I12. Moreover the drain current I13 becomes a drain current of the NMOS transistor M20, it is transmitted to the NMOS transistor M21 in the NMOS transistor M20 and a current mirror relationship. Now, if put PMOS transistor M7 and a PMOS transistor M19, and the overall mirror ratio of the NMOS transistor M20 and NMOS transistors M21 and [delta], the drain current of the NMOS transistor M21, that is, the current I6 flowing into the output terminal IB of a PMOS transistor M16 When the current value I 6 for,
I 6 = δ × I 12 = δ × V REF / R 5 ··· (12)
And it can be expressed.

On the other hand, the operational amplifier A3 and the PMOS transistor M22 constitutes a so-called voltage follower, noninverting by a feedback loop to the input terminal (+), the voltage of the output terminal VD1 (V D1) is the inverting input terminal of the operational amplifier A3 ( -) is feedback-controlled such that a voltage equal to the voltage of. Therefore, a voltage equal to the output voltage of the analog switch circuit 4 is sent to the output terminal VD1. Now, the resistance value of the GND of the ladder resistor RL4 to select switch connection points of the analog switch circuit 4 (node N6) and R 6, if the output voltage of the analog switch circuit 4 and V R,
V R (= V D1) = I 12 × R 6 = V REF × R 6 / R 5 ··· (13)
And it can be expressed. Therefore, the voltage of the output terminal VD1 (V D1) is, PMOS with capacitors C1 ~ capacitor C4 constant current source for charging and discharging drive, i.e. in a fixed relationship with the PMOS transistors M8, M9, and the current value of the NMOS transistor M14, M15 is a proportional current value of the current I6 of the transistor M16 (I 6). That is, Equation (12), the relationship between V D1 and I 6 from the equation (13),
V D1 = (1 / δ) × R 6 × I 6 ··· (14)
And it can be expressed.

Further, the operational amplifier A4 and the PMOS transistor M23 is similarly constitute a voltage follower, the output terminal VD2 inverting input terminal of the operational amplifier A4 (-) voltage is delivered. In Figure 7 the uppermost end of the ladder resistor RL4 is connected, if the resistance value to its uppermost end from GND and R 6 ', the voltage of the output terminal VD2 (V D2) is
V D2 = I 12 × R 6 '= V REF × R 6' / R 5 ··· (15)
And it can be expressed. Incidentally, R 6 in the formula (13) may vary according to the input signal of the frequency trimming signal input terminals T1 ~ Tn, ladder from the GND in the third modification of the R 6 'are 7 in the formula (15) It becomes resistance to the uppermost end of the resistor RL4, which is a fixed value. However, the invention is not limited thereto, may be configured using the resistance value to an arbitrary dividing point of the ladder resistor RL4.

In a state where the above-mentioned I 6 and V D1 is given, for charging and discharging operation of the capacitors C1 ~ capacitor C4, the same operation as the oscillation circuit 10C of the second embodiment shown in FIG. 6 (a) ~ (f) . However, the comparator CMP3, a comparator connected to the relationship between the terminals of the input terminals and each capacitor of the comparator CMP4 is in the oscillation circuit 10C of the second embodiment of FIG. 5 CMP1, since the connections of the comparator CMP2 is reversed, a comparator CMP3, each output of the comparator CMP4 is FIG. 6 (c), the a comparator CMP1, the inverted waveform of each output waveform of the comparator CMP2 in (d). FIG 6 (a), (b), (e), (f), (g), (h) shows the operation of the oscillation circuit 10D. Here, the voltage of FIG. (E) an output terminal Q of the logic circuit L2 (oscillation output terminal OUT), FIG. (F) is the voltage at the inverting output terminal QB of the logic circuit L2, FIG. (G) an oscillation circuit the output voltage of the comparator CMP3 of 10D, FIG (h) shows the output voltage of the comparator CMP4. That is, as shown in FIG. 6 (g), the output of the comparator CMP3 when the charge potential of the capacitor C1 exceeds the discharge potential of the capacitor C3 is inverted from High level to Low level, also in FIG. 6 (h) as shown, the output of the comparator CMP4 will be inverted from High level to Low level when the charge potential of the capacitor C2 exceeds the discharge potential of the capacitor C4. Time logic circuit L2 is also because of the configuration set signal input terminal S, a logic gate receiving a reset signal input terminal R NAND gates G1, G2, the comparator CMP3, the falling edge of the output of the comparator CMP4 is input in so that the output signal of the output terminal Q and the inverted output terminal QB is inverted.

Now, looking at the time corresponding to the timing D in FIG. 6, the potential of the terminal of the capacitor C4 (node ​​N4) is placed in a state of higher potential than the potential of the terminal of the capacitor C2 (node ​​N2), the output of the comparator CMP4 is in a state of High level. On the other hand, the comparator CMP3 side outputs inverted to Low level from the High level when the charge potential of the capacitor C1 exceeds the discharge potential of the capacitor C3, which is input to the set signal input terminal S of the logic circuit L2. In the logic circuit L2 is, NAND gate G1 for connecting one input terminal to the set signal input terminal S receives a Low level transition of the input terminal, shifts its output to the High level. Thus, none of the NAND gates G2-side input terminal becomes High level, to transition its output to Low level, both the input terminals of the instant NAND gate G1 becomes Low level. Further receiving the High level transition of NAND gate G1 output, the output terminal Q via the inverter G3, G4 are to High level, the inverted output terminal QB is shifted respectively to the Low level.

High level of the output terminal Q, subjected to Low level transition of the inverted output terminal QB, and a transition NMOS transistor M10 and PMOS transistor M12 to the on state, the terminals of the capacitor C1 (node ​​N1) is to GND, the capacitor C3 terminal (node N3) are short-circuited respectively to the power supply terminal VD1. Therefore, the potential of the terminal (node ​​N3) of the capacitor C3 immediately after the short-circuit operation becomes to exceed the potential of the terminal of the capacitor C1 (node ​​N1), the output of the comparator CMP3 is restored from the Low level to the High level. In this case the logic circuit L2, but will be set signal input terminal S is shifted to High level, the NAND gate the other input terminal of the G1 to undergo it, it has been maintained at the Low level by the NAND gate G2 outputs Therefore, NAND gate G1 output maintains the High level, the output terminal Q becomes on maintaining High level.

On the other hand, in the case the capacitor C2, capacitor C4 side, NMOS transistors M11 and PMOS transistors M13, transits to the OFF state, the charging of the capacitor C2, and a discharge of the capacitor C4 begins. And at the time corresponding to the timing C '(or timing C) in FIG. 6, when the charging potential of the capacitor C2 exceeds the discharge potential of the capacitor C4, the output of the comparator CMP4 is inverted from High level to Low level. Thus, the falling edge transition to Low level is inputted to the reset signal input terminal R of the logic circuit L2, NAND gate G2 outputs for receiving it is inverted from Low level to High level. NAND gate G1, by any of the set signal input terminal S and the NAND gate G2 output becomes High level, inverts the output from the High level to the Low level. Accordingly, the output terminal Q of the logic circuit L2 via the inverter G3, G4 is to the Low level, the inverted output terminal QB is changed respectively to the High level.

Low level of the output terminal Q, subjected to High level transition of the inverted output terminal QB, and a transition NMOS transistors M11, and the PMOS transistor M13 to the ON state, the GND terminal of the capacitor C2 (node ​​N2), the capacitor C4 pin ( shorting each node N4) to the power supply terminal VD1. Therefore, the potential of the terminal of the capacitor C4 (node ​​N4) immediately after the short-circuit operation becomes to exceed the potential of the terminal of the capacitor C2 (node ​​N2), the output of the comparator CMP4 returns from the Low level to the High level. In this case the logic circuit L2, although the reset signal input terminal R is that the transition to the High level, the NAND gate the other input terminal of G2 to receive it, is maintained in Low level by the NAND gate G1 outputs Therefore, NAND gate G2 output is maintained at the High level.

On the other hand, then the capacitor C1, the capacitor C3 side, NMOS transistors M10, and the PMOS transistor M12 is a transition to the OFF state, charging of the capacitor C1, and the discharge of the capacitor C3 is started again. The comparator CMP3 output is inverted from High level to Low level when the charge potential of the capacitor C1 exceeds the discharge potential of the capacitor C3, to again High level output terminal Q of the logic circuit L2, the inverting output terminal QB again Low each will be reversed to level.

Since, although to repeat the above operation, the output terminal Q of the logic circuit L2 maintains the High level state of the until the next falling edge in the reset signal input terminal R is input, also a reset signal input When the falling edge to the terminal R is inverted is input to the Low level, then the falling edge to the set signal input terminal S is to maintain the Low level state until the input. Thus the output terminal Q, so that the oscillation pulses to the charging and discharging time of the charge and discharge time and capacitors C2 and C4 of the capacitors C1 and C3 and a half period can be obtained.

Here, consider the charge and discharge time of the capacitor C1 and capacitor C3 or capacitor C2 and capacitor C4,. Now, the same value each capacitance of the capacitors C1, C2, C3, C4, the current I8, I9, I10, I11 is assumed that the MOS transistor constant is chosen such that the current value of the capacitor C1 'discharging period of the charging period / capacitor C4 and the capacitor C2 (Tc2 discharge period (Tc1)' charging period / capacitor C3) becomes substantially equal. For example, in charging and discharging operation of the capacitors C1 and C3, because is half the voltage of the power supply terminal VD1 is the potential is equal in both capacitor terminals (nodes N1, N3), the charge and discharge to reach the voltage When time T C and '(= Tc1' = Tc2 ' ),
T C '= C × (1/2 ) × V D1 / I 8
= C × (1/2) × V D1 / (ε × I 6) ··· (16)
Denoted. Here, C is the capacitor C1, C2, C3, capacitance value of C4, the voltage value of V D1 power supply terminal VD1, current value I 6 a current I6, the current value of I 8 is the current I8, also ε is PMOS transistor representing the M16 and the mirror ratio of the PMOS transistor M8. Incidentally, the total of from current I8, I9, I10, I11 is the same current value, the mirror ratio of the PMOS transistor M16 and PMOS transistor M9, until the NMOS transistor M14 and NMOS transistors M15, further through the PMOS transistor M16 and PMOS transistor M17 specific mirror ratio also assumed to be epsilon.

Formula to Formula (16) (12) and substituting equation (13),
T C '= C × (1/2 ) × (V REF × R 6 / R 5) / (ε × δ × V REF / R 5)
= {1 / (2 × ε × δ)} × C × R 6 ··· (17)
Denoted. For further oscillation period (T), the charge and discharge time as shown in FIG. 6 (T C ') to the comparator response delay time (td' from) plus becomes half period, the oscillation period (T) is T = 2 × (T C ' + td')
= 2 × {1 / (2 × ε × δ)} × C × R 6 + 2 × td '
= C × R 6 / (ε × δ) + 2 × td '··· (18)
It is expressed as given in a form that is independent of the reference voltage (V REF) and voltage (V D1). The resistance (R 6), since it varies according to the input signal of the frequency trimming signal input terminals T1 ~ Tn, the input signal of the frequency trimming signal input terminals T1 ~ Tn, the oscillation period (T), i.e. It indicates that it is possible to adjust the oscillation frequency. Note that the comparator response delay time in the equation (18) (td '), as with the oscillation circuit 10C of the second embodiment, the capacitor C1 of the rise by the charge terminal of the potential (or capacitor C2 (node ​​N1) a terminal potential of (the node N2)), because it is configured to compare the (potential (or terminal of the capacitor C4 (node ​​N4 of the node N3)) the potential of the) terminal of the capacitor C3 during the descent by the discharge, the comparator CMP3 each inverting input terminal of the CMP4 - for a potential difference is enlarged early, thus the same manner as in example 2, parameter variations such as temperature variations of the response of the comparator to speed between the non-inverting input terminal (+) () It has an effect of suppressing the variation of the response delay time (td ').

Further in the configuration of the oscillation circuit 10D shown in FIG. 7, a comparator CMP3, by the CMP4 output terminal VD1 of the bias circuit 6 of the power supply of the logic circuit L2 is supplied from the separate output terminal VD2 side, their outputs inversion operation even voltage variation to the output terminal VD2 by such a through current in the resulting occurs, thereby preventing it from propagating to the output terminal VD1 side. If when the output terminal VD1 and the common power supply terminal, the above voltage variation as it becomes variation of the voltage (V D1), which may lead to variations in the charge and discharge time of the capacitor C1 ~ C4 (T C ') . That is, in equation (17) above, charge and discharge time (T C ') is the voltage (V D1), it has been expressed in the form that does not contain components of the constant current (I 6), which is the voltage (V D1) a constant current (I 6) is a prerequisite to be in constant proportional relationship as shown in equation (14), when the variation in component that does not depend on the proportional relationship as in the above voltage variation, discharge time (T C ') also it would lead to variation. The variation in the charge and discharge time (T C '), that would lead to variation in the oscillation period (T). However, if even design on the voltage variation is no problem with respect to the oscillation frequency accuracy specification a target, it is of course possible to use the output terminal VD1 without providing the output terminal VD2 as a common power supply .

Moreover, it is conceivable to supply power to the power supply terminal comparator from VCC CMP3, CMP4 and a logic circuit L2 instead of the output terminal VD2, in which case, with sufficient pressure against the voltage applied to the power supply terminal VCC it is necessary to configure the like each comparator by the element. And, generally high-voltage element has poor responsiveness, which may deteriorates the response delay time of the comparator (td '). The voltage of the output terminal VD2 in the present embodiment, the use of low breakdown voltage elements it is possible to freely set are possible, thus can be the response delay time (td ') to speed lead to the stability of the oscillation period .

According to this modification, in addition to the effects of Embodiment 2, it is possible to obtain an oscillation frequency does not depend on the reference voltage (V REF), the variation in the reference voltage (V REF) by the parameter variation such as temperature variation occurs oscillator circuit is obtained which can also ensure a stable oscillation frequency. When addition was constituting the oscillating circuit on a semiconductor substrate, the capacitance of the capacitor, and manufacturing variation in the resistance value oscillation frequency occurs even deviate from the expected value, the oscillation frequency by the frequency trimming signal input terminals T1 ~ Tn adjustment, the oscillation circuit can be obtained that enables correction. Still further comparator CMP3, CMP4 and oscillation circuit which prevents the influence of the oscillation frequency of the power supply voltage variation caused by the operation of the logic circuit L2 is obtained, the comparator CMP3, CMP4 in this variation the comparator CMP1, CMP2 in Example 2 it is of course possible to configure the same input connection relation. In that case the same function as the logic circuit L1 a logic circuit L2 is namely the set signal input terminal S, an output terminal Q when a rising edge to the reset signal input terminal R is input, configured to inverting output terminal QB is inverted . Specific examples, along with replacing the NAND gate G1, G2 in the logic circuit L2 to the NOR gate, the output terminal Q of the output of the inverter G3, may be an inverter G4 output and the inverting output terminal QB.

The respective output terminals VD1 of the bias circuit 6 according to this modification connected to the power supply terminal VD1 of the oscillation circuit 10C according to the second embodiment, by changing the output terminal IB of the bias circuit 6 to a constant current bias source IB0, PMOS transistor M16 of connected to the drain terminal may be configured oscillation circuit.

<Modification 4>
Modification 4 is to provide an oscillation circuit capable of enlarging the range of adjustment of the oscillation frequency in Modification 3.

Figure 8 is a circuit diagram showing the configuration of a bias circuit according to a fourth modification.

The present modification will be described below with reference to FIG.

Bias circuit 61 according to a fourth modification is to replace the bias circuit 6 of the oscillation circuit 10D according to a third modification. That is, constituting the oscillation circuit by the oscillator circuit core OSC3 a bias circuit 61 which receives the output terminals VD1, VD2, IB in the bias circuit 6 of the oscillation circuit 10D.

Bias circuit 61, in addition to the configuration of the bias circuit 6 according to a third modification of FIG. 7, the frequency trimming signal input terminal of the m-bit Tn + 1 ~ Tn + m, and providing a decoder circuit 8. The bias circuit 61, in place of the NMOS transistor M21 which has been NMOS transistor M20 and the current mirror connected in the bias circuit 6, also the NMOS transistors M211 ~ M21i connected NMOS transistor M20 and the current mirror plurality of (i pieces) provision of the NMOS transistor. The bias circuit 61 is provided with an analog switch circuit 7 for connecting the respective drain terminals of the NMOS transistors M211 ~ M21i to selectively output terminal IB by a signal from the decoder circuit 8. NMOS transistors M211 ~ M21i analog switch circuit 7 and the decoder circuit 8 constitute a trimming circuit for adjusting the constant current value. Incidentally, the NMOS transistors M211 ~ M21i as sizing individually W / L (gate width / gate length), as is the current mirror ratio of the NMOS transistor M20 in each selected NMOS transistor varies, the frequency It shall adjust the current value of the output terminal IB by the input signal of the trimming signal input terminal Tn + 1 ~ Tn + m. Or, by varying the number of selected collector terminals of the NMOS transistors M211 ~ M21i by the input signal of the frequency trimming signal input terminal Tn + 1 ~ Tn + m, effectively it may be changed a current mirror ratio of the NMOS transistor M20.

Frequency adjustment by the frequency trimming signal input terminal Tn + 1 ~ Tn + m, the output terminal is due to adjusting the current value of IB, which drain current I12 and the output terminal IB of [delta] (PMOS transistor M7 in the formula (18) It corresponds to adjusting the overall mirror ratio of the sink current).

On the other hand, the frequency adjustment by the frequency trimming signal input terminals T1 ~ Tn which had in the bias circuit 6 is equivalent to the fact that by adjusting the R 6 in the formula (18), the selection of R 6 is power It will be subject to the VCC voltage constraints of. That is, the drain current I12 of PMOS transistor M7 (which is determined by the reference voltage (V REF) and the feedback taps ~ GND resistance between R5), the potential drop in the resistance R6 between the selected partial pressure tap and GND by the analog switch circuit 4 Occur. However, the potential drop can not exceed the voltage of the power supply VCC. Because in practice it is necessary to further secure the saturation region operation of the PMOS transistor M7, the upper limit of the potential drop it is necessary to suppress even lower.

The potential drop across the resistor R6 is also because it is configured to be supplied, for example, to detect the terminal voltage of the capacitor C1 ~ C4 as a power source circuit for charging and discharging operation of the capacitors C1 ~ C4 as a voltage of the output terminal VD1 when you want such enhanced responsiveness constituted by a thin low voltage transistor gate oxide thickness of the comparator, it becomes necessary to further suppress the potential drop.

Further the power supply voltage required to maintain the charging and discharging operation of the capacitors C1 ~ C4 may lower, thus the potential drop across the resistor R6 also present lower limit value.

Specific examples thereof include a bias circuit 6 in the third modification of FIG. 7 constituted by 5V system MOS transistors, a comparator CMP3, CMP4 and PMOS transistor M16 and later of the capacitor C1 connected to the output terminal VD1 of the bias circuit 6 ~ C4 charge If the circuit part related to the discharge operation is constituted by 3V type MOS transistor, the potential drop across the resistor 6, that is, as the voltage of the output terminal VD1 needs to be set within the range of about 2V ~ 3.6V.

According to this modification, since the oscillation frequency adjustment possible due to the current adjustment of the output terminal IB, it is possible to obtain an oscillation circuit that is larger frequency tuning range in addition to the effects of the third modification.

Example 3 shows an embodiment for a semiconductor integrated circuit device which applies the oscillation circuit described in Examples 1 and 2 and Modification 1-4.

Figure 9 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to the third embodiment.

The semiconductor integrated circuit device 9, on a single semiconductor substrate, the oscillation circuit (OSC) 10, a clock pulse generator (CPG) 11, ROM module (ROM) 13, RAM modules (RAM) 14, a logic circuit (LOGIC) 15 and further non-volatile memory module (NVM) 12 is mounted. Here the oscillation circuit 10 is, for example, a oscillating circuit 10D shown in the third modification of FIG. 7, the frequency trimming signal input terminals T1 ~ Tn, and the frequency trimming signal input terminal Tn + 1 ~ Tn + m is a non-volatile memory module 12 It shall be controlled based on the trimming data stored in the. The oscillation output signal CK0 of the oscillation circuit 10 is inputted to the clock pulse generating circuit 11, a clock pulse generating circuit 11 is a clock pulse that controls the ROM module 13, RAM module 14 and a logic circuit 15, based on the oscillation output signal CK0 sending a. Further, ROM module 13, RAM module 14 is two-phase clock signals CK1P, controlled by CK1N, also the logic circuit 15 is assumed to be controlled by a single-phase clock CK2. Logic circuit 15 is, for example, a central processing unit (CPU) or digital signal processor (DSP) or the like. The semiconductor integrated circuit device 9 is manufactured in a CMOS process or the like.

Incidentally, FIG. 11 is a circuit diagram showing the configuration of a generation circuit of the two-phase clock signals according to the third embodiment. Generating circuit 11d of the two-phase clock signals according to the third embodiment includes a clock pulse generation circuit 11. Generating circuit of two-phase clock signal 11d has a NAND gate G5 and the NOR gate G7 and an inverter G6 delay circuit (delay) 16. In the NAND gate G5, while the oscillation output signal to the input terminal CK0 is input, and the other output terminal of the delay circuit 16 to the input terminal connected to the input terminal of the inverter G6 is connected to the output terminal. In NOR gate G7, while the oscillation output signal to the input terminal CK0 is input, an output terminal of the delay circuit 16 to the other input terminal is connected. In the delay circuit 16, an oscillation output signal CK0 is input. The 2-phase clock signal CK1P from the output terminal of the inverter G6, and outputs the 2-phase clock signal CK1N from the output terminal of the NOR gate G7.

Figure 10 is a timing chart of the clock pulse generating circuit according to the third embodiment.

Now if the oscillation output signal CK0 rises, since the output of NOR gate G7 becomes Low level, first falls two-phase clock signals CK1N. On the other hand, two-phase clock signal CK1P side output Low level of the NAND gate G5 waiting for rising delay amount of the delay circuit 16, the output of the inverter G6 becomes the High level, the two-phase clock signal CK1P rises, the oscillation output the pulse rise is delayed relative to the rising of the signal CK0. Then, when falls oscillation output signal CK0, High level output of the NAND gate G5 is, since the output of the inverter G6 becomes Low level, first CK1P falls. Meanwhile, since the two-phase clock signal CK1N side falling waits a delay amount becomes the output of the NOR gate G7 is the High level two-phase clock signals CK1N delay circuit 16 rises, two-phase clock signal CK1N oscillation output signal the rise is the pulse that is delayed with respect to the falling edge of the CK0.

As shown in FIG. 10, two-phase clock signals CK1P, CK1N since having a delay time to each of the rising side of the oscillating output signal CK0 as described above (tcd), two-phase clock signals CK1P, each High levels of CK1N period without overlapping, to form a 2-phase clock signal. Then, as shown in FIG. 9, RAM if module 14 performs access control, for example, the data line precharge in the High level period of the two-phase clock signals CK1P RAM module 14 using 2-phase clock signals CLK1P, the CLK1N allocation period, then it is possible to read control such assign High level period of the two-phase clock signals CK1N the sense amplifier activation and the sense amplifier latch control of the output data of the data read. In such applications, two-phase clock signals CK1P, CK1N but both must always ensure a predetermined pulse width, to achieve this, the oscillation output signal CK0, and that the frequency variation is small with respect to such temperature variations, it is required in addition to the oscillation pulse duty approximately 50%.

The single-phase clock signal CK2 in Fig. 10, in the case of using a control such as logic circuits 15 in FIG. 9, one of the High level period width of the single-phase clock signal CK2 (tWH), and Low level period width (TWL) it is also obvious that it is important in the logic circuit 15, thus two-phase clock signals CK1P, similar case of CK1N, oscillation output signal CK0 of the oscillation circuit 10, the frequency variation is small with respect to such temperature fluctuations, and its it is required that in the oscillation pulse duty approximately 50%.

2-phase clock signals for controlling the embedded by the various modules in a semiconductor integrated circuit device on as described above CK1P, CK1N, called system clock such a single-phase clock signal CK2 is generally connect an external such as a crystal oscillator to obtain the oscillation frequency of the high precision. On the other hand, the present embodiment, by utilizing any of the oscillation circuit of Examples 1, 2 and the modifications 1 to 4 as an oscillation circuit 10, external components such as the beginning stabilizing capacitor crystal resonator is not required, cost, and also advantageous in part peeling and reliability plane.

In this embodiment, the frequency variation described above is small, it is possible to easily obtain the oscillation output of approximately 50% duty.

In Figure 9, the nonvolatile memory module 12, so that the oscillation output signal CK0 of the oscillation circuit 10 becomes a desired frequency in advance by writing frequency trimming data in the semiconductor integrated circuit device 9 in the manufacturing process, during normal operation by inputting the oscillation circuit 10 reads this, the oscillation frequency of the semiconductor integrated circuit device 9 alone oscillation circuit 10 can automatically be adjusted to a desired value. Incidentally, the decoder circuit 5 and 8, have a register or the like for storing frequency trimming data read from the nonvolatile memory module 12. Thus, it is possible to obtain a semiconductor integrated circuit device which reduces also individual variation in the oscillation frequency.

According to this embodiment, requires no external components such as a crystal oscillator, can be a small system clock frequency varies obtain easily producible semiconductor integrated circuit device.

Example 4 is an embodiment related to the rotation angle detecting device which applies the oscillation circuit described in Examples 1 and 2 and Modification 1-4.

Figure 12 is a block diagram showing the configuration of a rotation angle detecting apparatus according to the fourth embodiment. Rotation angle detecting apparatus 21 includes an oscillation circuit (VCO) 22 and servo (SERVO) 23 and the angular velocity detection element (MEMS) 24. Rotation angle detecting device 21 outputs a servo value the force displacement amount of Coriolis is made to resonate at a resonance frequency MEMS24. The angle of rotation is proportional to the servo value is detection principle. Note that the angular velocity (rotation angle) detecting apparatus is disclosed in Patent Documents 2 and 3.
[Patent Document 2] JP 2011-58860 JP [Patent Document 3] JP 2011-64515 JP VCO22, the oscillation circuit described in Examples 1 and 2 and the modifications 1 to 4 is used. VCO22 generates a basic clock of SERVO23.

SERVO23 generates a drive signal for resonating MEMS24 based on the basic clock. Specifically, SERVO23 the vibration of MEMS24 adjusts the frequency of the drive signal such that the resonant state. It converts the displacement of MEMS24 by the drive signal the displacement signals to detect a vibration displacement of the vibration axis performs synchronous detection. Then, a signal obtained by the synchronous detection, for example, integrated by the integrator (not shown). Driving signal and the displacement signal when the resonant state i.e. fv (the frequency of the drive signal) = fd (resonance frequency in the driving direction), the phase has a characteristic that differ 90 °. Therefore, when performing synchronous detection by the detection signal to the displacement signal, it is that the resonance state reached 0 subtraction output of the synchronous detection. Then the output of the integrator converges to a constant value. Then, it outputs the signal obtained by the integrator frequency trimming input terminal of the VCO 22. Basic clock VCO22 is output frequency changes following the change of the drive signal. Incidentally, VCO 22 and SERVO23 may be realized by a semiconductor integrated circuit device according to the third embodiment.

Further, SERVO23 performs servo control so that the feedback voltage such that the displacement of MEMS24 by Coriolis force generated in the oscillation axis direction perpendicular to zero the sensor. Then, it outputs an amplitude of the feedback voltage at that time as a detection signal of the angular velocity (rotation angle).

MEMS24, using semiconductor manufacturing technology, is produced by a mechanical mechanism and a functional device that integrates an electronic circuit integrated MEMS (Micro Electro Mechanical Systems) technology on a single silicon wafer.

VCO22 is thermally, since it is voltage stable, the rotation angle detection device 21, temperature, zero-point error for the voltage, change in sensitivity is reduced, it is possible to stably. Further, it allows fine adjustment of the resonance frequency of MEMS24 the manufacturing variation easily occurs, may wish to improvement in yield as a total when combined.

The present invention is not limited to the embodiments described above, but includes various modifications. For example, the above embodiments are those described in detail in order to better illustrate the invention and are not intended to be limited to those having the necessarily all described configurations. Further, it is possible to replace a part of the configuration of one embodiment in the configuration of another embodiment, it is also possible to add a configuration of an embodiment alternative embodiment to the configuration of. A part of the configuration of each embodiment may be added, deleted, or replaced for other configurations.

1 ... constant current generating circuit 2 ... reference voltage generating circuit 3,6,61 ... bias circuit 4,7 ... analog switch circuits 5,8 ... decoder circuit 9 ... semiconductor integrated circuit device 10,10A, 10B, 10C, 10D ··· oscillation circuit 12 ... nonvolatile memory modules 21 ... rotation angle detecting device 22 ... oscillation circuit (VCO)
23 ... servo (SERVO)
24 ... angular velocity sensor (MEMS)
C1, C2, C3, C4 ··· capacitor R1, R2, R3, R4, R5, R6 ··· resistance A1, A2, A3, A4, A30 ··· operational amplifier CMP1, CMP2, CMP3, CMP4 ··· comparator L1, L2 · · · logic circuits M1, M2, M3, M4, M7, M8, M9, M12, M13, M16, M17, M19, M22, M23, M31, M32 ··· PMOS transistor M5, M6, M10, M11, M14, M15, M18, M20, M21, M211, M12 ~ M21i, M30 ··· NMOS transistors N1, N2, N3, N4, N5, N6, N7, N8 ··· node RL2, RL4 ··· ladder resistance VCC ··· power supply terminal VREF ··· reference voltage input terminal G0 ··· bias output terminal VR ·· Comparison reference voltage output terminal VD1, VD2 output terminal of the voltage output terminal IB ... bias circuit ... bias circuit (for absorbing constant current)
IB0 · · · constant current bias source OUT · · · oscillation output terminals T1, T2, ~, Tn, Tn + 1, Tn + 2, ~, Tn + m ··· frequency trimming signal input terminal

Claims (15)

  1. Is charged driven by a current, a first capacitor that terminal voltage linearly changes in a first direction,
    Is discharged driven by a current with charge driver of the first capacitor, a second capacitor that varies in a second direction opposite the direction linearly from its terminal voltage is the first direction,
    Equipped with,
    An oscillator circuit the terminal voltages of the first and second capacitors is adapted to form a oscillation period based on the first timing crossing.
  2. According to claim 1,
    Based on the first timing, the terminal voltage of the first capacitor and the pull-down or pull-up in the second direction, pulling up or pulling down the terminal voltage of the second capacitor to the first direction oscillation circuit.
  3. According to claim 2,
    A third capacitor whose terminal voltage is charged driven linearly changed in the first direction by the current,
    Is discharged driven by a current with charge driver of the third capacitor, a fourth capacitor whose terminal voltage is linearly changed in the second direction,
    Equipped with,
    An oscillation circuit for inverting the oscillation output on the basis of the second Tamingu the respective terminal voltages of the third and fourth capacitor intersect.
  4. According to claim 3,
    Based on the second timing, the terminal voltage of the third capacitor and the pull-down or pull-up in the second direction, pulling up or pulling down the terminal voltage of the fourth capacitor to the first direction oscillation circuit.
  5. According to claim 4,
    The first direction is the direction of the potential of the first power supply terminal, the second direction is the direction of the reference potential,
    A first trimming circuit for adjusting the voltage value of the first power supply terminal,
    The current value of the current charging driving terminals of the first and third capacitor, a second trimming circuit for adjusting a current value of the second and fourth current terminal of the capacitor to discharge driving,
    Oscillation circuit having a.
  6. An oscillation circuit according to claim 5,
    A non-volatile memory module for storing the trimming data of said first and second trimming circuit,
    A logic circuit which is controlled by a system clock generated from the oscillation output pulse of the oscillation circuit,
    The semiconductor integrated circuit device having a.
  7. An oscillation circuit of any one of claims 1 to 5,
    A servo controlled by the oscillation output pulse clock of the oscillator circuit,
    An angular velocity detection element which receives a drive signal from the servo,
    Rotation angle detecting apparatus having a.
  8. And the first power supply terminal,
    First, having a second terminal, a first capacitor connected to said first terminal to a reference potential,
    A first constant current source provided between the second terminal and the first power supply terminal of said first capacitor,
    A first short circuit for short-circuiting between the second terminal and the reference potential of the first capacitor based on the first control signal,
    A first, a second terminal, a second capacitor connected to said first terminal to said reference potential,
    A second constant current source provided between the second terminal and the reference potential of said second capacitor,
    Second short circuit for short-circuiting between the second terminal and the first power supply terminal of said second capacitor based on a second control signal having a polarity inverted with respect to the first control signal When,
    A first, a second terminal, a third capacitor connected to said first terminal to said reference potential,
    A third constant current source provided between the second terminal and the first power supply terminal of said third capacitor,
    And a third short circuit for short-circuiting between the reference potential and a second terminal of said third capacitor based on said second control signal,
    A first, a second terminal, a fourth capacitor connected to said first terminal to said reference potential,
    A fourth constant current source provided between the second terminal and the reference potential of said fourth capacitor,
    A fourth short circuit for short-circuiting between the second terminal of the fourth capacitor based on the first control signal and said first power supply terminal,
    A first comparator for comparing the second terminal potential of the first said and second terminal potential second capacitor of the capacitor,
    A second comparator for comparing the second terminal potential of the third of said the second terminal potential fourth capacitor of the capacitor,
    A logic circuit for generating the first control signal based on the comparison output of said first comparator comparing the output and a second comparator and a second control signal,
    Equipped with,
    Said logic circuit,
    Wherein said second comparator from comparison output inverting said first comparator is form by detecting the intersection of the second terminal voltage of said first of said second capacitor and a second terminal potential of the capacitor first within a period of up to the second terminal potential and the fourth second crossing detection to form the comparison output inversion of the terminal potential of the capacitor of the three capacitors, the first first polarity control signal in, also respectively output the second control signal at a second polarity,
    Said second comparator the said third second terminal potential and the fourth second the first comparator cross from the comparison output inversion which form by detecting the terminal potential of the capacitor of the capacitor first the period of the comparison to the output inversion which form by detecting the intersection of the second terminal voltage of the second capacitor and the second terminal potential of the first capacitor, said first control signal the second polarity in, also configured to output the said second control signal at a first polarity,
    Wherein the first short circuit activates a first polarity of said first control signal,
    The second short circuit activates a second polarity of said second control signal,
    The third short circuit activates a first polarity of said second control signal,
    Wherein with fourth short circuit is configured to activate a second polarity of said first control signal, an oscillation circuit utilizing the first or second control signal as an oscillation output.
  9. According to claim 8,
    Further comprising a second power supply terminal,
    It said first and second comparators, and said logic circuit, said second oscillation circuit supplied with power from the power supply terminal.
  10. According to claim 8 or claim 9,
    Said first voltage applied to the power supply terminal, said first, second, third, and fourth current value and an oscillation circuit having a proportional relationship between the constant current source.
  11. According to claim 8 or claim 9,
    Inverting input terminal has a non-inverting input terminal and an output terminal, a differential amplifier operating between the different third power supply terminal and a reference potential and the first or second power supply terminal,
    A source terminal connected to a third power supply terminal, a first MOS transistor of the first conductivity type which is directly or indirectly controlled by its gate terminal the output terminal of the differential amplifier,
    A plurality of resistors connected in series, one end reference potential f, connect the other end to the drain terminal of the first MOS transistor, a voltage divider is connected to any resistor connection point to the non-inverting input terminal of the differential amplifier When,
    A second MOS transistor of the first conductivity type and each connected in common said first MOS transistor and the gate and source terminals,
    The drain terminal to the drain terminal of the second MOS transistor, connected respectively to a source terminal to a reference potential, a third MOS transistor of the second conductivity type which is short-circuited to the gate terminal to the drain terminal,
    Said third MOS transistor and a source terminal, and a fourth MOS transistor of the second conductivity type which is respectively connected in common gate terminal,
    The drain terminal to the drain terminal of said fourth MOS transistor, connected respectively to the source terminal to the first power supply terminal, a fifth MOS transistor of the first conductivity type which is short-circuited to the gate terminal to the drain terminal,
    Equipped with,
    Forming the fifth MOS transistor and a source terminal, a sixth of the first conductivity type and each connected in common gate terminal, and each of the first constant current source by the seventh MOS transistor and said third constant current source and,
    The sixth MOS transistor and the source terminal, and constitute the second constant current source and a fourth constant current source, respectively, by the eighth, and ninth MOS transistor of the second conductivity type which is respectively connected in common gate terminal,
    Said first voltage applied to the power terminal, an oscillation circuit for generating based on a voltage taken out from an arbitrary resistor connection point of the voltage dividing circuit in.
  12. According to claim 11,
    And a trimming control input signal terminal comprising a plurality of bits,
    A plurality of analog switches, one end of each analog switch is connected to a plurality of resistors connected point in the voltage divider circuit, and an analog switch circuit as the output terminal and the other end of the analog switch commonly connected to,
    A decoder circuit for selectively turning on control of the respective analog switches of said analog switch circuit based on a signal from the trimming control input signal terminal,
    Equipped with,
    Voltage supplied to the first power supply terminal, said together is generated based on the voltage taken out from the output terminal of the analog switch circuit, the voltage is adjusted based on the input signal to the trimming control input signal terminal oscillation circuit.
  13. According to claim 8 or claim 9,
    A first trimming circuit for adjusting the voltage value of the first power supply terminal,
    Said first and second trimming circuit for adjusting the second, third, and fourth constant current value,
    Oscillation circuit having a.
  14. An oscillation circuit according to any one of claims 13 claim 8,
    A non-volatile memory module for storing the oscillation frequency trimming data of said oscillation circuit, a logic circuit which is controlled by a system clock generated from the oscillation output pulse of the oscillation circuit,
    The semiconductor integrated circuit device having a.
  15. An oscillation circuit according to any one of claims 13 claim 8,
    A servo controlled by the oscillation output pulse clock of the oscillator circuit,
    An angular velocity detection element which receives a drive signal from the servo,
    Rotation angle detecting apparatus having a.
PCT/JP2014/052389 2013-09-10 2014-02-03 Oscillation circuit, semiconductor integrated circuit device using same, and rotational angle detection device WO2015037252A1 (en)

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JP2018025414A (en) * 2016-08-08 2018-02-15 日立オートモティブシステムズ株式会社 Inertial detector

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