JP2012160927A - Delay control circuit, charge pump circuit, and method of controlling charge/discharge current in charge pump circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay control circuit that apples an optimum bias voltage to a charge pump circuit even if transistors are unbalanced.SOLUTION: The delay control circuit includes: the charge pump circuit adapted to charge/discharge from a current input/output terminal on receipt of predetermined signals; a delay circuit supplied as power supply with a voltage depending on a terminal voltage at the current input/output terminal; and a bias generation circuit for generating a bias voltage on which the charge/discharge current of the charge pump circuit is based. The charge pump circuit and the delay circuit each comprise first conductivity type transistors and second conductivity type transistors, and the bias generation circuit generates the bias voltage on the basis of the sum of a transconductance of the first conductivity type transistors and a transconductance of the second conductivity type transistors. The charge/discharge of the charge pump circuit controls the power supply voltage to the delay circuit to control a delay time of the delay circuit.

Description

  The present invention relates to a delay control circuit, a charge pump circuit, and a charge / discharge current control method in the charge pump circuit. In particular, in a delay control circuit that controls the delay time of the delay circuit and the oscillation frequency of the ring oscillator based on the output voltage of the charge pump circuit such as a PLL circuit or a DLL circuit, the charge pump circuit of the charge pump circuit is controlled based on the output voltage of the charge pump circuit. The present invention relates to an adaptive bias type delay control circuit for controlling the magnitude of a charge / discharge current.

  Non-Patent Document 1 describes an adaptive bias type (adaptive bias type) PLL (Phase-Locked Loop) circuit and a DLL (Delay-Locked Loop) circuit. In Non-Patent Document 1, when the power supply voltage of a delay circuit having a CMOS configuration (in the case of a PLL circuit, the delay circuit is a ring oscillator) is changed to change the delay time of the delay circuit (the oscillation frequency of the ring oscillator), the delay circuit is given. Based on the power supply voltage, the bias voltage applied to the charge pump circuit included in the PLL and DLL control loops and the bias voltage applied to the amplifier used to supply power to the delay circuit are controlled. By controlling in this way, the charge / discharge current of the charge pump circuit and the output resistance of the power amplifier are optimized in accordance with the delay time of the delay circuit (the oscillation frequency of the ring oscillator). It is described that even if the delay time of the delay circuit (the oscillation frequency of the ring oscillator) is changed over a wide range, the damping factor of the control loop can be made constant and low jitter can be realized.

  Patent document 1 describes a conventional reference voltage generation circuit.

JP 11-45125 A (corresponding to US Pat. No. 6,160,391)

S. Sidiropoulos et al. "Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers", in Proc. Symposium on VLSI Circuits, pp. 124-127, June 2000

  The entire disclosure of Patent Document 1 and Non-Patent Document 1 is incorporated herein by reference.

  The following analysis is given by the present invention. If the delay circuit is composed of a first conductivity type transistor and a second conductivity type transistor, such as a CMOS PMOS transistor and an NMOS transistor, even if the delay time of the delay circuit is the same as shown in FIG. Due to variations in characteristics of the first conductivity type transistor and the second conductivity type transistor, the power supply voltage of the delay circuit is not the same. In particular, if the characteristics of the first conductivity type transistor and the second conductivity type transistor vary in imbalance, even if the operation current of the control loop of the PLL or DLL is controlled based on the power supply voltage of the delay circuit, the operation current does not increase. It is not optimal for the control loop and the desired characteristics cannot be obtained. This problem will be described in more detail in the description of the embodiment.

  According to a first aspect of the present invention, a charge pump circuit that charges and discharges from a current input / output terminal in response to a predetermined signal, and a delay circuit to which a voltage based on the terminal voltage of the current input / output terminal is supplied as a power source And a bias generation circuit for applying a bias voltage serving as a reference for charge / discharge current to the charge pump circuit, wherein the charge pump circuit and the delay circuit are respectively a first conductivity type transistor and a first conductivity type. The bias generation circuit is configured to include a second conductivity type transistor having a conductivity type different from that of the transistor, and the bias generation circuit is configured based on a sum of a mutual conductance of the first conductivity type transistor and a mutual conductance of the second conductivity type transistor. A delay control circuit for generating a voltage is provided.

  According to the second aspect of the present invention, a charging circuit that charges the current flowing through the first conductivity type charging transistor from the current input / output terminal in response to the first signal, and the second circuit in response to the second signal. A discharge circuit for discharging a current flowing through the two-conductivity type discharge transistor from the current input / output terminal; a value of the discharge current equal to a value of the charge current; and a current value of the mutual conductance of the first conductivity type transistor There is provided a charge pump circuit comprising: a bias generation circuit that applies a bias voltage to the charging transistor and the discharging transistor so as to be proportional to the sum of the mutual conductances of the second conductivity type transistors.

  According to a third aspect of the present invention, there is provided a phase comparison circuit constituted by CMOS circuits each having a PMOS transistor and an NMOS transistor, a charge pump circuit, and a voltage controlled oscillation circuit, and the phase comparison circuit includes PLL which compares the oscillation clock of the voltage controlled oscillation circuit with an externally applied reference clock with respect to the oscillation frequency and phase, and based on the comparison result, the PLL which charges and discharges the power supplied to the voltage controlled oscillation circuit by the charge pump circuit In the circuit, a step of generating a reference current based on a sum of a mutual conductance of the PMOS transistor and a mutual conductance of the NMOS transistor, a charge current of the charge pump circuit based on a value of the reference current, and a discharge current And a step of controlling the constant Discharge current control method of the charge pump circuit, characterized in that there is provided.

  According to each aspect of the present invention, the charge / discharge current of the charge pump circuit can be optimized even when the characteristics of the first conductivity type transistor and the second conductivity type transistor vary in imbalance.

1 is a block diagram of an entire delay control circuit (PLL circuit) according to a first embodiment of the present invention. FIG. 2 is a circuit block diagram illustrating an example of a configuration of a bias current generation circuit in FIG. 1. FIG. 3 is a circuit block diagram illustrating an example of a configuration of a regulator amplifier in FIG. 2. FIG. 2 is a circuit block diagram illustrating an example of a configuration of a charge pump circuit in FIG. 1. It is explanatory drawing which shows the relationship between the threshold value of a transistor, a VCO control voltage, and a charge pump circuit bias current in a comparative example. FIG. 5 is an explanatory diagram illustrating a relationship among a transistor threshold, a VCO control voltage, and a charge pump circuit bias current in the first embodiment. It is a block diagram of the whole delay control circuit (PLL circuit) by the 2nd Embodiment of this invention. It is a block diagram of the whole delay control circuit (DLL circuit) by the 3rd Embodiment of this invention. It is a circuit block diagram of an adaptive bias type PLL circuit which is a comparative example of the present invention.

[Outline of Embodiment]
An outline of an embodiment of the present invention will be described. As shown in FIG. 1, a charge pump circuit 10 that charges and discharges from a current input / output terminal CIO in response to predetermined signals (UPB, DN), and a voltage VC based on the terminal voltage VPMP of the current input / output terminal CIO is a power source. And a bias generation circuit 30 that supplies the charge pump circuit 10 with bias voltages (Vbiasp, Vbiasn) serving as a reference for charge / discharge current. Further, referring also to FIG. 4, the charge pump circuit 10 and the delay circuit 20 include a first conductivity type transistor (MP9, MP10, MVP0 to MVP2) and a second conductivity type transistor having a conductivity type different from that of the first conductivity type transistor, respectively. (MN12, MN13). Further, the bias generation circuit 30 generates a bias voltage based on the sum of the mutual conductance of the first conductivity type transistor and the mutual conductance of the second conductivity type transistor.

  Therefore, a current proportional to the sum of the mutual conductance of the first conductivity type transistor and the mutual conductance of the second conductivity type transistor flows in the charge / discharge current of the charge pump circuit. Since the transmission speed of the signal of the delay circuit (the reciprocal of the delay time) is approximately proportional to the sum of the mutual conductance of the first conductivity type transistor and the mutual conductance of the second conductivity type transistor, even if the mutual conductance of the first conductivity type transistor is Even when the value of the value and the value of the mutual conductance of the second conductivity type transistor are unbalanced, the charge / discharge current value of the charge pump circuit can be optimized.

  It should be noted that the drawings cited in this summary and the accompanying drawing reference numerals are merely examples for facilitating understanding, and are not intended to be limited to the illustrated embodiments.

[Supplementary explanation of problems of conventional technology]
Next, before describing the embodiments of the present invention in detail, the problems of the prior art will be described in a little more detail. FIG. 9 is a circuit block diagram of an adaptive bias type PLL circuit as a comparative example of the present invention. FIG. 9 is a drawing created by the inventor based on the contents disclosed in Non-Patent Document 1 already described.

  A configuration of an adaptive bias type PLL circuit 900 as a comparative example of FIG. 9 will be described. The phase comparison circuit 40 compares the frequency and phase of a reference clock REFCLK given from the outside with CLKOUT that is an output clock signal of the entire adaptive bias type PLL circuit 900. When the phase comparison circuit 40 detects that the frequency and phase of the output clock signal CLKOUT are delayed with respect to the frequency and phase of the reference clock REFCLK, it outputs a low level to the control signal UPB. On the other hand, when the frequency and phase of the output clock signal CLKOUT are aligned with or delayed from the reference clock REFCLK, the control signal UPB outputs a high level.

  When the phase comparison circuit 40 detects that the frequency and phase of the output clock signal CLKOUT are advanced with respect to the frequency and phase of the reference clock REFCLK, the phase comparison circuit 40 outputs a high level to the control signal DN. On the other hand, when the frequency and phase of the output clock signal CLKOUT are aligned with or delayed from the reference clock REFCLK, the control signal DN outputs a low level. Control signals UPB and DN output from the phase comparison circuit 40 are connected to the charge pump circuit 10.

  The charge pump circuit 10 charges and discharges from the current input / output terminal CIO based on the logic levels of the control signals UPB and DN. FIG. 4 is a circuit block diagram showing an internal configuration of the charge pump circuit 10. As shown in FIG. 4, the charge pump circuit 10 includes a charging circuit 15 and a discharging circuit 16.

  The charging circuit 15 has a source controlled to the power supply VDD, a gate controlled to the first bias voltage Vbiasp, a charging current source transistor MP9 connected as a PMOS transistor, a source controlled to the drain of the current source transistor MP9, and a gate controlled. The signal UPB includes a switch transistor MP10 which is a PMOS transistor having a drain connected to the current input / output terminal CIO.

  In the discharge circuit 16, the source is the power source VSS, the gate is the second bias voltage Vbiasn, the discharge current source transistor MN12 is an NMOS transistor connected, the source is the drain of the current source transistor MN12, and the gate is controlled. The signal DN includes a switch transistor MN13 which is an NMOS transistor whose drain is connected to the current input / output terminal CIO.

  Returning to FIG. 9, the description will be continued. The current input / output terminal CIO of the charge pump circuit 10 is connected to the loop filter 60. The loop filter 60 includes a fixed resistor Rz and a capacitor Cp connected in series between the current input / output terminal CIO and the power supply VSS. The terminal voltage (output voltage of the loop filter 60) VPMP of the current input / output terminal CIO filtered by the loop filter 60 is connected to the non-inverting input terminal INP of the regulator amplifier 50 serving as the power supply circuit of the delay circuit 20. The VPMP is also connected to the bias generation circuit 930.

  The output terminal OUT of the regulator amplifier 50 is connected to the inverting input terminal INM, and the regulator amplifier 50 has a voltage equal to the terminal voltage VPMP of the current input / output terminal CIO filtered by the loop filter 60 input to the non-inverting input terminal INP. Output from the output terminal OUT. The output terminal OUT of the regulator amplifier 50 is connected to the power supply of the delay circuit 20 and supplies the power supply voltage VC to the delay circuit 20. The power supply voltage VC of the delay circuit 20 is substantially equal to the terminal voltage VPMP of the current input / output terminal CIO filtered by the loop filter 60. The operating current of the regulator amplifier 50 is controlled by the second bias voltage Vbiasn given from the bias generation circuit 930, and the output impedance as the power supply circuit is also controlled by the bias voltage Vbiasn.

  The delay circuit 20 includes three CMOS inverter circuits each including a PMOS transistor MVP0 and an NMOS transistor MVN0, a PMOS transistor MVP1 and an NMOS transistor MVN1, and a PMOS transistor MVP2 and an NMOS transistor MVN2. The three inverter circuits function as a ring oscillator by connecting the output terminal of the preceding stage to the input terminal of the subsequent stage and connecting the output terminal of the final stage to the input terminal of the first stage. Since the oscillation frequency is controlled by the voltage value of the power supply voltage VC, the ring oscillator functions as a voltage controlled oscillator (VCO) in the PLL control loop. The output signal of the delay circuit 20 constituting the ring oscillator is frequency-divided by the frequency dividing circuit 41 and output to the outside as the output clock signal CLKOUT, and is also feedback-connected to the phase comparison circuit 40.

  The bias generation circuit 930 receives the output voltage VPMP of the charge pump circuit 10 and controls the first and second bias voltages Vbiasp and Vbiasn given to the charge pump circuit 10 based on this voltage value. The second bias voltage Vbiasn is also supplied to the regulator amplifier 50 serving as a power source for the delay circuit 20 to control the operating current of the regulator amplifier 50.

  The bias generation circuit 930 includes NMOS transistors MN21 and MN22 each having an output voltage VPMP of the charge pump circuit 10 connected to the gate. The source of the NMOS transistor MN22 is connected to the power supply VSS, and the drain is connected in series to the source of the NMOS transistor MN21. The NMOS transistors MN21 and MN22 connected in series convert the output voltage VPMP of the charge pump circuit 10 into a current Ibias. The plurality of transistors MN21 and MN22 are connected in series in part because the load circuit is provided between the power supply VSS and the source of the NMOS transistor MN21 for adjusting the current value of the current amount Ibias. Thus, the NMOS transistor MN21 is operated in the saturation region. The number of NMOS transistors connected in series may be three or more. Most basically, the voltage of the output voltage VPMP can also be converted to the current Ibias by connecting the output voltage VPMP to the gate of one NMOS transistor whose source is connected to a fixed voltage.

  The drain of the NMOS transistor MN21 is connected to the gate and drain of the PMOS transistor MP2, and the source of MP2 of the PMOS transistor is connected to the power supply VDD. Further, the gate and drain of the PMOS transistor MP2 are also connected to the gate of the PMOS transistor MP3. The source of the PMOS transistor MP3 is connected to the power supply VDD. The PMOS transistors MP2 and MP3 function as a current mirror circuit, and a current proportional to the current Ibias flowing between the source and drain of the PMOS transistor MP2 flows between the source and drain of the PMOS transistor MP2. In the current mirror circuit, the drain of the PMOS transistor MP2 serves as the current inlet, and the drain of the PMOS transistor MP3 serves as the current outlet.

  Further, the drain of the PMOS transistor MP3 is connected to the current input terminal (the drain of the NMOS transistor MN5) of the second current mirror circuit composed of the NMOS transistors MN5 and MN6 and the current source transistor MN12 (see FIG. 4) of the charge pump circuit 10. Has been. Further, the drain of the NMOS transistor MN5 is connected to the gates of the NMOS transistors MN5 and MN6 and the current source transistor MN12, respectively. The drain of the NMOS transistor MN5 is also connected to the gate of a current source NMOS transistor (not shown) of the regulator amplifier 50. The sources of the NMOS transistors MN5 and MN6 are both connected to the power supply VSS. By this second current mirror circuit, the second bias voltage Vbisasn is generated by the source-drain voltage generated by the current flowing between the source and drain of the NMOS transistor MN5. Further, the discharge current of the charge pump circuit 10 and the operating current of the regulator amplifier 50 are controlled by the second bias voltage Vbisasn.

  The drain of the NMOS transistor MN6 is connected to the current input terminal (drain of the PMOS transistor MP4) of the third current mirror circuit composed of the PMOS transistor MP4 and the current source transistor MP9 of the charge circuit 10 (see FIG. 4). . Further, the drain of the PMOS transistor MP4 is connected to the gates of the PMOS transistor MP4 and the current source transistor MP9, respectively. The source of the PMOS transistor MP4 is connected to the power supply VDD. By the third current mirror circuit, the first bias voltage Vbisasp is generated by the source-drain voltage generated by the current flowing between the source and drain of the PMOS transistor MP4. The charging current of the charge pump circuit 10 is controlled by the first bias voltage Vbisasp.

  A voltage-current converter circuit comprising NMOS transistors MN21 and MN22; a first current mirror circuit comprising PMOS transistors MP2 and MP3; a second current mirror circuit comprising NMOS transistors MN5 and MN6; and a current source NMOS transistor MN12 of the charge pump circuit; The magnitude of the charge / discharge current of the charge pump circuit is controlled based on the voltage of the output voltage VPMP of the charge pump circuit 10 by the third current mirror circuit composed of the PMOS transistor MP4 and the current source PMOS transistor MP9 of the charge pump circuit. be able to. Further, by appropriately setting the transistor size of each current mirror circuit, the charge current when charging the charge pump circuit 10 and the magnitude of the discharge current when discharging are relatively accurately and equal to each other. Can be.

  According to the adaptive bias type PLL circuit 900 as the comparative example, the charge / discharge current of the charge pump circuit 10 is calculated based on the output voltage VPMP of the charge pump circuit 10 which is a reference voltage of the power supply voltage VC of the delay circuit 20. Since the delay time of the delay circuit 20, that is, the oscillation frequency of the VCO changes in a wide range, the characteristics of the PLL control loop such as the charge pump circuit 10 and the regulator amplifier 50 are set to the oscillation frequency. Since the combined values can be set, even if the delay time of the delay circuit (the oscillation frequency of the ring oscillator) is changed over a wide range, the damping factor of the control loop can be made constant and a PLL circuit with low jitter can be realized.

  However, the adaptive bias PLL circuit 900 of this comparative example uses the NMOS transistors MN21 and MN22 to convert the output voltage of the loop filter into a current. On the other hand, since the delay circuit 20 has a CMOS configuration, an NMOS transistor and a PMOS transistor are used. Accordingly, when the characteristics of the NMOS transistor and the PMOS transistor vary, particularly when the characteristics of the NMOS transistor and the PMOS transistor vary in an unbalanced manner, the charge pump circuit 10 with respect to the delay time of the delay circuit 20 and the oscillation frequency of the VCO. In some cases, the charging / discharging current and the output impedance of the regulator amplifier 50 that supplies power to the delay circuit 20 may not be optimal.

  FIG. 5 shows a characteristic variation (CASE A to CASE D) of the PMOS transistor and the NMOS transistor constituting the circuit, a VCO control voltage (left axis), a charge pump circuit, etc. Shows the variation in the magnitude of the bias current (right axis) applied to. Among the variations in transistor characteristics, CASE A is a case where the threshold values of the PMOS transistor and the NMOS transistor both vary toward the lower side. Similarly, CASE B is a case where the threshold value of the PMOS transistor varies toward the higher threshold value and varies toward the lower threshold value of the NMOS transistor. On the other hand, CASE C is a case where the threshold value of the PMOS transistor varies toward the lower threshold value and varies toward the higher threshold value of the NMOS transistor. Further, CASE D is a case where both the threshold values of the PMOS transistor and the NMOS transistor vary to the higher one. Note that the case where the transistor has a lower threshold value is an example in which the transistor has a lower mutual conductance, and the case where the transistor has a higher threshold value is an example in which the transistor has a higher mutual conductance. The same result as in FIG. 5 is obtained when the mutual conductance varies for reasons other than the variation in threshold.

  Essentially, if the oscillation frequency of the VCO (delay time of the delay circuit) is constant, the characteristics of the PLL control loop, such as the charge / discharge current of the charge pump circuit, regardless of variations in the characteristics of the VCO control voltage and the transistors constituting the circuit. Is desirable as a characteristic of the PLL control loop. However, this is not the case in practice.

  Since the delay circuit (ring oscillator) operates at a high speed even if the power supply voltage is low when the threshold value of the transistor is low, the VCO control voltage has a low threshold value for both the PMOS transistor and the NMOS transistor when the oscillation frequency is considered to be constant. In the case of A, the control voltage is the lowest. Conversely, if the threshold voltage of the transistor is high, the delay circuit does not operate at a desired speed unless the power supply voltage is increased. Therefore, the control voltage is highest in the case of CASE D. As in CASE B and CASE C, when one of the PMOS transistor and the NMOS transistor is high and the other is low, the control voltage has an intermediate level.

  On the other hand, as shown in FIG. 9, when the voltage / current conversion is performed using an NMOS transistor, the bias current value is influenced by both the magnitude of the VCO control voltage and the variation in characteristics of the NMOS transistor. Receive. As in CASE A, when the threshold values of the PMOS transistor and the NMOS transistor both vary toward the lower side, the control voltage of the VCO becomes lower, so that the bias current is reduced. However, since the threshold of the NMOS transistor is low and the mutual conductance gm is high, the bias current acts in the direction of increasing. In the case of CASE A, the bias current can be set to an appropriate current value by canceling out the effect due to the low control voltage of the VCO and the direct effect due to the low threshold voltage of the NMOS transistor.

  As in CASE B, when the threshold value of the PMOS transistor varies toward the higher one and the threshold value of the NMOS transistor varies, the magnitude of the VCO control voltage becomes a standard value. It does not affect the magnitude of the current. However, since the threshold value of the NMOS transistor varies toward the lower side, variations in the threshold value of the NMOS transistor directly affect the bias current, and the bias current varies in the increasing direction. Assuming that the threshold voltage of the NMOS transistor is Vtn and (VCO control voltage VC) = (gate voltage VPMP of the NMOS transistor MN21 in the input stage of the bias generation circuit), the bias current Ibias is the square of (VPMP−Vtn). The value is proportional to.

  As in CASE C, when the threshold voltage of the PMOS transistor varies toward the higher threshold value of the NMOS transistor, the magnitude of the VCO control voltage becomes a standard value, so that bias is applied via variations in the VCO control voltage. It does not affect the magnitude of the current. However, since the threshold value of the NMOS transistor varies toward the higher one, the variation in the threshold value of the NMOS transistor directly affects the bias current, and the bias current varies in a decreasing direction.

  Finally, as in CASE D, when the threshold values of both the PMOS transistor and the NMOS transistor vary to the higher one, the control voltage of the VCO becomes higher, so that the bias current increases. However, since the threshold value of the NMOS transistor is high and the mutual conductance gm is low, the bias current acts in a decreasing direction. In the case of CASE D, the bias current can be set to an appropriate current value by canceling out the effect caused by the high control voltage of the VCO and the direct effect caused by the high threshold voltage of the NMOS transistor.

  Among CASE A to D, when the threshold value of the PMOS transistor of CASE B varies toward the higher threshold value and varies toward the lower threshold value of the NMOS transistor, the following problems occur.

  First, since the NMOS transistor that generates the bias current has a high mutual conductance, a large current flows through the bias current. However, since the mutual conductance of the PMOS transistor is low, the PMOS transistor MP9 of the charge pump circuit 10 and the regulator The gate overdrive voltage (Vgs−Vth) of the PMOS transistor of the amplifier 50 increases. As the gate overdrive voltage increases, the saturation margin decreases, and the power supply noise rejection ratio of the output voltage VPMP of the charge pump circuit and the power supply voltage VC of the delay circuit deteriorates.

  Second, since the input range of the regulator amplifier 50 that inputs the output voltage VPMP of the charge pump circuit to the non-inverting input terminal is narrowed, the VCmax level that is the maximum output voltage of the regulator amplifier 50 is lowered. When the maximum output voltage VCmax of the regulator amplifier 50 decreases, the maximum oscillation frequency of the VCO decreases, and the maximum operating frequency as the PLL circuit decreases.

  Third, since the bias current increases excessively, the current consumption increases.

  On the other hand, when the threshold value of the PMOS transistor of CASE C varies toward the lower side and the threshold value of the NMOS transistor varies toward the higher side, the bias current becomes too small and the response becomes slow. For example, when the frequency is shifted for some reason such as noise, the return to the normal frequency is delayed.

  That is, a problem particularly occurs when the threshold values of the PMOS transistor and the NMOS transistor (transistor transconductance) vary in imbalance.

[Operation of the present invention]
To solve this problem, in the present invention, as shown in an example of the circuit in FIG. 2, the bias current Ibias is based on the sum of the mutual conductance of the first conductivity type transistor MP1 and the mutual conductance of the second conductivity type transistor (MN1 + MN2). Is generated. Alternatively, a voltage VPMP based on the output voltage of the charge pump circuit is applied as a bias voltage to the first conductivity type transistor, and a first current is passed through the first conductivity type current source transistor MP1, and a voltage based on the output voltage of the charge pump circuit is set. A bias current is applied to the second conductivity type transistor as a bias voltage to cause the second current to flow through the second conductivity type current source transistor (MN1 + MN2), and a bias current Ibias is generated based on a current obtained by adding the first current and the second current. To do. As a result, as shown in FIG. 6, even if the characteristics of the first conductivity type transistor and the second conductivity type transistor vary in imbalance, if the delay time of the delay circuit is constant, a constant bias corresponding thereto is obtained. A current can be generated. A specific implementation method will be described in the description of each embodiment.

[First Embodiment]
FIG. 1 is an overall block diagram of a delay control circuit 100 according to the first embodiment of the present invention. Specifically, the delay control circuit 100 in FIG. 1 is adapted to control the charge / discharge current of the charge pump circuit 10 and the operating current of the regulator amplifier serving as the power supply circuit of the delay circuit 20 by the output voltage VPMP of the charge pump circuit 10. This is a bias type PLL circuit. Parts having the same circuit configuration as those of the comparative example already described in FIG. 9 will be denoted by the same reference numerals, and redundant description will be omitted. Therefore, please refer to the description of the comparative example in FIG.

  In FIG. 1, a phase comparison circuit 40 compares the frequency and phase of a reference clock REFCLK given from the outside with CLKOUT, which is an output clock signal of the entire delay control circuit 100, and based on the result, a control signal UPB and DN are output.

  The charge pump circuit 10 charges and discharges from the current input / output terminal CIO based on the logic levels of the control signals UPB and DN. FIG. 4 is a circuit block diagram showing the configuration of the charge pump circuit 10. The charge pump circuit 10 includes a charging circuit 15 and a discharging circuit 16. The configuration itself of the charge pump circuit 10 is the same as that of the comparative example shown in FIG.

  The current input / output terminal CIO of the charge pump circuit 10 is connected to the loop filter 60. The loop filter 60 includes a fixed resistor Rz and a capacitor Cp connected in series between the current input / output terminal CIO and the power supply VSS. The fixed resistor Rz is a resistor for phase adjustment. Further, the terminal voltage (output voltage of the loop filter 60) VPMP of the current input / output terminal CIO filtered by the loop filter 60 is connected to the non-inverting input terminal INP of the regulator amplifier 50 serving as the power supply circuit of the delay circuit 20.

  The output terminal OUT of the regulator amplifier 50 serving as the power supply circuit of the delay circuit 20 is connected to the inverting input terminal INM. The regulator amplifier 50 is the current input / output terminal CIO filtered by the loop filter 60 input to the non-inverting input terminal INP. A voltage equal to the terminal voltage VPMP is output from the output terminal OUT. The output terminal OUT of the regulator amplifier 50 is connected to the power supply of the delay circuit 20 and supplies the power supply voltage VC to the delay circuit 20. The power supply voltage VC of the delay circuit 20 is substantially equal to the terminal voltage VPMP of the current input / output terminal CIO filtered by the loop filter 60. The operating current and output impedance of the regulator amplifier 50 are controlled by the second bias voltage Vbiasn given from the bias generation circuit 30. The internal circuit configuration of the regulator amplifier 50 will be described later. The same circuit as the regulator amplifier 32 shown in FIG. 3 can be used. However, while a fixed bias voltage is applied to the bias voltage input terminal Vbiasn of the regulator amplifier 32, the bias generation circuit 30 applies the output voltage of the loop filter 60 to the bias voltage input terminal Vbiasn of the regulator amplifier 50. The difference is that a bias voltage depending on the variation in mutual conductance of the PMOS transistor and the variation in mutual conductance of the NMOS transistor is applied.

  The delay circuit 20 includes a ring oscillator in which three inverter circuits are connected in a ring shape. This ring oscillator has its oscillation frequency controlled by the voltage value of the power supply voltage VC and functions as a voltage controlled oscillator VCO. The output signal of the delay circuit 20 constituting the ring oscillator is frequency-divided by the frequency-dividing circuit 41 and output to the outside as the output clock signal CLKOUT, and is also feedback-connected to the phase comparison circuit 40.

  The bias generation circuit 30 receives the output voltage VPMP of the charge pump circuit 10 and generates first and second bias voltages Vbiasp and Vbiasn to be supplied to the charge pump circuit 10 based on this voltage value. The second bias voltage Vbiasn is also supplied to the regulator amplifier 50 serving as the power supply for the delay circuit 20 to control the operating current and output impedance of the regulator amplifier 50.

  The bias generation circuit 30 includes a bias current generation circuit 31 that generates Ibias from the output voltage VPMP of the charge pump circuit 10 as a bias current. The bias current Ibias generated by the bias current generation circuit 31 is generated by the first to third current mirror circuits to generate the first bias voltage Vbiasp and the second bias voltage Vbiasn, and the charge / discharge current of the charge pump circuit 10 and the regulator amplifier The control of 50 operating current and output impedance is basically the same as the adaptive bias PLL circuit 900 of the comparative example of FIG.

  Of the first to third current mirror circuits, the first current mirror circuit includes PMOS transistors MP2 and MP3. The second current mirror circuit includes the NMOS transistors MN5 and MN6 of the bias generation circuit 30, the NMOS transistor MN12 (see FIG. 4) of the charge pump circuit 10, and the current source transistor of the regulator amplifier 50 (corresponding to the NMOS transistor MN9 of FIG. 3). ) Is included. The third current mirror circuit includes a PMOS transistor MP4 of the bias generation circuit 30 and a PMOS transistor MP9 (see FIG. 4) of the charge pump circuit 10.

  FIG. 2 is a circuit block diagram illustrating an example of the configuration of the bias current generation circuit 31. The bias current generation circuit 31 includes a regulator amplifier 32 that receives the output voltage VPMP of the charge pump circuit 10 and outputs a voltage proportional thereto. The output voltage VPMP of the charge pump circuit 10 is input to the non-inverted signal input terminal INP of the regulator amplifier 32, and the inverted signal input terminal INM of the regulator amplifier 32 is connected to the output terminal OUT. The bias voltage input terminal Vbiasn of the regulator amplifier 32 is supplied with a fixed bias voltage that does not depend on the power supply voltage VDD and the output voltage VPMP of the charge pump circuit 10. As a circuit for providing such a fixed bias voltage, a known reference voltage generating circuit as described in Patent Document 1 can be used.

  In FIG. 2, the regulator amplifier 32 outputs a voltage equal to the output voltage VPMP of the charge pump circuit 10 input to the non-inverted signal input terminal INP from the output terminal OUT. Therefore, when the voltage at the output terminal OUT is VPMPMIR, the voltage value of VPMPMIR is substantially equal to the voltage value of VPMP.

  The output terminal OUT of the regulator amplifier 32 is connected to the source of the PMOS transistor MP1 serving as the first current source transistor. Since the gate of the PMOS transistor MP1 is connected to the power supply VSS, "-VPMP" in which the sign of the voltage VPMP is inverted is applied between the gate and source of the PMOS transistor MP1 when the voltage of the power supply VSS is 0V. Is done. That is, when the PMOS transistor MP1 is considered as a current source transistor, since the gate potential is fixed, a bias voltage for controlling the current output from the drain is given to the source by the voltage applied to the source of the PMOS transistor MP1. Can be considered. The bias voltage applied to this source is substantially equal to the output voltage VPMP of the charge pump circuit 10.

  Here, the first current source transistor PMOS transistor MP1 is controlled such that when the voltage VPMP increases, the drain current increases, and when the voltage VPMP decreases, the drain current decreases.

  The drain of the PMOS transistor MP1 is connected to the gate and drain of the NMOS transistor MN3 and the gate of the NMOS transistor MN4. The sources of the NMOS transistors MN3 and MN4 are both connected to the power supply VSS. The NMOS transistors MN3 and MN4 form a current mirror circuit, and output a current equal to the current output from the drain of the PMOS transistor MP1 from the drain of the NMOS transistor MN4. However, since the current flows out from the drain of the PMOS transistor MP1 and the current flows into the drain of the NMOS transistor MN4, the current flows in the opposite direction.

  The source of the NMOS transistor MN2 is connected to the power supply VSS, and the drain is connected to the source of the NMOS transistor MN1. Further, the output voltage VPMP of the charge pump circuit 10 is supplied to the gates of the NMOS transistors MN1 and MN2. The NMOS transistors MN1 and MN2 function as a second current source transistor as a whole. When the voltage of the power supply VSS is set to 0 V, the current flowing through the drain of the NMOS transistor MN1 is controlled by the voltage VPMP applied to the gate. The

  Further, the drain of the NMOS transistor MN1 is connected to the drain of the NMOS transistor MN4 and is connected to the bias current output terminal of the bias current generating circuit 31. That is, the current flowing through the drain of the NMOS transistor MN4 and the current flowing through the drain of the NMOS transistor MN1 are added here to generate a bias current Ibias. Since the current flowing through the drain of the NMOS transistor MN4 is equal to the current flowing through the first current source transistor MP1, which is a PMOS transistor, the current flowing through the first current source transistor of the PMOS here and the second current source of the NMOS The currents flowing through the transistors are added to form a bias current Ibias and output from the bias current generation circuit 31.

  Here, let gmp be the mutual conductance of the PMOS first current source transistor MP1, and let gmn be the mutual conductance of the NMOS second current source transistor MN1 + MN2. Since it can be considered that a common bias voltage VPMP is applied to both the first current source transistor MP1 and the second current source transistor MN1 + MN2, when the input voltage VPMP changes in the bias current generation circuit 31 The change in the output current Ibias is expressed by Expression (1).

ΔIbias = gmp * ΔVPMP + gmn * ΔVPMP
= ΔVPMP * (gmp + gmn) Equation (1)

  That is, when considering the bias current generation circuit 31 as a whole, the output current change ΔIbias with respect to the input voltage change ΔVPMP of the bias current generation circuit 31 as a whole is the sum of the mutual conductance gmp of the PMOS transistor MP1 and the mutual conductance gmn of the NMOS transistor MN1 + MN2. Is equal to However, since it is necessary to reverse the direction in which the bias voltage is applied between the PMOS transistor and the NMOS transistor, when the bias voltage VPMP is applied to the PMOS transistor MP1, the regulator amplifier 32 is used to substantially bias the source of the PMOS transistor MP1. A voltage equal to the voltage VPMP is applied, and the gate is connected to a fixed potential (power supply VSS as an example). Further, in order to reverse the direction of current flow, the current flow direction is reversed using a current mirror circuit composed of NMOS transistors MN3 and MN4, the current flowing to the drain of the PMOS transistor MP1, and the drain of the NMOS transistor MN1 + MN2 Is added to generate a bias current Ibias.

  Next, FIG. 3 is a circuit block diagram showing an example of the configuration of the regulator amplifier 32. The NMOS transistor MN9 is a transistor that serves as a current source for the NMOS transistors MN7 and MN8 constituting the differential pair. The source of the NMOS transistor MN9 is connected to the power supply VSS, and the bias voltage Vbias is connected to the gate.

  Further, the sources of NMOS transistors MN7 and MN8 forming a differential pair are connected to the drain of the NMOS transistor MN9. The gate of the NMOS transistor MN7 is connected to the inverted signal input terminal INM, and the gate of the NMOS transistor MN8 is connected to the non-inverted signal input terminal INP.

  The drain of the NMOS transistor MN7 is connected to the gate and drain of the PMOS transistor MP5 serving as a load circuit, and is connected to the gate of the PMOS transistor MP6. The sources of the PMOS transistors MP5 and MP6 are both connected to the power supply VDD.

  The drain of the other NMOS transistor MN8 of the differential pair is connected to the gate and drain of a PMOS transistor MP7 serving as a load circuit, and the drain of the NMOS transistor MN8 is further connected to the gate of the PMOS transistor MP8 serving as an output transistor of the regulator amplifier 32. It is connected. The sources of the PMOS transistors MP7 and MP8 are both connected to the power supply VDD.

  The drain of the PMOS transistor MP6 is connected to the gate and drain of the NMOS transistor MN10 and to the gate of the NMOS transistor MN11 that serves as the output transistor. The sources of the NMOS transistors MN10 and MN11 are connected to the power supply VSS. The drains of the NMOS transistor MN11 and the PMOS transistor MP8, which are push-pull output transistors, are connected to the output terminal OUT.

[Effect of the first embodiment]
FIG. 6 shows variations in characteristics (CASE A to CASE D) of the PMOS transistor and the NMOS transistor constituting the circuit and the VCO control voltage (left axis) in the delay control circuit (adaptive bias type PLL circuit) 100 of the first embodiment. And the variation (right axis) in the magnitude of the bias current flowing through the charge pump circuit and the like. Since the four cases CASE A to CASE D are the same as those in FIG. Similar to FIG. 5, the variation in the threshold value of the transistor is an example of the variation in the mutual conductance of the transistor.

  Since the circuit configuration of the delay circuit 20 is not different from the comparative example of FIG. 9, the VCO control voltage is equal to the threshold value (transconductance) of the transistor even if the delay time of the delay circuit (the oscillation frequency of the VCO) is the same. It is influenced and varies. That is, the control voltage is the lowest in the case of CASE A where the threshold values of the PMOS transistor and the NMOS transistor are both low (both the mutual conductance is high). On the contrary, the control voltage is highest in the case of CASE D where both the threshold values of the PMOS transistor and the NMOS transistor are high (both the mutual conductance is low). As in CASE B and CASE C, when one of the PMOS transistor and the NMOS transistor is high and the other is low, the control voltage has an intermediate level.

  However, in the delay control circuit 100 of the first embodiment, based on the sum of the mutual conductance of the PMOS transistor and the mutual conductance of the NMOS transistor, the VCO control voltage (actually the output voltage VPMP of the charge pump circuit 10 and the VCO control voltage VC itself) VPMP is substantially equal to the VCO control voltage VC) to a bias current Ibias. Therefore, when the bias current generation circuit 31 generates the bias current Ibias from the voltage VPMP corresponding to the VCO control voltage VC, the unbalanced variation in the mutual conductance (for example, transistor threshold) of the PMOS transistor and the NMOS transistor is corrected. Even if there is an unbalanced variation in transistors, an almost constant optimum bias current can be generated.

  In the manufacturing process of a semiconductor integrated circuit, the threshold voltage Vth of the transistor has the greatest effect on the variation in mutual conductance of the MOS transistor. Therefore, from the viewpoint of fluctuations in the threshold value Vth, the first embodiment is summarized as follows.

  The control voltage VPMP (= VC) of the PLL is proportional to the internal delay of the VCO. Since the internal delay of the VCO is determined by Td = Cload * Ron, and Ron can be considered as the on resistance of the PMOS and NMOS of the inverter constituting the VCO, the equations (2) and (3) are established.

VC (= VPMP) ∝Ronp∝1 / (Wmvp / Lmvp * (VC-Vthp) Equation (2)

VC (= VPMP) ∝Ronn∝1 / (Wmvn / Lmvn * (VC-Vthp) Equation (3)

  In equation (2), Wmvp and Lmvp are the channel width and channel length of the PMOS transistor of the VCO circuit, respectively. In Equation (3), Wmvn and Lmvn are the channel width and channel length of the NMOS transistor of the VCO circuit, respectively.

  From the equations (2) and (3), the power supply voltage VC of the VCO circuit has the threshold Vth dependency of the NMOS transistor and the PMOS transistor. On the other hand, the basic bias current Ibias generated by the bias current generation circuit 31 is expressed by the following equation (4).

Ibias∝Wmn1 / Lmn1 * (VPMP-Vthn) ² + Wmp1 / Lmp1 * (VPMP-Vthp) ² formulas (4)

  In Expression (4), Wmn1 and Lmn1 are the channel width and channel length of the NMOS transistor MN1 of the bias current generation circuit 31, respectively, and Wmp1 and Lmp1 are the channel width and channel length of the PMOS transistor MP1 of the bias current generation circuit 31, respectively. is there.

  From the above equation (4), the basic bias current Ibias depends on the threshold value Vthn of the NMOS transistor and the threshold value Vthp of the PMOS transistor.

  From the above expressions (2) and (3), the voltage VC increases as Vthn and Vthp increase. From equation (4), Ibias decreases as either Vthn or Vthp increases. Therefore, fluctuations in the bias current are suppressed by causing Ibias to fluctuate in conjunction with fluctuations in the voltage VC with respect to Vth fluctuations in the NMOS transistor and the PMOS transistor.

[Second Embodiment]
FIG. 7 is a block diagram of the entire delay control circuit according to the second embodiment. Similarly to the delay control circuit 100 according to the first embodiment, the delay control circuit 100A according to the second embodiment shown in FIG. 7 is also based on the output voltage of the charge pump circuit 10 (substantially the power supply voltage of the voltage controlled oscillator VCO). An adaptive bias type PLL circuit that controls the bias current. The delay control circuit 100A according to the second embodiment includes the second charge pump circuit 11 in addition to the first charge pump circuit 10, and the circuit configuration inside the loop filter (low-pass filter) 60A is different. ing. Other configurations are the same as the configuration and operation of the delay control circuit 100 of the first embodiment. Therefore, the same portions are denoted by the same reference numerals, and redundant description is omitted.

  The second charge pump circuit 11 has the same internal configuration as the first charge pump circuit 10, and the input signal connection is also common to the first charge pump circuit 10. Accordingly, the description of the internal configuration and the operation of the second charge pump circuit 11 will not be repeated.

  The loop filter (low-pass filter) 60A includes a first capacitor Cp, a second capacitor Cz, and a zero point adjustment amplifier 61. The first capacitor Cp has one end connected to the current input / output terminal CIO of the first charge pump circuit 10 and the other end connected to the power supply VSS.

  In the zero point adjustment amplifier 61, the non-inverting input terminal INP is connected to the current input / output terminal CIO of the first charge pump circuit 10, and the inverting input terminal INM is the current of the output terminal OUT and the second charge pump circuit 11. It is connected to the input / output terminal CIO2. The second capacitor Cz has one end connected to the output terminal OUT of the zero point adjustment amplifier 61 and the other end connected to the power supply VSS.

  The bias voltage input terminal Vbiasn of the zero point adjustment amplifier 61 is supplied with the second bias voltage Vbiasn from the bias generation circuit 30. As an internal circuit of the zero point adjusting amplifier 61, a differential amplifier circuit having the same configuration as that of the regulator amplifier 32 shown in FIG. 3 can be used.

  The zero point adjusting amplifier 61 is a phase adjusting amplifier. The value of the output impedance changes according to the bias voltage Vbiasn given from the bias generation circuit 30. In the first embodiment, the resistor Rz provided for phase adjustment is a fixed resistor. In the second embodiment, the bias generator 30 optimizes the resistance Rz according to the oscillation frequency of the VCO. Therefore, a more stable PLL control loop characteristic can be obtained over a wide range of the oscillation frequency of the VCO.

[Third Embodiment]
FIG. 8 is a block diagram of the entire delay control circuit according to the third embodiment. The delay control circuit 100B of FIG. 8 is an adaptive bias type DLL circuit that controls the bias current of the DLL control loop based on the output voltage VPMP of the charge pump circuit 10 (substantially the power supply voltage VC of the delay circuit 20A). .

  The delay control circuit 100B of the third embodiment is the same in basic configuration as the delay control circuit 100 of the first embodiment, except that the control loop is a PLL or a DLL. Accordingly, parts that are the same as those of the delay control circuit 100 of the first embodiment are given the same reference numerals, and redundant descriptions are omitted. In the case of the PLL circuit 100, the delay circuit 20 is self-excited by inverting the phase of the output of the final stage for a plurality of cascaded inverter circuits and inputting it to the first stage, but in the DLL circuit 100B, The reference clock signal REFCLK is externally connected as an input clock signal of the first stage of the delay elements of the cascaded delay circuit 20A, the phase of the reference clock signal REFCLK is delayed by the delay circuit 20A, and the waveform is shaped by the waveform shaping circuit 21. The output clock signal is generated and input to the phase comparison circuit 40. Other configurations are the same as those of the first embodiment.

  In other words, the application of the delay control circuit according to the present invention is not limited to the PLL circuit, but can be applied to the DLL circuit, and the mutual conductance between the first conductivity type transistor and the second conductivity type transistor is the same. Even when there is a variation in imbalance, it is possible to give an optimum bias according to the frequency of the clock signal to the DLL control system such as the charge pump circuit.

[Modification of each embodiment]
In the first to third embodiments, the PMOS transistors MVP0, MVP1, MVP2, and the NMOS transistors MVN0, MVN1, MVN2 included in the PMOS transistor MP1, NMOS transistor MN1, delay circuits 20, 20A of the bias current generation circuit 31 of FIG. Alternatively, a depletion type MOS transistor can be used. By using a depletion type transistor, the transistor can always be operated in a saturation region. By operating the transistor in the saturation region, the relationship between the output voltage VPMP of the charge pump circuit 10 and the bias current can be made linear.

  Further, the delay control circuit of the present invention is not necessarily limited to a delay control circuit having a feedback loop such as a PLL circuit or a DLL circuit, and receives a control signal UPB, DN from the outside and delays the delay time by a charge pump circuit. It is also possible to apply to a delay control circuit to be controlled. Further, any charge pump circuit that charges and discharges using the first conductivity type transistor and the second conductivity type transistor can be applied to a charge pump circuit that does not control the delay time. When the present invention is applied to a CMOS circuit, when the voltage value of the power supply VDD is higher than the voltage value of the power supply VSS, a PMOS transistor is used as the first conductivity type transistor and an NMOS transistor is used as the second conductivity type transistor. However, when the voltage value of the power supply VDD is lower than the voltage value of the power supply VSS, it is preferable to use an NMOS transistor as the first conductivity type transistor and a PMOS transistor as the second conductivity type transistor. Furthermore, although a CMOS circuit is shown as a preferred embodiment, the first conductivity type transistor, such as a PNP transistor or an NPN transistor, and / or the second conductivity type transistor, other than the PMOS transistor and the NMOS transistor, are used. It is also possible to use a transistor.

  The present invention is applicable to a circuit including a charge pump using a first conductivity type transistor and a second conductivity type transistor.

  Within the scope of the entire disclosure (including claims and drawings) of the present invention, the examples and the examples can be changed and adjusted based on the basic technical concept. In addition, various combinations or selections of various disclosed elements are possible within the scope of the claims of the present invention. That is, the present invention naturally includes various modifications and changes that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea.

10, 11: Charge pump circuit 15: Charge circuit 16: Discharge circuit 20: Delay circuit (ring oscillator: voltage controlled oscillator)
20A: delay circuit 21: waveform shaping circuit (inverter)
30, 930: Bias generation circuit 31: Bias current generation circuit 32: Regulator amplifier 40: Phase comparison circuit 41: Frequency divider circuit 50: Regulator amplifier (power supply circuit of delay circuit)
60, 60A: Low-pass filter (loop filter)
61: Zero point adjustment amplifier 100, 100A: Delay control circuit (PLL circuit)
100B: DLL circuit (delay control circuit)
900: Adaptive bias type PLL circuit CIO, CIO2: Current input / output terminals Cp, Cz: Capacitance Rz: Resistance MP1 to MP8, MVP0 to MVP2: PMOS transistor MP9: PMOS transistor (charging transistor: current source transistor)
MP10: PMOS transistor (discharge transistor: current source transistor)
MN1 to MN13, MN21, MN22, MVN0 to MVN2: NMOS transistor CLKOUT: output clock signal REFCLK: reference clock signal

Claims (20)

A charge pump circuit that receives a predetermined signal and charges and discharges from a current input / output terminal;
A delay circuit to which a voltage based on the terminal voltage of the current input / output terminal is supplied as a power supply;
A bias generation circuit that applies a bias voltage serving as a reference of charge / discharge current to the charge pump circuit;
With
The charge pump circuit and the delay circuit each include a first conductivity type transistor and a second conductivity type transistor having a conductivity type different from that of the first conductivity type transistor,
The delay control circuit, wherein the bias generation circuit generates the bias voltage based on a sum of a mutual conductance of the first conductivity type transistor and a mutual conductance of the second conductivity type transistor. The bias generation circuit includes:
A first conductivity type reference current generating transistor to which the terminal voltage of the current input / output terminal is applied as a bias voltage; and a second conductivity type reference current generating transistor to which the terminal voltage of the current input / output terminal is applied as a bias voltage. A bias current generation circuit that generates a bias current by adding a current flowing through the first conductivity type reference current generation transistor and a current flowing through the second conductivity type reference current generation transistor;
Based on the current value of the bias current, a first bias voltage applied to the first conductivity type transistor of the charge pump circuit and a second bias voltage applied to the second conductivity type transistor of the charge pump circuit, A bias voltage generation circuit for generating a bias voltage;
The delay control circuit according to claim 1, comprising: The charge pump circuit
A first-conductivity-type current source transistor in which the magnitude of a current flowing when the first bias voltage is applied is controlled;
A second conductivity type current source transistor in which the magnitude of the current flowing when the second bias voltage is applied is controlled;
The first conductive type current source transistor is connected in series between the first power source and the current input / output terminal, and conduction / non-conduction is controlled by the first predetermined signal. A first conductivity type switch transistor for passing a current controlled in magnitude by a one conductivity type current source transistor between the first power source and the current input / output terminal;
The second conductive type current source transistor is connected in series between a second power source and the current input / output terminal, and conduction / non-conduction is controlled by the second predetermined signal. A second conductivity type switch transistor for passing a current controlled in magnitude by a two conductivity type current source transistor to the second power source and the current input / output terminal;
The delay control circuit according to claim 2, further comprising: The bias current generation circuit includes:
A regulator amplifier that inputs a terminal voltage of the current input / output terminal and outputs a voltage proportional to the terminal voltage;
A current mirror circuit,
The first conductivity type reference current generating transistor has a source connected to the output terminal of the regulator amplifier, a gate connected to a fixed potential, and a drain connected to a current input terminal of the current mirror circuit,
The second conductivity type reference current generating transistor inputs a terminal voltage of the current input / output terminal to a gate, a source is connected to the second power supply, and a drain is connected to a current output terminal of the current mirror circuit. To generate the bias current,
4. The delay control circuit according to claim 3, wherein the bias voltage generation circuit converts the bias current into a current voltage to generate the first bias voltage and the second bias voltage.   A regulator amplifier that inputs an output voltage of the charge pump circuit and outputs a voltage proportional thereto; and further includes a power supply circuit of the delay circuit that supplies the output voltage of the regulator amplifier as a power supply of the delay circuit. 5. The delay control circuit according to claim 1, wherein the delay control circuit is characterized in that: A low-pass filter connected to the current input / output terminal;
6. The delay control circuit according to claim 5, wherein the power supply circuit of the delay circuit supplies power to the delay circuit based on an output voltage of the charge pump circuit filtered by the low-pass filter.   The delay control circuit according to claim 6, wherein the low-pass filter includes a resistor and a capacitor connected in series between the current input / output terminal and ground. A second charge pump circuit connected in parallel with the first charge pump circuit when the charge pump circuit is a first charge pump circuit;
The low-pass filter is
A first capacitor connected between the current input / output terminal of the first charge pump and ground;
The current input / output terminal of the first charge pump circuit is connected to a non-inverting input terminal, the current input / output terminal of the second charge pump circuit is connected to an inverting input terminal and an output terminal, and the bias generation circuit An amplifier for zero point adjustment in which a bias voltage is applied and output resistance is controlled;
A second capacitor connected between the output terminal of the zero point adjustment amplifier and the ground;
The delay control circuit according to claim 6, further comprising:   9. The method according to claim 1, further comprising a phase comparison circuit that compares phases of an output signal of the delay circuit and a reference clock signal and generates the predetermined signal based on a comparison result. The delay control circuit according to claim 1. The delay circuit is a ring oscillator in which a plurality of delay elements are connected in cascade, and the phase of the output stage is inverted and connected to the input of the first stage,
10. The delay control circuit according to claim 9, wherein the delay control circuit is a PLL circuit that controls an oscillation frequency and a phase of the ring oscillator so that the ring oscillator oscillates in synchronization with the reference clock signal. . The delay circuit is a delay circuit that inputs the reference clock signal and delays and outputs the phase of the reference clock signal;
The delay control circuit according to claim 9, wherein the delay control circuit is a DLL circuit.   12. The delay control circuit according to claim 1, wherein one of the first conductivity type transistor and the second conductivity type transistor is a PMOS transistor and the other is an NMOS transistor.   The first conductive type reference current generating transistor, the second conductive type reference current generating transistor, and the first conductive type transistor and the second conductive type transistor included in the delay circuit are all depletion type field effect transistors. 13. The delay control circuit according to claim 1, wherein the delay control circuit is provided.   The bias generation circuit compensates for variations in output voltage of the charge pump circuit due to variations in mutual conductance between the first conductivity type transistor and the second conductivity type transistor when the delay time of the delay circuit is constant. 14. The delay control circuit according to claim 1, wherein the bias voltage is controlled so as to flow a current that depends on a delay time of the delay circuit. A charging circuit for charging a current flowing through the first conductivity type charging transistor in response to a first signal from a current input / output terminal;
A discharge circuit for discharging a current flowing through the second conductivity type discharge transistor in response to a second signal from the current input / output terminal;
The charging transistor and the charge transistor are configured such that the value of the discharge current is equal to the value of the charging current, and the current value is proportional to the sum of the mutual conductance of the first conductivity type transistor and the mutual conductance of the second conductivity type transistor. A bias generation circuit for applying a bias voltage to the discharge transistor;
A charge pump circuit comprising: The bias generation circuit includes:
A first conductivity type reference current generating transistor to which the terminal voltage of the current input / output terminal is applied as a bias voltage; and a second conductivity type reference current generating transistor to which the terminal voltage of the current input / output terminal is applied as a bias voltage. A bias current generation circuit that generates a bias current by adding a current flowing through the first conductivity type reference current generation transistor and a current flowing through the second conductivity type reference current generation transistor;
A first current mirror circuit for passing a current proportional to the bias current to the charging transistor;
A second current mirror circuit for flowing a current proportional to the bias current to the discharge transistor;
16. The charge pump circuit according to claim 15, further comprising: The bias current generation circuit includes:
A regulator amplifier that inputs a terminal voltage of the current input / output terminal and outputs a voltage proportional to the terminal voltage;
A third current mirror circuit having a current input terminal connected to the drain of the first conductivity type reference current generating transistor and a current output terminal connected to the output terminal of the bias current;
Further comprising
The first conductivity type reference current generating transistor has a source connected to the output terminal of the regulator amplifier and a gate connected to a fixed potential,
The second conductivity type reference current generating transistor inputs a terminal voltage of the current input / output terminal to a gate, a source is connected to a fixed potential via a load circuit, and a drain is a current output of the third current mirror circuit The bias current is generated by adding a current flowing through the first conductivity type reference current generation transistor and a current flowing through the second conductivity type reference current generation transistor, connected to an end, and generating the bias current. Charge pump circuit. The charging circuit is
A first conductivity type switch transistor connected in series with the charging transistor between a first power source and the current input / output terminal and receiving the first signal to control conduction / non-conduction;
The discharge circuit is
The discharge transistor is connected in series between a second power source and the current input / output terminal,
18. The charge pump circuit according to claim 15, further comprising a second conductivity type switch transistor that receives the second signal and controls conduction and non-conduction. 18. A phase comparison circuit configured by CMOS circuits each having a PMOS transistor and an NMOS transistor, a charge pump circuit, and a voltage control oscillation circuit, and the phase comparison circuit externally transmits an oscillation clock of the voltage control oscillation circuit. In a PLL circuit that compares a given reference clock with an oscillation frequency and a phase, and charges and discharges a power source that the charge pump circuit supplies to the voltage controlled oscillation circuit based on the comparison result,
Generating a reference current based on the sum of the transconductance of the PMOS transistor and the transconductance of the NMOS transistor;
Based on the value of the reference current, the charge current of the charge pump circuit and the discharge current are controlled to be constant,
A charge / discharge current control method for a charge pump circuit. Generating the reference current comprises:
A voltage proportional to a potential difference between a power supply voltage and a fixed potential applied to the voltage controlled oscillation circuit is applied between the gate source of the PMOS transistor and converted into a drain current of the PMOS transistor;
Applying a voltage proportional to the power supply voltage applied to the voltage controlled oscillation circuit to the gate of the NMOS transistor to convert it to the drain current of the NMOS transistor;
Adding the drain current of the PMOS transistor and the drain current of the NMOS transistor to generate the reference current;
With
The step of controlling the charging current and the discharging current to be constant,
Flowing a charging current proportional to the reference current when flowing the charging current;
Flowing the discharge current proportional to the reference current when flowing the discharge current;
20. The charge / discharge current control method for a charge pump circuit according to claim 19, further comprising:

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