JP2010273386A - Voltage controlled oscillator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage controlled oscillator which can suppress variation in oscillation frequency. <P>SOLUTION: The voltage controlled oscillator includes N (N is an integer of ≥2) pieces of inverted differential amplifiers (9) connected in series. Each of the N pieces of inverted differential amplifiers (9) operates in accordance with the constant voltage (V<SB>cn1</SB>) and the control voltage (V<SB>cnt</SB>) of predetermined voltage values. The operating current of each of the N pieces of inverted differential amplifiers (9) is directly determined from a current value obtained by adding a current corresponding to the constant voltage (V<SB>cn1</SB>) to a current corresponding to the control voltage (V<SB>cnt</SB>). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a voltage controlled oscillator, and more particularly to a voltage controlled oscillator that can suppress variation in oscillation frequency.

  A general voltage controlled oscillator (VCO) generates an output signal that oscillates at a frequency corresponding to a voltage supplied from the outside, and is used in various fields such as information processing and communication. A conventional voltage controlled oscillator (VCO) will be described with reference to FIG. FIG. 12 is a circuit diagram showing a configuration of a conventional voltage controlled oscillator (VCO).

  As shown in FIG. 12, the conventional voltage controlled oscillator (VCO) 105 includes a bias generator (BG) 108, a ring oscillator (RO) 109, and a level converter (LC) 107.

A constant voltage V _cn1 and a voltage V _cnt having predetermined voltage values are supplied / input to the bias generator (BG) 108 from the outside. Further, a power supply voltage is supplied / input from the outside to the bias generator (BG) 108 and the ring oscillator (RO) 109. The output of the bias generator (BG) 108 is supplied / input to the ring oscillator (RO) 109.

The ring oscillator (RO) 109 includes N inverting differential amplifiers. Here, N is an integer of 2 or more. Each of the N inverting differential amplifiers adds a current I _cn1 corresponding to the value of the constant voltage V _cn1 supplied to the bias generator (BG) 108 and a current I _cnt corresponding to the value of the voltage V _cnt . Operates with current. Each of the operating current of the N inverting differential amplifier includes a current _{I cn1} corresponding to the value of the constant voltage _{V cn1} by a bias generator (BG) 108, the sum of the current _{I cnt} corresponding to the value of the voltage _{V cnt} Indirectly determined by current. The bias generator (BG) 108 compensates for the operating current of the ring oscillator (RO) 109. Compensation means that when a transistor acting as a switch of the ring oscillator (RO) 109 is ON / OFF, a current is passed quickly, and the rising and falling of the oscillation waveform are operated at high speed (to make it steep) and oscillate at high speed. To encourage This compensation can improve the high frequency characteristics, that is, improve the followability.

The ring oscillator (RO) 109 gives an offset frequency by the constant voltage V _cn1 and controls the oscillation frequency determined in proportion to the voltage V _cnt to determine a desired oscillation frequency. The desired oscillation frequency is indirectly obtained by adding a current I _cn1 corresponding to the value of the constant voltage V _cn1 supplied to the bias generator (BG) 108 and a current I _cnt corresponding to the value of the voltage V _cnt. Determined. The ring oscillator (RO) 109 receives one of the maximum voltage V _OUT1 representing the maximum peak and the minimum voltage V _OUT2 representing the minimum peak among the amplitude of the voltage corresponding to the determined desired oscillation frequency via the first output terminal OUT1. _Is supplied to the level converter (LC) 107, and the other of the maximum voltage V _OUT1 and the minimum voltage V _OUT2 is supplied to the level converter (LC) 107 via the second output terminal OUT2.

The level converter (LC) 107 increases the amplitude between the minimum voltage V _OUT2 and the maximum voltage V _OUT1 to a CMOS level (for example, from 0 (V) to a power supply voltage), and outputs an output signal. _{Create an} F _VCO . The output signal F _VCO generated by the level converter (LC) 107 is sent to the outside as an output signal of the voltage controlled oscillator (VCO) 105.

Here, the oscillation frequency corresponding to the output signal F _VCO generated by the voltage controlled oscillator (VCO) 105 will be described. FIG. 14 is a diagram illustrating the relationship between the output signal F _VCO and the voltage V _cnt .

As shown in FIG. 14, reference numeral X _{<b> 1} indicating the relationship (frequency characteristic) between the output signal F _VCO and the voltage V _cnt that is normally generated by the voltage controlled oscillator (VCO) is included in the voltage controlled oscillator (VCO) 105. When the voltage V _cnt becomes larger than a threshold voltage V _a101 of a transistor to be described later, the linearity is such that the oscillation frequency of the output signal F _VCO becomes larger than 0 (Hz). The voltage controlled oscillator (VCO) 105 controls the oscillation frequency determined in proportion to the voltage V _cnt in the range from the threshold voltage V _a101 to the external power supply voltage V _DD that operates the voltage controlled oscillator (VCO) 105. _Is determined. At this time, a voltage for obtaining a desired oscillation frequency F _b101 corresponding to the output signal F _VCO is V _b101 (V _a101 <V _b101 <V _DD ).

However, when the voltage V _b101 fluctuates due to external noise component interference, the slope of the frequency characteristic indicated by the symbol X1 is steep, so that the desired oscillation frequency F _b101 varies depending on the slope of the frequency characteristic. Increased (jitter increases).

In order to suppress the large fluctuation of the oscillation frequency _Fb101 , the voltage controlled oscillator (VCO) 105 has an offset frequency by adding a current corresponding to the constant voltage _Vcn1 by the bias generator (BG) 108. The frequency characteristic indicated by the reference sign Y101, which has a frequency characteristic indicated by the reference sign X1 that has a gentle slope, by making the frequency F _a101 greater than 0 (Hz) and smaller than the desired frequency F _{b101 a} reference frequency (self-running oscillation frequency). Can be generated.

  Next, the configuration of the bias generator (BG) 108 and the ring oscillator (RO) 109 of the conventional voltage controlled oscillator (VCO) 105 when N is an even number equal to or greater than 2 will be described in detail with reference to FIG. To do.

  As shown in FIG. 12, the bias generator (BG) 108 includes an adder circuit 108a and a mirror circuit 108b. The adder circuit 108a has a P-channel MOS transistor 111 and N-channel MOS transistors 112 and 113. The mirror circuit 108b has a P-channel MOS transistor 114 and an N-channel MOS transistor 115. Hereinafter, the P channel MOS transistor is referred to as a PMOS transistor, and the N channel MOS transistor is referred to as an NMOS transistor. In addition, the mirror circuit or the current mirror circuit means that, for example, the second transistor connected to the first transistor is supplied with the same current as or proportional to the current flowing through the first transistor (1/2 times, 2 times, etc.). When the current flowing through the first transistor increases, the current flowing through the second transistor also increases proportionally. The same current as or proportional to the current flowing through the first transistor is called a mirror current.

  First, the configuration of the adder circuit 108a will be described.

A high-order power supply is connected to the source electrode of the PMOS transistor 111, and the power supply voltage V _DD is input / supplied. The drain electrode of the PMOS transistor 111 is connected to the drain electrodes of the NMOS transistors 112 and 113. A constant voltage _Vcn1 is input / supplied to the gate electrode of the NMOS transistor 112 from the outside. The source electrode of the NMOS transistor 112 is connected to the lower power supply and is usually grounded. A voltage V _cnt is input / supplied to the gate electrode of the NMOS transistor 113 from the outside. The source electrode of the NMOS transistor 113 is connected to the lower power supply and is usually grounded.

  Next, the configuration of the mirror circuit 108b will be described.

A high-side power supply is connected to the source electrode of the PMOS transistor 114, and the power supply voltage V _DD is input / supplied. The gate electrode of the PMOS transistor 114 is connected to the drain electrode of the PMOS transistor 111. The drain electrode of the NMOS transistor 115 is connected to the drain electrode of the PMOS transistor 114. The source electrode of the NMOS transistor 115 is connected to the lower power supply and is normally grounded.

  Next, the configuration of the ring oscillator (RO) 109 will be described.

  As shown in FIG. 12, the ring oscillator (RO) 109 includes a first inverting differential amplifier 109a, a second inverting differential amplifier 109b, a third inverting differential amplifier 109c, and a fourth inverting differential amplifier 109d. Yes. Each of the first inverting differential amplifier 109a, the second inverting differential amplifier 109b, the third inverting differential amplifier 109c, and the fourth inverting differential amplifier 109d includes PMOS transistors 121, 122, 123, and 124, and NMOS transistors 125 and 126, respectively. 129.

  The configuration of each of the first inverting differential amplifier 109a, the second inverting differential amplifier 109b, the third inverting differential amplifier 109c, and the fourth inverting differential amplifier 109d will be described.

The high-side power supply is connected to the source electrodes of the PMOS transistors 121, 122, 123, and 124, and the power supply voltage V _DD is input / supplied. The gate electrodes of the PMOS transistors 122 and 123 are connected to the drain electrode and the gate electrode of the PMOS transistor 111. Here, the PMOS transistors 122 and 123 are current mirror circuits with respect to the PMOS transistor 111. The gate electrode of the NMOS transistor 129 is connected to the drain electrode and the gate electrode of the NMOS transistor 115. The source electrode of the NMOS transistor 129 is connected to the lower power supply and is usually grounded. Here, the NMOS transistor 129 is a current mirror circuit with respect to the NMOS transistor 115. The drain electrode of the NMOS transistor 129 is connected to the source electrodes of the NMOS transistors 125 and 126. The drain electrode of the NMOS transistor 125 is connected to the drain electrodes of the PMOS transistors 121 and 122 and the gate electrode of the PMOS transistor 121. The drain electrode of the NMOS transistor 126 is connected to the drain electrodes of the PMOS transistors 123 and 124 and the gate electrode of the PMOS transistor 124.

  The gate electrode of the NMOS transistor 125 of the second inverting differential amplifier 109b is connected to the drain electrode of the NMOS transistor 125 of the first inverting differential amplifier 109a. The gate electrode of the NMOS transistor 126 of the second inverting differential amplifier 109b is connected to the drain electrode of the NMOS transistor 126 of the first inverting differential amplifier 109a.

  The gate electrode of the NMOS transistor 125 of the third inverting differential amplifier 109c is connected to the drain electrode of the NMOS transistor 125 of the second inverting differential amplifier 109b. The gate electrode of the NMOS transistor 126 of the third inverting differential amplifier 109c is connected to the drain electrode of the NMOS transistor 126 of the second inverting differential amplifier 109b.

  The gate electrode of the NMOS transistor 125 of the fourth inverting differential amplifier 109d is connected to the drain electrode of the NMOS transistor 125 of the third inverting differential amplifier 109c. The gate electrode of the NMOS transistor 126 of the fourth inverting differential amplifier 109d is connected to the drain electrode of the NMOS transistor 126 of the third inverting differential amplifier 109c.

  The gate electrode of the NMOS transistor 125 of the first inverting differential amplifier 109a is connected to the drain electrode of the NMOS transistor 126 of the fourth inverting differential amplifier 109d. The gate electrode of the NMOS transistor 126 of the first inverting differential amplifier 109a is connected to the drain electrode of the NMOS transistor 125 of the fourth inverting differential amplifier 109d. The drain electrode of the NMOS transistor 125 of the fourth inverting differential amplifier 109d is connected to the level converter (LC) 107 via the first output terminal OUT1. The drain electrode of the NMOS transistor 126 of the fourth inverting differential amplifier 109d is connected to the level converter (LC) 107 via the second output terminal OUT2.

Next, operations of the bias generator (BG) 108 and the ring oscillator (RO) 109 of the voltage controlled oscillator (VCO) 105 will be described with reference to FIG. Here, a reference level is biased to the constant voltage V _cn1 input to the voltage controlled oscillator (VCO) 105, and a control level is biased to the voltage V _cnt .

  First, the circuit operation of the addition circuit 108a of the bias generator (BG) 108 will be described.

As shown in FIG. 12, since the constant voltage V _cn1 is biased at the gate of the NMOS transistor 112, the drain current ID 112 corresponding to the bias flows. The control level is biased to the voltage V _cnt , but if the level is now 0 (V), the NMOS transistor 113 is OFF (because the threshold voltage has not been reached), so the drain current ID 113 is 0 (A). Accordingly, the drain current ID111 of the PMOS transistor 111 is the sum of the drain current ID112 and the drain current ID113, but since the drain current ID113 is 0 (A), only the drain current ID112 flows. Since the gate and the drain of the PMOS transistor are the same node, the PMOS transistor is in the saturation region, and the level of the gate is determined so that the drain current ID111 flows. This level is the same as that of the PMOS transistor 114 of the mirror circuit 108b, the first inverting differential amplifier 109a, the second inverting differential amplifier 109b, the third inverting differential amplifier 109c, and the fourth inverting differential amplifier 109d in the ring oscillator (RO) 109. The gate level of each of the PMOS transistors 122 and 123 is set. With respect to the PMOS transistor 111, the PMOS transistor 114 of the mirror circuit 108b, the first inverting differential amplifier 109a, the second inverting differential amplifier 109b, the third inverting differential amplifier 109c, and the fourth inverting difference in the ring oscillator (RO) 109. Since each of the PMOS transistors 122 and 123 of the dynamic amplifier 109d constitutes a current mirror circuit, the size of the PMOS transistor 111 (including the threshold value of the PMOS transistor 111, the gate length, and the thickness of the gate oxide film) , The current corresponding to the ratio of the sizes of the PMOS transistors 114, 122, 123 (including the threshold value of each PMOS transistor, the gate length, the thickness of the gate oxide film) is the drain of the PMOS transistors 114, 122, 123. It becomes current.

  Next, the circuit operation of the mirror circuit 108b of the bias generator (BG) 108 will be described.

  The drain current ID115 of the NMOS transistor 115 includes the size of the PMOS transistor 111 (including the threshold value, gate length, and thickness of the gate oxide film of the PMOS transistor 111) and the size of the PMOS transistor 114 (the threshold of the PMOS transistor 114). The drain current ID 114 of the PMOS transistor 114 flows in accordance with the ratio of the value, the gate length, and the thickness of the gate oxide film. Since the gate and the drain of the NMOS transistor 115 are the same node, the NMOS transistor 115 is in the saturation region, and the level of the gate is determined so that the drain current ID 115 flows. This level is the level of the gate of the NMOS transistor 129 of each of the first inverting differential amplifier 109a, the second inverting differential amplifier 109b, the third inverting differential amplifier 109c, and the fourth inverting differential amplifier 109d. For the NMOS transistor 115, the NMOS transistor 129 of each of the first inverting differential amplifier 109a, the second inverting differential amplifier 109b, the third inverting differential amplifier 109c, and the fourth inverting differential amplifier 109d constitutes a current mirror circuit. Therefore, the size of the NMOS transistor 115 (including the threshold value, gate length, and thickness of the gate oxide film of the NMOS transistor 115) and the size of the NMOS transistor 129 (threshold value, gate of each NMOS transistor) The current corresponding to the ratio of the length and the thickness of the gate oxide film becomes the drain current of the NMOS transistor 129.

When the control level voltage V _cnt increases and becomes equal to or higher than the threshold of the NMOS transistor 113 (a level at which the NMOS transistor 113 is turned on), the drain current ID113 of the NMOS transistor 113 flows. As the voltage V _cnt increases, the drain current ID113 of the NMOS transistor 113 also increases, and as a result, the drain current ID111 of the PMOS transistor 111 also increases. Therefore, the drain currents of the PMOS transistors 122 and 123 constituting the current mirror circuit and the drain current of the NMOS transistor 129 also increase.

  Next, the circuit operation of the ring oscillator (RO) 109 will be described. Here, since the circuit operation of each of the first inverting differential amplifier 109a, the second inverting differential amplifier 109b, the third inverting differential amplifier 109c, and the fourth inverting differential amplifier 109d is the same, the first inverting differential amplifier The amplifier 109a will be described as an example.

When the reference level is biased to the constant voltage V _cn1 input to the bias generator (BG) 108 and the voltage V _cnt is 0 level, the drain current ID 129 flows through the NMOS transistor 129 of the first inverting differential amplifier 109a. When the source electrodes of the NMOS transistors 125 and 126 are commonly connected to the drain electrode of the NMOS transistor 129, the drain current ID129 of the NMOS transistor 129 flows.

  The NMOS transistors 125 and 126 of the differential circuit operating as switches operate with the drain current ID129 of the NMOS transistor 129 described above. The NMOS transistors 125 and 126 pass drain currents ID125 and ID126 corresponding to the input signals (outputs from the fourth inverting differential amplifier 109d) and supply them to the PMOS transistors 121 and 124 which are active loads. When the NMOS transistor 125 is turned on and the NMOS transistor 126 is turned off, a current flows through the NMOS transistor 125 and a current also flows through the PMOS transistor 121. At this time, a voltage drop corresponding to the drain-source voltage VDS121 of the PMOS transistor 121 occurs, and the output of the NMOS transistor 125 (the input to the NMOS transistor 125 of the second inverting differential amplifier 109b) becomes the LOW level. Since the NMOS transistor 126 is OFF, the output of the NMOS transistor 126a (the input to the NMOS transistor 126 of the second inverting differential amplifier 109b) becomes HIGH level.

  The PMOS transistors 122 and 123 connected in parallel as the PMOS transistors of the active load have a mirror configuration with the bias generator (BG) 108, and when the mirror current flows, the NMOS transistors 125 and 126 are turned ON / OFF. Has the effect of flowing current quickly. The rise and fall of the output can be operated at high speed, and oscillation can be promoted at high speed.

When the level of the voltage V _cnt input to the bias generator (BG) 108 increases and the drain current ID129 of the NMOS transistor 129 of the first inverting differential amplifier 109 further flows, the circuit current of the first inverting differential amplifier 109a. Will increase. As the current increases, the drive capability of the circuit naturally increases, and the time for charging / discharging the output load (the gate capacitance and the wiring capacitance of the NMOS transistor 125, the NMOS transistor 126, etc. of the second inverting differential amplifier 109b) also increases. . That is, the delay time of the first inverting differential amplifier 109a is shortened.

  Next, the operation of the ring oscillator (RO) 109 as an oscillator will be described.

  As described above, when the NMOS transistor 125 of the first inverting differential amplifier 109a is ON and the NMOS transistor 126 is OFF, the output is the LOW level on the NMOS transistor 125 side and the HIGH level on the NMOS transistor 126 side, as described above.

  The LOW level is input to the NMOS transistor 125 of the second inverting differential amplifier 109b and the HIGH level is input to the NMOS transistor 126 by the output from the first inverting differential amplifier 109a. As a result, the NMOS transistor 125 is turned off, the NMOS transistor 126 is turned on, the output of the NMOS transistor 125 (the input to the NMOS transistor 125c of the third inverting differential amplifier 109c) is HIGH level, and the output of the NMOS transistor 126 (first output). The input to the NMOS transistor 126 of the tri-inverting differential amplifier 109c becomes LOW level.

  By the output from the second inverting differential amplifier 109b, the HIGH level is input to the NMOS transistor 125 of the third inverting differential amplifier 109c, and the LOW level is input to the NMOS transistor 126. As a result, the NMOS transistor 125 is turned on, the NMOS transistor 126 is turned off, the output of the NMOS transistor 125 (the input to the NMOS transistor 125 of the fourth inverting differential amplifier 109d) is LOW level, and the output of the NMOS transistor 126 (first output). The input to the NMOS transistor 126 of the 4-inverting differential amplifier 109d becomes HIGH level.

  Based on the output from the third inverting differential amplifier 109c, the LOW level is input to the NMOS transistor 125 of the fourth inverting differential amplifier 109d, and the HIGH level is input to the NMOS transistor 126. As a result, the NMOS transistor 125 is turned off, the NMOS transistor 126 is turned on, the output of the NMOS transistor 125 (input to the NMOS transistor 126 of the first inverting differential amplifier 109a) is HIGH level, and the output of the NMOS transistor 126 (first output). The input to the NMOS transistor 125 of the 1-inverting differential amplifier 109a becomes the LOW level.

  Based on the output from the fourth inverting differential amplifier 109d, the LOW level is input to the NMOS transistor 125 of the first inverting differential amplifier 109a, and the HIGH level is input to the NMOS transistor 126. As a result, the NMOS transistor 125 is turned off, the NMOS transistor 126 is turned on, the output of the NMOS transistor 125 (the input to the NMOS transistor 125 of the second inverting differential amplifier 109b) is HIGH level, and the output of the NMOS transistor 126 (first output). The input to the NMOS transistor 126 of the inverting differential amplifier 109b becomes the LOW level.

  Initially, the NMOS transistor 125 of the first inversion-type differential amplifier 109a was on and the NMOS transistor 126 was off. When the ring made one turn (the first inversion-type differential amplifier 109a to the fourth inversion-type differential amplifier 109d), The NMOS transistor 125 of the 1-inverting amplifier 109a is OFF and the NMOS transistor 126 is ON. Since this operation continues, it oscillates.

Since the voltage controlled oscillator (VCO) 105 has an offset to the above-described free-running oscillation frequency _Fa101 , the slope of the frequency characteristic can be relaxed. Therefore, when the voltage V _cnt including the noise component is input, the fluctuation of the oscillation frequency F _b101 described above can be reduced as compared with a voltage controlled oscillator having no offset.

  Here, frequency characteristics of the conventional voltage controlled oscillator (VCO) 105 will be described with reference to FIG. FIG. 15 is a diagram showing frequency characteristics of a conventional voltage controlled oscillator (VCO).

As shown in FIG. 15, the symbol Y <b> 101 represents the frequency characteristic at the time of type-case. At this time, the free-running oscillation frequency F _a101 is about 500 (MHz). The type-case has no manufacturing variation, and the threshold voltage V _tn of the NMOS transistor and the threshold voltage V _{tp of the} PMOS transistor corresponding to V _a101 , V _a102 , and V _a103 illustrated in FIG. This is the characteristic when it is made at the center. However, there are manufacturing variations, and a frequency characteristic at the time of fast-case such as Y101 ′ and a frequency characteristic at the time of slow-case such as Y101 ″ will appear. Fast-case is a characteristic when V _tn , V _tp, etc. can be lowered, and the transistor is turned on quickly, the gate length is thin, the wiring is thin, etc., and the parasitic capacitance is also small. Therefore, the signal etc. propagates quickly. Slow-case is a characteristic when V _tn , V _tp, etc. can be increased. The transistor turns on slowly, the gate length is thick, the wiring is long, etc., and there is a lot of parasitic capacitance etc. Therefore, the signal etc. propagates slowly. In addition, V _tn , V _{tp, and the} like may vary on the contrary.

When the frequency characteristic is obtained in consideration of such manufacturing variations, the upper limit is MAX of the code Y101 ′, and the lower limit is MIN of the code Y101 ″. In the frequency characteristics (fast-case) indicated by the symbol Y101 ′, the free-running oscillation frequency _Fa102 is about 600 (MHz). This is about 20% faster than the frequency characteristic (typ-case) indicated by the code Y101. However, as the voltage V _cnt increases, the voltage for obtaining the desired oscillation frequency F _b101 corresponding to the output signal F _VCO is V _b101 , V _a101 <V _b101 <V _DD , and the oscillation frequency F _b101 is 1000 ( MHz) _as) when a level of _{V b101,} becomes a frequency characteristic indicated by the reference numeral Y101 (typ-case) at about 1000 (MHz), from the code Y101 'indicates the frequency characteristic (fast-Case) in typ-Case 55 % Is about 1550 (MHz), which is faster. In the frequency characteristic (slow-case) indicated by the symbol Y101 ″, the free-running oscillation frequency _Fa103 is about 400 (MHz). This is about 20% slower than the frequency characteristic (typ-case) indicated by the reference Y101. However, when the voltage V _cnt increases and reaches the level of V _b101 , the frequency characteristic (typ-case) indicated by the reference Y101 becomes approximately 1000 (MHz), but the frequency characteristic indicated by the reference Y101 ″ (slow−) In case), it becomes about 600 (MHz), which is 40% slower than type-case.

As described above, the frequency characteristic of the conventional voltage controlled oscillator (VCO) 105 was settled with 20% variation at the time of free-running oscillation, but when the voltage V _cnt becomes larger, the variation becomes the upper limit side (sign 55% for the frequency characteristic indicated by Y101 ′, and 40% for the lower limit side (frequency characteristic indicated by Y101 ″). This is because a current mirror circuit is mainly used for the voltage controlled oscillator (VCO) 105, and the variation in oscillation frequency becomes large due to the channel length modulation effect. In recent LSIs, when the transistor size is reduced, the effect becomes significant due to the channel length modulation effect.

  The channel length modulation effect usually refers to an effect that the drain current increases as the drain voltage increases in the drain voltage range (saturation region) where the drain current saturates due to transistor characteristics. Due to this effect, the drain current varies according to the variation of the drain voltage, and the oscillation frequency varies.

  Next, the configuration of a PLL circuit using a conventional voltage-controlled oscillator (VCO) 105 will be described with reference to FIG. 13 taking a PLL (Phase-Locked Loop) as an example. FIG. 13 is a block diagram showing a configuration of a PLL circuit using a conventional voltage controlled oscillator (VCO).

  As shown in FIG. 13, the PLL circuit includes a phase frequency comparator (PFD) 101, a charge pump 102, a loop filter 103, an offset circuit (OFST) 104, a voltage controlled oscillator (VCO) 105, and a frequency divider 106. ing.

A phase frequency comparator (PFD) 101 compares the phase and frequency of the input signal F _ref and the feedback signal F _fb from the frequency divider 106, and _generates an increment signal UP and a decrement signal DOWN representing an error between these two signals. Generate. For example, a clock signal from an oscillator (not shown) is used as the input signal F _ref . The increment signal UP generated by the phase frequency comparator (PFD) 101 has a pulse width corresponding to a frequency drop and a phase delay of the feedback signal F _fb with respect to the input signal F _ref . The decrement signal DOWN has a pulse width corresponding to the frequency increase and phase advance of the feedback signal F _fb with respect to the input signal F _ref . The increment signal UP and the decrement signal DOWN generated by the phase frequency comparator (PFD) 101 are supplied to the charge pump 102.

The charge pump 102 is a single output charge pump, and generates a current pulse corresponding to each pulse width of the increment signal UP and the decrement signal DOWN and supplies the current pulse to the loop filter 103. In response to the current pulse supplied from the charge pump 102, the loop filter 103 accumulates electric charge in a capacitor (not shown), for example, and discharges electric charge accumulated in the capacitor (not shown), according to the above-described current pulse. A voltage V _cnt is generated. The voltage V _cnt generated by the loop filter 103 is supplied to a voltage controlled oscillator (VCO) 105.

The offset circuit (OFST) 104 generates a constant voltage V _cn1 and supplies it to the bias generator (BG) 108 of the voltage controlled oscillator (VCO) 105. A constant voltage V _cn1 is supplied from the offset circuit (OFST) 104 and a voltage V _cnt is supplied from the loop filter 103 to the bias generator (BG) 108 of the voltage controlled oscillator (VCO) 105. The voltage controlled oscillator (VCO) 105 generates an output signal F _VCO that oscillates at a frequency corresponding to the constant voltage V _cn1 supplied from the offset circuit (OFST) 104 and the voltage V _cnt supplied from the loop filter 103. . The oscillation frequency is indirectly determined by a current obtained by adding a current I _cn1 corresponding to the value of the constant voltage V _cn1 and a current I _cnt corresponding to the value of the voltage V _cnt . In the locked state, the voltage controlled oscillator (VCO) 105 oscillates at a frequency that is M times the frequency of the input signal F _ref (M times is a real number).

The output signal F _VCO generated by the voltage controlled oscillator (VCO) 105 is sent to the outside as an output signal of the PLL circuit and is supplied to the frequency divider 106. The frequency divider 106 _divides the output signal F _VCO by 1 / N and supplies it to the phase frequency comparator (PFD) 101.

  Next, the operation of the PLL circuit using the conventional voltage controlled oscillator (VCO) 105 will be described.

Assume that the phase of the feedback signal F _fb fed back from the frequency divider 106 to the phase frequency comparator (PFD) 101 is delayed from the phase of the input signal F _ref . In this case, the phase frequency comparator (PFD) 101 generates an incremental signal UP having a pulse width corresponding to the frequency drop and the phase delay, and supplies the increment signal UP to the charge pump 102. The charge pump 102 discharges a current corresponding to the increment signal UP and charges a capacitor (not shown) of the loop filter 103. As a result, the voltage V _cnt generated by the loop filter 103 increases. As a result, the oscillation frequency of the output signal F _VCO output from the voltage controlled oscillator (VCO) 105 increases, and the phase of the output signal F _VCO advances to approach the phase of the input signal F _ref .

On the other hand, when the phase of the feedback signal F _fb is advanced from the phase of the input signal F _ref , the phase frequency comparator (PFD) 101 generates a decrement signal DOWN having a pulse width corresponding to the frequency increase and the phase advance. And supplied to the charge pump 102. The charge pump 102 draws a current corresponding to the decrement signal DOWN to discharge a capacitor (not shown) of the loop filter 103. As a result, the voltage V _cnt output from the loop filter 103 is lowered. As a result, the oscillation frequency of the output signal F _VCO output from the voltage controlled oscillator (VCO) 105 decreases, and the phase of the output signal F _VCO is delayed and approaches the phase of the input signal F _ref .

Thus, in the PLL circuit using the conventional voltage controlled oscillator (VCO) 105, it is constantly compared with the phase and frequency of the phase and frequency as the input signal _{F ref} of the output signal _{F VCO,} the output signal to the input signal _{F ref} If there is a phase delay or phase advance of the F _VCO , feedback control is performed to correct them. When the phase delay or phase advance converges within a predetermined range, the phase frequency comparator (PFD) 101 generates the increment signal UP and the decrement signal DOWN having the same short pulse width. As a result, the amounts of charges charged and discharged by a capacitor (not shown) of the loop filter 103 are equalized and balanced, and the PLL circuit enters a locked state. In this locked state, the phase of the output signal F _VCO matches the phase of the input signal F _ref . However, in the PLL circuit using the voltage controlled oscillator (VCO) 105, when the noise component is included in the voltage V _cnt output from the loop filter 3, the offset frequency is provided, so that the offset frequency is not provided. As compared with the above, the fluctuation of the desired oscillation frequency can be suppressed to a small value, but since a large number of current mirror circuits are used, the fluctuation of the oscillation frequency due to manufacturing fluctuation cannot be suppressed low.

  Further, as a PLL circuit using a voltage controlled oscillator (VCO), Japanese Patent Laid-Open No. 8-125531 discloses a “frequency synthesizer circuit” that can prevent phase fluctuation of an RF modulation signal due to disturbance and has good modulation accuracy. Yes.

  This frequency synthesizer circuit is an offset signal generation circuit that generates an offset voltage for canceling the frequency fluctuation caused by the disturbance signal based on the disturbance signal that causes the frequency of the local oscillation signal that is the output of the voltage controlled oscillator to fluctuate. And an offset signal adding circuit for adding the offset voltage from the offset signal generating circuit to the tuning voltage and supplying the same to the voltage controlled oscillator.

Further, in Patent Document 1 , regardless of variations in manufacturing conditions, voltage signals fluctuate due to power supply fluctuations, temperature changes, etc., and even if control characteristics fluctuate, the oscillation frequency is not affected, and no unlock occurs. A PLL circuit "is disclosed.

  This PLL (phase-locked loop) circuit is controlled in frequency in response to the phase of the phase-locked loop circuit section that generates a DC voltage signal from the error signal of the phase comparison result between the oscillation signal and the reference signal. A voltage-controlled oscillation circuit that outputs an oscillation signal, examines device characteristic changes due to fluctuations in manufacturing conditions, and outputs manufacturing process condition detection means that outputs corresponding process fluctuation signals, and voltage in response to supply of process fluctuation signals Voltage offset means for offsetting the center value of the signal to be close to the level at the time of frequency locking.

Non-Patent Document 1 describes the phase frequency comparator in detail.

Japanese Patent Laid-Open No. 11-177416

Hiromi Notani et al. “A 622-MHz CMOS Phase-Locked Loop with Precharge-Type Phase Frequency Detector” “Symposium on VLSI Circuits Digest of the Worlds”. 129-130

  The conventional voltage controlled oscillator (VCO) 105 includes many current mirror circuits. When a transistor with a small size is used as in recent years, the fluctuation factor due to the channel length modulation effect also increases. Therefore, in the conventional voltage controlled oscillator (VCO) 105, the channel length modulation effect is added by the number of stages of the current mirror circuit. The variation of the oscillation frequency becomes large.

  The conventional voltage controlled oscillator (VCO) 105 has the following problems because the oscillation frequency varies greatly as described above.

In the conventional voltage controlled oscillator (VCO) 105, since the channel length modulation effect is added to the manufacturing variation, the variation of the oscillation frequency becomes large. When the gain is minimum, for example, even if the voltage V _cnt is increased to the value of the power supply voltage V _{DD in} the frequency characteristic indicated by the symbol Y101 ″ shown in FIG. 15, there is a risk that the oscillation frequency becomes smaller than the desired frequency F _b101 There is sex. Therefore, in order to obtain the desired frequency _Fb101 even if there is a manufacturing variation, the gain of the conventional voltage controlled oscillator (VCO) 105 is increased (the frequency characteristic is sharpened). Then, when a noise component is applied to the voltage V _cnt , the oscillation frequency varies greatly (jitter increases).

Further, in consideration of fluctuations in the oscillation frequency, it is not possible to set a wide range of oscillation frequencies that can be controlled within the range of the voltage V _cnt . That is, the conventional voltage controlled oscillator (VCO) 105 cannot secure a frequency range that can be minimized, and the frequency range of the conventional voltage controlled oscillator (VCO) 105 is denoted by reference numeral F _{100 as shown} in FIG. This frequency range F _{100 represents} from the free-running oscillation frequency F _a102 in the frequency characteristic indicated by the symbol Y101 ′ to the oscillation frequency when the voltage V _cnt is the value of the power supply voltage V _{DD in} the frequency characteristic indicated by the symbol Y101 ″. It does not include the desired oscillation frequency _{F b101} in the frequency range _{F 100.}

  An object of the present invention is to provide a voltage controlled oscillator capable of suppressing variations in oscillation frequency.

  Another object of the present invention is to provide a voltage controlled oscillator in which jitter is reduced.

  Still another object of the present invention is to provide a voltage controlled oscillator capable of widening the frequency range.

  Means for solving the problem is expressed as follows. In the technical matters corresponding to the claims in the expression, numbers, symbols and the like are appended with parentheses (). The numbers, symbols, and the like correspond to technical matters constituting at least one embodiment or a plurality of embodiments of the present embodiment, or a plurality of embodiments, in particular, the embodiments or examples. This corresponds to the reference numerals, reference symbols, and the like attached to the technical matters expressed in the drawings. Such reference numbers and reference symbols clarify the correspondence and bridging between the technical matters described in the claims and the technical matters of the embodiments or examples. Such correspondence and bridging does not mean that the technical matters described in the claims are interpreted as being limited to the technical matters of the embodiments or examples.

The voltage controlled oscillator according to the present invention includes N (N is an integer of 2 or more) inverting differential amplifiers (9) connected in series. Each of the N inverting differential amplifiers (9) operates according to a constant voltage (V _cn1 ) and a control voltage (V _cnt ) having a predetermined voltage value. The operating current of each of the N inverting differential amplifiers (9) is directly determined by a current value obtained by adding a current corresponding to the constant voltage (V _cn1 ) and a current corresponding to the control voltage (V _cnt ).

  When N is an even number of 2 or more, the output of the last-stage inverting differential amplifier (9d) among the N inverting differential amplifiers (9) is the first stage among the N inverting differential amplifiers (9). Is inverted and returned to the inverting differential amplifier (9a).

  When N is an odd number of 3 or more, the output of the last-stage inverting differential amplifier (9c) among the N inverting differential amplifiers (9) is the first stage among the N inverting differential amplifiers (9). Is returned to the inverting differential amplifier (9a).

The voltage controlled oscillator according to the invention further comprises a bias generator (8) for compensating the operating current. The bias generator (8) has a control electrode to which a constant voltage (V _cn1 ) is input, a first input stage transistor (12) connected in series between the first power supply and the second power supply, and a control A second input stage transistor having a control electrode to which a voltage (V _cnt ) is input, connected in series between the first power supply and the second power supply, and connected in parallel with the first input stage transistor (12); 13) and a specific transistor (11) connected between the first power source and the first and second input stage transistors (12, 13). The bias generator (58) has a control electrode to which a constant voltage (V _cn1 ) is input, and a first input stage transistor (12) connected in series between the first power supply and the second power supply; A specific transistor (11) connected between the first power supply and the first input stage transistor (12).

Each of the N inverting differential amplifiers (9) includes first and second output stage transistors (25, 26) connected in parallel between the first power source and the second power source, and a constant voltage (V _cn1 ). And a third input stage transistor (27) connected between the first and second output stage transistors (25, 26) and the second power source, and a control voltage (V _cnt ). Is connected between the first and second output stage transistors (25, 26) and the second power source, and is connected in parallel with the third input stage transistor (27). An input stage transistor (28), a first transistor (22) connected in series between the first power supply and the first output stage transistor (25), and connected to the specific transistor (11); Connected in series with the second output stage transistor (26). The second transistor (23) connected to the specific transistor (11) is connected in series between the first power source and the first output stage transistor (25), and in parallel with the first transistor (22). The third transistor (21) connected, and the fourth transistor (24) connected in series between the first power supply and the second output stage transistor (26) and connected in parallel with the second transistor (23). And.

  The specific transistor (11) and the first transistor (22) constitute a current mirror circuit, and the specific transistor (11) and the second transistor (23) constitute a current mirror circuit.

Each of the N inverting differential amplifiers (79) includes a first and second output stage transistors (25, 26) connected in parallel between the first power source and the second power source, and a constant voltage (V _cn1 ). And a control voltage (V _cnt ), a first input stage transistor (27) connected between the first and second output stage transistors (25, 26) and the second power source. Is connected between the first and second output stage transistors (25, 26) and the second power source, and is connected in parallel with the first input stage transistor (27). An input stage transistor (28), a resistance element (81) connected in series between a first power supply and a first output stage transistor (25), and a first power supply and a second output stage transistor (26) And a resistance element (82) connected in series therebetween.

The voltage controlled oscillator according to the present invention comprises N inverting differential amplifiers (9) connected in series. Each of the N inverting differential amplifiers (9) is connected to the differential unit, the constant voltage (V _cn1 ) and the control voltage (V _cnt ) connected to the differential unit. And a current source.

The voltage controlled oscillator according to the present invention determines an intended frequency by controlling an offset means for providing an offset frequency by a constant voltage (V _cn1 ) having a predetermined voltage value and a frequency determined in proportion to the control voltage (V _cnt ). Control means. The frequency is directly determined by the constant voltage (V _cn1 ) and the control voltage (V _cnt ).

The PLL circuit according to the present invention compares the phase and frequency of an external input signal (F _ref ) and a feedback signal (F _fb ), and generates a control voltage (V _cnt ) based on the comparison result. A generator (1, 2, 3), an offset circuit (4) for generating a constant voltage (V _cn1 ) having a predetermined voltage value, and a current corresponding to the constant voltage (V _cn1 ) from the offset circuit (4) Then, the current corresponding to the control voltage (V _cnt ) from the control voltage generator (1, 2, 3) is added to generate an output signal (F _VCO ) that oscillates at a frequency corresponding to the value of the added current. _Frequency division of the voltage controlled oscillator (5) and the output signal (F _VCO ) from the voltage controlled oscillator (5) and feeding back as a feedback signal (F _fb ) to the control voltage generator (1, 2, 3) (6). The voltage controlled oscillator (5) includes N (N is an integer of 2 or more) inverting differential amplifiers (9) connected in series. Each of the N inverting differential amplifiers (9) operates according to the constant voltage (V _cn1 ) and the control voltage (V _cnt ). The operating current of each of the N inverting differential amplifiers (9) is directly determined by a current value obtained by adding a current corresponding to the constant voltage (V _cn1 ) and a current corresponding to the control voltage (V _cnt ).

  When N is an even number of 2 or more, the output of the last-stage inverting differential amplifier (9d) among the N inverting differential amplifiers (9) is the first stage among the N inverting differential amplifiers (9). Is inverted and returned to the inverting differential amplifier (9a).

  When N is an odd number of 3 or more, the output of the last-stage inverting differential amplifier (9d) among the N inverting differential amplifiers (9) is the first stage among the N inverting differential amplifiers (9). Is returned to the inverting differential amplifier (9a).

The voltage controlled oscillator (5) further comprises a bias generator (8) for compensating the operating current. The bias generator (8) has a control electrode to which a constant voltage (V _cn1 ) is input, a first input stage transistor (12) connected in series between the first power supply and the second power supply, and a control A second input stage transistor having a control electrode to which a voltage (V _cnt ) is input, connected in series between the first power supply and the second power supply, and connected in parallel with the first input stage transistor (12); 13) and a specific transistor (11) connected between the first power source and the first and second input stage transistors (12, 13). The bias generator (58) has a control electrode to which a constant voltage (V _cn1 ) is input, and a first input stage transistor (12) connected in series between the first power supply and the second power supply; A specific transistor (11) connected between the first power supply and the first input stage transistor (12).

Each of the N inverting differential amplifiers (9) includes first and second output stage transistors (25, 26) connected in parallel between the first power source and the second power source, and a constant voltage (V _cn1 ). And a third input stage transistor (27) connected between the first and second output stage transistors (25, 26) and the second power source, and a control voltage (V _cnt ). Is connected between the first and second output stage transistors (25, 26) and the second power source, and is connected in parallel with the third input stage transistor (27). An input stage transistor (28), a first transistor (22) connected in series between the first power supply and the first output stage transistor (25), and connected to the specific transistor (11); Connected in series with the second output stage transistor (26). The second transistor (23) connected to the specific transistor (11) is connected in series between the first power source and the first output stage transistor (25), and in parallel with the first transistor (22). The third transistor (21) connected, and the fourth transistor (24) connected in series between the first power supply and the second output stage transistor (26) and connected in parallel with the second transistor (23). And.

  The specific transistor (11) and the first transistor (22) constitute a current mirror circuit, and the specific transistor (11) and the second transistor (23) constitute a current mirror circuit.

Each of the N inverting differential amplifiers (79) includes a first and second output stage transistors (25, 26) connected in parallel between the first power source and the second power source, and a constant voltage (V _cn1 ). And a control voltage (V _cnt ), a first input stage transistor (27) connected between the first and second output stage transistors (25, 26) and the second power source. Is connected between the first and second output stage transistors (25, 26) and the second power source, and is connected in parallel with the first input stage transistor (27). An input stage transistor (28), a resistance element (81) connected in series between a first power supply and a first output stage transistor (25), and a first power supply and a second output stage transistor (26) And a resistance element (82) connected in series therebetween.

The PLL circuit according to the present invention compares the phase and frequency of an external input signal (F _ref ) and a feedback signal (F _fb ), and generates a control voltage (V _cnt ) based on the comparison result. A generator (1, 2, 3), an offset circuit (4) for generating a constant voltage (V _cn1 ) having a predetermined voltage value, and a current corresponding to the constant voltage (V _cn1 ) from the offset circuit (4) Then, the current corresponding to the control voltage (V _cnt ) from the control voltage generator (1, 2, 3) is added to generate an output signal (F _VCO ) that oscillates at a frequency corresponding to the value of the added current. _Frequency division of the voltage controlled oscillator (5) and the output signal (F _VCO ) from the voltage controlled oscillator (5) and feeding back as a feedback signal (F _fb ) to the control voltage generator (1, 2, 3) (6). The voltage controlled oscillator (5) includes N inverting differential amplifiers (9) connected in series. Each of the N inverting differential amplifiers (9) is connected to the differential unit, the constant voltage (V _cn1 ) and the control voltage (V _cnt ) connected to the differential unit. And a current source.

The PLL circuit according to the present invention compares the phase and frequency of an external input signal (F _ref ) and a feedback signal (F _fb ), and generates a control voltage (V _cnt ) based on the comparison result. A generator (1, 2, 3), an offset circuit (4) for generating a constant voltage (V _cn1 ) having a predetermined voltage value, and a current corresponding to the constant voltage (V _cn1 ) from the offset circuit (4) Then, the current corresponding to the control voltage (V _cnt ) from the control voltage generator (1, 2, 3) is added to generate an output signal (F _VCO ) that oscillates at a frequency corresponding to the value of the added current. _Frequency division of the voltage controlled oscillator (5) and the output signal (F _VCO ) from the voltage controlled oscillator (5) and feeding back as a feedback signal (F _fb ) to the control voltage generator (1, 2, 3) (6). The voltage controlled oscillator (5) includes offset means for providing an offset frequency by a constant voltage (V _cn1 ), and control means for controlling a frequency determined in proportion to the control voltage (V _cnt ) to determine a desired frequency. ing. The frequency is directly determined by the constant voltage (V _cn1 ) and the control voltage (V _cnt ). The PLL circuit according to the present invention can be implemented not only by the voltage controlled oscillator (5) but also by the voltage controlled oscillator (55) and the voltage controlled oscillator (75).

  The voltage controlled oscillator of the present invention can suppress variation in oscillation frequency.

FIG. 1 is a circuit diagram showing a configuration of a voltage controlled oscillator (VCO) according to the first embodiment. FIG. 2 is a circuit diagram showing another configuration of the voltage controlled oscillator (VCO) according to the first embodiment. FIG. 3 is a block diagram showing a configuration of a PLL circuit using the voltage controlled oscillator (VCO) according to the first embodiment. FIG. 4 is a diagram illustrating the relationship between the output signal F _VCO and the voltage V _cnt . FIG. 5 is a diagram illustrating frequency characteristics of the voltage controlled oscillator (VCO) according to the first embodiment. FIG. 6 is a circuit diagram showing a configuration of a voltage controlled oscillator (VCO) according to the second embodiment. FIG. 7 is a circuit diagram showing another configuration of the voltage controlled oscillator (VCO) according to the second embodiment. FIG. 8 is a block diagram showing a configuration of a PLL circuit using the voltage controlled oscillator (VCO) according to the second embodiment. FIG. 9 is a circuit diagram showing a configuration of a voltage controlled oscillator (VCO) according to the third embodiment. FIG. 10 is a circuit diagram showing another configuration of the voltage controlled oscillator (VCO) according to the third embodiment. FIG. 11 is a block diagram showing a configuration of a PLL circuit using a voltage controlled oscillator (VCO) according to the third embodiment. FIG. 12 is a circuit diagram showing a configuration of a conventional voltage controlled oscillator (VCO). FIG. 13 is a block diagram showing a configuration of a PLL circuit using a conventional voltage controlled oscillator (VCO). FIG. 14 is a diagram illustrating the relationship between the output signal F _VCO and the voltage V _cnt . FIG. 15 is a diagram showing frequency characteristics of a conventional voltage controlled oscillator (VCO).

  Embodiments of a voltage controlled oscillator according to the present invention will be described below with reference to the accompanying drawings.

(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration of a voltage controlled oscillator (VCO) according to the first embodiment.

  As shown in FIG. 1, the voltage controlled oscillator (VCO) 5 according to the first embodiment includes a bias generator (BG) 8, a ring oscillator (RO) 9, and a level converter (LC) 7.

The bias generator (BG) 8 and the ring oscillator (RO) 9 are supplied / input with constant voltages V _cn1 and V _cnt having predetermined voltage values from the outside. A power supply voltage is supplied / input from the outside to the bias generator (BG) 8 and the ring oscillator (RO) 9. The output of the bias generator (BG) 8 is supplied / input to the ring oscillator (RO) 9.

The ring oscillator (RO) 9 includes N inverting differential amplifiers. Here, N is an integer of 2 or more. Each of the N inverting differential amplifiers operates according to an external constant voltage V _cn1 and an external voltage V _cnt . Each of the operating current of the N inverting differential amplifier, a current _{I cn1} corresponding to the value of the constant voltage _{V cn1,} determined directly by a current obtained by adding the current _{I cnt} corresponding to the value of the voltage _{V cnt.} The bias generator (BG) 8 is a ring oscillator (RO) that uses a current obtained by adding a current I _cn1 corresponding to the value of the external constant voltage V _cn1 and a current I _cnt corresponding to the value of the external voltage V _cnt. 9 operating current is compensated. Compensation means that when a transistor acting as a switch of the ring oscillator (RO) 9 is ON / OFF, a current is passed quickly, and the rising and falling of the oscillation waveform are operated at high speed (to make it steep) and oscillate at high speed. To encourage This compensation can improve the high frequency characteristics, that is, improve the followability.

The ring oscillator (RO) 9 gives an offset frequency by the constant voltage V _cn1 and controls the oscillation frequency determined in proportion to the voltage V _cnt to determine a desired oscillation frequency. The desired oscillation frequency is directly determined by the current obtained by adding the current I _cn1 corresponding to the value of the constant voltage V _cn1 and the current I _cnt corresponding to the value of the voltage V _cnt . The ring oscillator (RO) 9 receives one of the maximum voltage V _OUT1 representing the maximum peak and the minimum voltage V _OUT2 representing the minimum peak among the amplitudes of the voltages corresponding to the determined desired oscillation frequency via the first output terminal OUT1. _Is supplied to the level converter (LC) 7, and the other of the maximum voltage V _OUT1 and the minimum voltage V _OUT2 is supplied to the level converter (LC) 7 via the second output terminal OUT2.

The level converter (L-C) 7 increases the amplitude between the minimum voltage V _OUT2 and the maximum voltage V _OUT1 to a CMOS level (for example, from 0 (V) to a power supply voltage) and outputs an output signal. _{Create an} F _VCO . The output signal F _VCO generated by the level converter (LC) 7 is sent to the outside as an output signal of the voltage controlled oscillator (VCO) 5.

Here, the oscillation frequency corresponding to the output signal F _VCO generated by the voltage controlled oscillator (VCO) 5 will be described with reference to FIG. FIG. 4 is a diagram illustrating the relationship between the output signal F _VCO and the voltage V _cnt .

As shown in FIG. 4, a code X1 indicating a relationship (frequency characteristic) between the output signal F _VCO and the voltage V _cnt that is normally generated by the voltage controlled oscillator (VCO) is included in the voltage controlled oscillator (VCO) 5. When the voltage V _cnt is greater than a threshold voltage V _a1 of a transistor to be described later, the linearity is such that the oscillation frequency of the output signal F _VCO becomes greater than 0 (Hz). The voltage controlled oscillator (VCO) 5 is an external power supply voltage V _DD (for example, 2.5 (V)) that operates the voltage controlled oscillator (VCO) 5 from a threshold voltage V _a1 (for example, 0.5 (V)). The desired oscillation frequency F _VCO ′ is determined by controlling the oscillation frequency determined in proportion to the voltage V _cnt in the range up to. At this time, a voltage for obtaining a desired oscillation frequency F _b1 corresponding to the output signal F _VCO is V _b1 (V _a1 <V _b1 <V _DD ).

However, when the voltage V _b1 fluctuates due to external noise component interference, the slope of the frequency characteristic indicated by the symbol X1 is steep, so that the desired oscillation frequency F _b1 fluctuates according to the slope of the frequency characteristic. Increased (jitter increases).

In order to suppress the large fluctuation of the oscillation frequency F _b1 , the voltage controlled oscillator (VCO) 5 has an offset frequency because the ring oscillator (RO) 9 adds a current corresponding to the constant voltage V _cn1 to provide an offset frequency. The frequency characteristic indicated by the reference sign Y1 is obtained by making the frequency F _a1 larger than 0 (Hz) and smaller than the desired frequency F _b1 as a reference frequency (self-running oscillation frequency) to make the slope of the frequency characteristic indicated by the reference sign X1 gentle. Can be generated.

  Next, referring to FIG. 1 for the configuration of the bias generator (BG) 8 and the ring oscillator (RO) 9 of the voltage controlled oscillator (VCO) 5 according to the first embodiment when N is an even number of 2 or more. However, it explains in detail.

As shown in FIG. 1, the bias generator (BG) 8 includes a P-channel MOS transistor 11 and N-channel MOS transistors 12 and 13. Hereinafter, the P channel MOS transistor is referred to as a PMOS transistor, and the N channel MOS transistor is referred to as an NMOS transistor. A high voltage source is connected to the source electrode of the PMOS transistor 11, and the power supply voltage V _DD is input / supplied. The drain electrode of the PMOS transistor 11 is connected to the drain electrodes of the NMOS transistors 12 and 13. A constant voltage _Vcn1 is input / supplied to the gate electrode of the NMOS transistor 12 from the outside. Further, the source electrode of the NMOS transistor 12 is connected to the lower power supply and is usually grounded. A voltage V _cnt is input / supplied to the gate electrode of the NMOS transistor 13 from the outside. The source electrode of the NMOS transistor 13 is connected to the lower power supply and is usually grounded.

  Next, the configuration of the ring oscillator (RO) 9 will be described.

As shown in FIG. 1, when N is 4, the ring oscillator (RO) 9 includes a first inverting differential amplifier 9a, a second inverting differential amplifier 9b, a third inverting differential amplifier 9c, and a fourth inverting difference. A dynamic amplifier 9d is provided. Each of the first inverting differential amplifier 9a to the fourth inverting differential amplifier 9d has PMOS transistors 21, 22, 23, and 24, and NMOS transistors 25 and 26 as differential parts, and a current connected to the differential part. An NMOS transistor 27 driven by a constant voltage V _cn1 and an NMOS transistor 28 driven by a voltage V _cnt are provided as sources.

  The configuration of each of the first inverting differential amplifier 9a to the fourth inverting differential amplifier 9d will be described.

A high voltage source is connected to the source electrodes of the PMOS transistors 21, 22, 23, and 24, and the power supply voltage V _DD is input / supplied. The gate electrodes of the PMOS transistors 22 and 23 are connected to the drain electrode and the gate electrode of the PMOS transistor 11. Here, with respect to the PMOS transistor 11 of the bias generator (BG) 8, the PMOS transistors 22 and 23 are current mirror circuits. A constant voltage _Vcn1 is input / supplied to the gate electrode of the NMOS transistor 27 from the outside. The source electrode of the NMOS transistor 27 is connected to the lower power supply and is usually grounded. A voltage V _cnt is input / supplied to the gate electrode of the NMOS transistor 28 from the outside. The source electrode of the NMOS transistor 28 is connected to the lower power supply and is usually grounded. The drain electrode of the NMOS transistor 28 is connected to the drain electrode of the NMOS transistor 27 and the source electrodes of the NMOS transistors 25 and 26. The drain electrode of the NMOS transistor 25 is connected to the drain electrodes of the PMOS transistors 21 and 22 and the gate electrode of the PMOS transistor 21. The drain electrode of the NMOS transistor 26 is connected to the drain electrodes of the PMOS transistors 23 and 24 and the gate electrode of the PMOS transistor 24.

  The gate electrode of the NMOS transistor 25 of the second inverting differential amplifier 9b is connected to the drain electrode of the NMOS transistor 25 of the first inverting differential amplifier 9a. The gate electrode of the NMOS transistor 26 of the second inverting differential amplifier 9b is connected to the drain electrode of the NMOS transistor 26 of the first inverting differential amplifier 9a.

  The gate electrode of the NMOS transistor 25 of the third inverting differential amplifier 9c is connected to the drain electrode of the NMOS transistor 25 of the second inverting differential amplifier 9b. The gate electrode of the NMOS transistor 26 of the third inverting differential amplifier 9c is connected to the drain electrode of the NMOS transistor 26 of the second inverting differential amplifier 9b.

  The gate electrode of the NMOS transistor 25 of the fourth inverting differential amplifier 9d is connected to the drain electrode of the NMOS transistor 25 of the third inverting differential amplifier 9c. The gate electrode of the NMOS transistor 26 of the fourth inverting differential amplifier 9d is connected to the drain electrode of the NMOS transistor 26 of the third inverting differential amplifier 9c.

  The gate electrode of the NMOS transistor 25 of the first inverting differential amplifier 9a is connected to the drain electrode of the NMOS transistor 26 of the fourth inverting differential amplifier 9d. The gate electrode of the NMOS transistor 26 of the first inverting differential amplifier 9a is connected to the drain electrode of the NMOS transistor 25 of the fourth inverting differential amplifier 9d. The drain electrode of the NMOS transistor 25 of the fourth inverting differential amplifier 9d is connected to the level converter (LC) 7 through the first output terminal OUT1. The drain electrode of the NMOS transistor 26 of the fourth inverting differential amplifier 9d is connected to the level converter (LC) 7 via the second output terminal OUT2.

Next, operations of the bias generator (BG) 8 and the ring oscillator (RO) 9 of the voltage controlled oscillator (VCO) 5 will be described with reference to FIG. Here, a reference level is biased to the constant voltage V _cn1 input to the voltage controlled oscillator (VCO) 5, and a control level is biased to the voltage V _cnt .

  First, the circuit operation of the bias generator (BG) 8 will be described.

As shown in FIG. 1, since the constant voltage _Vcn1 is biased at the gate of the NMOS transistor 12, a drain current ID12 corresponding to the bias flows. The control level is biased to the voltage V _cnt , but if the level is now 0 (V), the NMOS transistor 13 is OFF (because the threshold voltage has not been reached), so the drain current ID 13 is 0 (A). Accordingly, the drain current ID11 of the PMOS transistor 11 is the sum of the drain current ID12 and the drain current ID13, but since the drain current ID13 is 0 (A), only the drain current ID12 flows. Since the gate and drain of the PMOS transistor are the same node, the PMOS transistor is in the saturation region, and the level of the gate is determined so that the drain current ID11 flows. This level is the same as that of the first inverting differential amplifier 109a, the second inverting differential amplifier 109b, the third inverting differential amplifier 109c, and the fourth inverting differential amplifier 109d in the ring oscillator (RO) 109. At the gate level. For the PMOS transistor 11, the PMOS transistors 22 and 23 of the first inverting differential amplifier 109a, the second inverting differential amplifier 109b, the third inverting differential amplifier 109c, and the fourth inverting differential amplifier 109d are current mirror circuits. Therefore, the size of the PMOS transistor 11 (including the threshold value, gate length, and thickness of the gate oxide film of the PMOS transistor 11) and the size of the PMOS transistors 22 and 23 (the size of each PMOS transistor) The current corresponding to the ratio of the threshold value, the gate length, and the thickness of the gate oxide film becomes the drain current of the PMOS transistors 22 and 23. The PMOS transistor 11 compensates for the operating current of the ring oscillator (RO) 9 by adding a current I _cn1 corresponding to the value of the constant voltage V _cn1 and a current I _cnt corresponding to the value of the voltage V _cnt. .

When the control level voltage V _cnt rises and becomes equal to or higher than the threshold of the NMOS transistor 13 (a level at which the NMOS transistor 13 is turned on), the drain current ID13 of the NMOS transistor 13 flows. As the voltage V _cnt rises, the drain current ID13 of the NMOS transistor 13 increases as the voltage _Vcnt increases. As a result, the drain current ID11 of the PMOS transistor 11 also increases. Therefore, the drain currents of the PMOS transistors 22 and 23 constituting the current mirror circuit also increase.

  Next, the circuit operation of the ring oscillator (RO) 9 will be described. Here, since the circuit operation of each of the first inverting differential amplifier 9a to the fourth inverting differential amplifier 9d is the same, the first inverting differential amplifier 9a will be described as an example.

When the reference level is biased to the constant voltage V _cn1 and the voltage V _cnt is 0 level, the drain current ID27 flows to the NMOS transistor 27, and the NMOS transistor 28 is off, so the drain current ID28 does not flow. When the source electrodes of the NMOS transistors 25 and 26 are commonly connected to the drain electrodes of the NMOS transistors 27 and 28, the drain current ID27 of the NMOS transistor 27 flows.

The NMOS transistors 25 and 26 of the differential circuit operating as switches operate with the drain current ID27 of the NMOS transistor 27 described above. The NMOS transistors 25 and 26 pass drain currents ID25 and ID26 corresponding to the input signals (outputs from the fourth inverting differential amplifier 9d) and supply them to the PMOS transistors 21 and 24, which are active loads. When the NMOS transistor 25 is turned on and the NMOS transistor 26 is turned off, a current flows through the NMOS transistor 25 and a current also flows through the PMOS transistor 21. At this time, a voltage drop corresponding to the drain-source voltage VDS21 of the PMOS transistor 21 occurs, and the output of the NMOS transistor 25 (the input to the NMOS transistor 25 of the second inverting differential amplifier 9b) becomes the LOW level. Since the NMOS transistor 26 is OFF, the output of the NMOS transistor 26 (the input to the NMOS transistor 26 of the second inverting differential amplifier 9b) becomes HIGH level. As a result, the ring oscillator (RO) 9 generates an oscillation frequency according to the current value obtained by adding the current I _cn1 corresponding to the value of the constant voltage V _cn1 and the current I _cnt corresponding to the value of the voltage V _cnt. To do. The oscillation frequency has a small amplitude of about 0.7V.

  The PMOS transistors 22 and 23 connected in parallel as the active load PMOS transistors have a mirror configuration with the bias generator (BG) 8, and when the mirror current flows, the NMOS transistors 25 and 26 are turned ON / OFF. In this case, there is an effect of flowing current quickly, and the rising and falling of the output can be operated at high speed, and oscillation can be promoted at high speed.

When the level of the voltage V _cnt increases, the NMOS transistor 28 is turned on, and the drain current ID28 of the NMOS transistor 28 flows, the circuit current of the first inverting differential amplifier 9a increases. As the current increases, the drive capability of the circuit naturally increases, and the time for charging and discharging the output load (the gate capacitance and the wiring capacitance of the NMOS transistor 25 and the NMOS transistor 26 of the second inverting differential amplifier 9b) also becomes faster. . That is, the delay time of the first inverting differential amplifier 9a is shortened.

  Next, the operation of the ring oscillator (RO) 9 as an oscillator will be described.

  When the NMOS transistor 25 of the first inverting differential amplifier 9a is ON and the NMOS transistor 26 is OFF, as described above, the output is the LOW level on the NMOS transistor 25 side and the HIGH level on the NMOS transistor 26 side.

  Due to the output from the first inverting differential amplifier 9a, the LOW level is input to the NMOS transistor 25 of the second inverting differential amplifier 9b, and the HIGH level is input to the NMOS transistor 26. As a result, the NMOS transistor 25 is turned off, the NMOS transistor 26 is turned on, and the output of the NMOS transistor 25 (input to the NMOS transistor 25 of the third inverting differential amplifier 9c) is at the HIGH level, and the output of the NMOS transistor 26 (first output). The input to the NMOS transistor 26 of the tri-inverting differential amplifier 9c becomes the LOW level.

  By the output from the second inverting differential amplifier 9b, the HIGH level is input to the NMOS transistor 25 of the third inverting differential amplifier 9c, and the LOW level is input to the NMOS transistor 26. As a result, the NMOS transistor 25 is turned ON, the NMOS transistor 26 is turned OFF, the output of the NMOS transistor 25 (input to the NMOS transistor 25 of the fourth inversion differential amplifier 9d) is LOW level, and the output of the NMOS transistor 26 (first output). The input to the NMOS transistor 26 of the 4 inverting differential amplifier 9d becomes HIGH level.

  Based on the output from the third inverting differential amplifier 9c, the LOW level is input to the NMOS transistor 25 of the fourth inverting differential amplifier 9d, and the HIGH level is input to the NMOS transistor 26. As a result, the NMOS transistor 25 is turned off, the NMOS transistor 26 is turned on, and the output of the NMOS transistor 25 (input to the NMOS transistor 26 of the first inversion-type differential amplifier 9a) is at the HIGH level, and the output of the NMOS transistor 26 (first output). The input to the NMOS transistor 25 of the 1-inverting differential amplifier 9a becomes LOW level.

  Based on the output from the fourth inverting differential amplifier 9d, the LOW level is input to the NMOS transistor 25 of the first inverting differential amplifier 9a, and the HIGH level is input to the NMOS transistor 26. As a result, the NMOS transistor 25 is turned off, the NMOS transistor 26 is turned on, the output of the NMOS transistor 25 (the input to the NMOS transistor 25 of the second inverting differential amplifier 9b) is HIGH level, and the output of the NMOS transistor 26 (first output). The input to the NMOS transistor 26 of the 2 inverting differential amplifier 9b becomes LOW level.

At first, the NMOS transistor 25 of the first inversion-type differential amplifier 9a is ON and the NMOS transistor 26 is OFF. When the ring makes one round (the first inversion-type differential amplifier 9a to the fourth inversion-type differential amplifier 9d), The NMOS transistor 25 of the 1-inverting amplifier 9a is OFF and the NMOS transistor 26 is ON. That is, the output of the fourth inverting differential amplifier 9d at the final stage is inverted and returned to the first inverting differential amplifier 9a at the first stage. Since this operation continues, it oscillates. As described above, when the level of the voltage V _cnt increases, the delay time of each of the first inversion-type differential amplifier 9a to the fourth inversion-type differential amplifier 9d is shortened, so that the oscillation frequency is increased.

  When N is an odd number equal to or greater than 3, when N is 3, the drain electrode of the NMOS transistor 25 of the third inverting differential amplifier 9c is connected to the first inverting differential amplifier 9a as shown in FIG. The gate electrode of the NMOS transistor 25 is connected to the level converter (LC) 7 through the first output terminal OUT1. The drain electrode of the NMOS transistor 26 is connected to the gate electrode of the NMOS transistor 26 of the first inverting differential amplifier 9a and the level converter (LC) 7 via the second output terminal OUT2. That is, the output of the third inverting differential amplifier 9c at the final stage is returned to the first inverting differential amplifier 9a at the first stage.

Since the voltage-controlled oscillator (VCO) 5 has an offset in the above-described free-running oscillation frequency _Fa1 , the frequency characteristics can be made less inclined. Therefore, when the voltage V _cnt including the noise component is input, the fluctuation of the oscillation frequency F _b1 described above can be reduced as compared with the voltage controlled oscillator having no offset.

  Here, the frequency characteristics of the voltage controlled oscillator (VCO) 5 according to the first embodiment will be described with reference to FIG. FIG. 5 is a diagram illustrating frequency characteristics of the voltage controlled oscillator (VCO) according to the first embodiment.

As shown in FIG. 5, the symbol Y <b> 1 represents the frequency characteristic at the time of type-case. At this time, the free-running oscillation frequency F _a1 is about 500 (MHz). Also, due to manufacturing variations, there are frequency characteristics at fast-case such as symbol Y1 ′ and frequency characteristics at slow-case such as symbol Y1 ″.

In the frequency characteristic (fast-case) indicated by the reference symbol Y1 ′, the free-running oscillation frequency _Fa2 is about 600 (MHz). As the voltage V _cnt increases, the voltage for obtaining the desired oscillation frequency F _b1 corresponding to the output signal F _VCO is V _b1 , V _a1 <V _b1 <V _DD , and the oscillation frequency F _b1 is 1000 (MHz). When the level reaches V _b1, the frequency characteristic (typ-case) indicated by the sign Y1 is about 1000 (MHz), and the frequency characteristic (fast-case) indicated by the sign Y1 ′ is about 40% faster than the type-case. 1400 (MHz). In the frequency characteristic (slow-case) indicated by the symbol Y1 ″, the free-running oscillation frequency F _a3 is about 400 (MHz). When the voltage V _cnt increases and reaches the level of V _b1 , the frequency characteristic (typ-case) indicated by the sign Y1 is about 1000 (MHz), and the frequency characteristic (slow-case) indicated by the sign Y1 ″ is It is 600 (MHz), which is 30% slower than the type-case.

Thus, when a voltage _{V cnt} becomes larger, the frequency characteristics of the conventional voltage controlled oscillator (VCO) 105, when the voltage _{V cnt} becomes larger, the frequency indicated by the variation upper limit side (reference numeral Y101 ' In the frequency characteristic of the voltage controlled oscillator (VCO) 5, the variation is 55% on the lower limit side (frequency characteristic indicated by the symbol Y101 ″), whereas the variation in the frequency characteristic of the voltage controlled oscillator (VCO) 5 is on the upper limit side (reference symbol Y1). The frequency characteristic indicated by 'is improved to 40%, and the lower limit side (frequency characteristic indicated by symbol Y1'') is improved to 30%. Since the voltage controlled oscillator (VCO) 5 uses the current mirror circuit to the minimum necessary, the influence of the channel length modulation effect can be reduced, and variations in the oscillation frequency can be suppressed. Further, since the voltage controlled oscillator (VCO) 5 does not need to increase the gain of the voltage controlled oscillator (VCO) 5, jitter is reduced. In addition, the voltage controlled oscillator (VCO) 5 is, for example, a frequency range that can be suppressed to a minimum even if the voltage V _cnt is not increased to the value of the power supply voltage V _{DD in} the frequency characteristic indicated by the symbol Y1 ″ shown in FIG. F ₁ can be secured. This frequency range F ₁ represents from the free-running oscillation frequency F _a2 in the frequency characteristic indicated by the symbol Y1 ′ to the oscillation frequency when the voltage V _cnt is the value of the power supply voltage V _{DD in} the frequency characteristic indicated by the symbol Y1 ″. includes a desired oscillation frequency _{F b1} is the frequency range _{F 1.} Therefore, the voltage-controlled oscillator (VCO) 5 can set the controllable oscillation frequency range within the range of the voltage V _cnt in consideration of the fluctuation of the oscillation frequency.

  Next, the configuration of a PLL circuit using the voltage controlled oscillator (VCO) 5 according to the first embodiment will be described with reference to FIG. 3 taking a PLL (Phase-Locked Loop) as an example. FIG. 3 is a block diagram showing a configuration of a PLL circuit using the voltage controlled oscillator (VCO) according to the first embodiment.

  As shown in FIG. 3, the PLL circuit includes a phase frequency comparator (PFD) 1, a charge pump 2, a loop filter 3, an offset circuit (OFST) 4, a voltage controlled oscillator (VCO) 5, and a frequency divider 6. ing.

The phase frequency comparator (PFD) 1 compares the phase and frequency of the input signal F _ref and the feedback signal F _fb from the frequency divider 6, and an incremental signal (a rising instruction signal) UP representing an error between the two signals. A decrement signal (down instruction signal) DOWN is generated. For example, a clock signal from an oscillator (not shown) is used as the input signal F _ref . The increment signal UP generated by the phase frequency comparator (PFD) 1 has a pulse width corresponding to the frequency drop and phase delay of the feedback signal F _fb with respect to the input signal F _ref . The decrement signal DOWN has a pulse width corresponding to the frequency increase and phase advance of the feedback signal F _fb with respect to the input signal F _ref . The increment signal UP and the decrement signal DOWN generated by the phase frequency comparator (PFD) 1 are supplied to the charge pump 2.

The charge pump 2 is a single output charge pump, and generates a current pulse corresponding to each pulse width of the increment signal UP and the decrement signal DOWN and supplies the current pulse to the loop filter 3. In response to the current pulse supplied from the charge pump 2, the loop filter 3 accumulates charges in a capacitor (not shown), for example, and discharges the charges accumulated in the capacitor (not shown), and responds to the current pulse described above. A voltage V _cnt is generated. The voltage V _cnt generated by the loop filter 3 is supplied to a voltage controlled oscillator (VCO) 5.

An offset circuit (OFST) 4 as a bias circuit generates a constant voltage V _cn1 and supplies it to a bias generator (BG) 8 and a ring oscillator (RO) 9 of a voltage controlled oscillator (VCO) 5. A constant voltage V _cn1 is supplied from an offset circuit (OFST) 4 and a voltage V _cnt is supplied from a loop filter 3 to a bias generator (BG) 8 and a ring oscillator (RO) 9 of a voltage controlled oscillator (VCO) 5. . The voltage controlled oscillator (VCO) 5 includes a current I _cn1 according to the value of the constant voltage V _cn1 supplied from the offset circuit (OFST) 4 and a current I according to the value of the voltage V _cnt supplied from the loop filter 3. _The output signal F _VCO that oscillates at a frequency corresponding to the added current is generated by adding _cnt . This oscillation frequency is directly determined by a current obtained by adding a current I _cn1 corresponding to the value of the constant voltage V _cn1 and a current I _cnt corresponding to the value of the voltage V _cnt . In the locked state, the voltage controlled oscillator (VCO) 5 oscillates at a frequency that is M times the frequency of the input signal F _ref (M is a real number).

The output signal F _VCO generated by the voltage controlled oscillator (VCO) 5 is sent to the outside as an output signal of the PLL circuit from the level converter ( _LC ) 7 and also supplied to the frequency divider 6. The frequency divider 6 _divides the output signal F _VCO by 1 / N and supplies it to the phase frequency comparator (PFD) 1.

  Next, the operation of the PLL circuit using the voltage controlled oscillator (VCO) 5 according to the first embodiment will be described.

Assume that the phase of the feedback signal F _fb fed back from the frequency divider 6 to the phase frequency comparator (PFD) 1 is delayed from the phase of the input signal F _ref . In this case, the phase frequency comparator (PFD) 1 generates an increment signal UP having a pulse width corresponding to the frequency drop and the phase delay, and supplies the increment signal UP to the charge pump 2. The charge pump 2 discharges a current corresponding to the increment signal UP and charges a capacitor (not shown) of the loop filter 3. As a result, the voltage V _cnt generated by the loop filter 3 is increased. As a result, the oscillation frequency of the output signal F _VCO output from the voltage controlled oscillator (VCO) 5 increases, and the phase of the output signal F _VCO advances to approach the phase of the input signal F _ref .

On the other hand, when the phase of the feedback signal F _fb is advanced from the phase of the input signal F _ref , the phase frequency comparator (PFD) 1 generates a decrement signal DOWN having a pulse width corresponding to the frequency increase and the phase advance. And supplied to the charge pump 2. The charge pump 2 draws a current corresponding to the decrement signal DOWN to discharge a capacitor (not shown) of the loop filter 3. As a result, the voltage V _cnt output from the loop filter 3 is lowered. As a result, the oscillation frequency of the output signal F _VCO output from the voltage controlled oscillator (VCO) 5 decreases, and the phase of the output signal F _VCO is delayed and approaches the phase of the input signal F _ref .

Thus, in the PLL circuit using the voltage controlled oscillator (VCO) 5 according to the first embodiment, the phase and frequency of the output signal F _{VCO and} the phase and frequency of the input signal F _ref are always compared, and the input signal F If there is a phase lag or phase advance of the output signal F _VCO with respect to _ref , feedback control is performed to correct them. When the phase lag or phase advance converges within a predetermined range, the phase frequency comparator (PFD) 1 generates an increment signal UP and a decrement signal DOWN having the same short pulse width. As a result, the amount of charge charged / discharged by a capacitor (not shown) of the loop filter 3 is equalized and balanced, and the PLL circuit enters a locked state. In this locked state, the phase of the output signal F _VCO matches the phase of the input signal F _ref . Further, in the PLL circuit using the voltage controlled oscillator (VCO) 5 according to the first embodiment, when the noise component is included in the voltage V _cnt output from the loop filter 3, the offset frequency is given, so that the offset The fluctuation of the desired oscillation frequency can be suppressed to a smaller level compared to the one without frequency, and the current mirror circuit is used to the minimum necessary, so the influence of channel length modulation effect is small and the oscillation frequency due to manufacturing variations The variation of can be kept low.

  As described above, according to the voltage controlled oscillator (VCO) 5 according to the first embodiment, since the current mirror circuit is used as much as possible, the influence of the channel length modulation effect can be reduced, and the oscillation frequency varies. Can be suppressed.

  Further, according to the voltage controlled oscillator (VCO) 5 according to the first embodiment, it is not necessary to increase the gain of the voltage controlled oscillator (VCO) 5, so that jitter is reduced.

Further, according to the voltage controlled oscillator (VCO) 5 according to the first embodiment, it is possible to take a wide oscillation frequency range that can be controlled within the range of the voltage V _cnt in consideration of fluctuations in the oscillation frequency.

(Embodiment 2)
Next, a voltage controlled oscillator (VCO) according to the second embodiment will be described with reference to FIG.

  As shown in FIG. 6, the voltage controlled oscillator (VCO) 55 according to the second embodiment includes a bias generator (BG) 58, a ring oscillator (RO) 9, and a level converter (LC) 7. That is, the voltage controlled oscillator (VCO) 55 according to the second embodiment includes a bias generator (BG) 58 instead of the bias generator (BG) 8. Here, in the voltage controlled oscillator (VCO) 55 according to the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals. Further, since the operation of the voltage controlled oscillator (VCO) 55 according to the second embodiment is the same as that of the voltage controlled oscillator (VCO) 5 according to the first embodiment, the description thereof is omitted.

A voltage controlled oscillator (VCO) 5 according to the first embodiment, addition and bias generator (BG) 8 current _{I cn1} corresponding to the value of the constant voltage _{V cn1,} and a current _{I cnt} corresponding to the value of the voltage _{V cnt} In the voltage controlled oscillator (VCO) 55 according to the second embodiment, the bias generator (BG) 58 corresponds to the value of the constant voltage V _cn1 . The operating current of the ring oscillator (RO) 9 can be compensated only by the current _Icn1 . Thereby, in addition to the effects of the first embodiment, the number of transistors of the voltage controlled oscillator (VCO) 55 according to the second embodiment is smaller than that of the voltage controlled oscillator (VCO) 5 according to the first embodiment. Therefore, the influence of manufacturing variations can be reduced.

  In this case, the bias generator (BG) 58 has only the PMOS transistor 11 and the NMOS transistor 12. That is, the bias generator (BG) 58 is a circuit in which the NMOS transistor 13 of the bias generator (BG) 8 in the first embodiment is removed. As shown in FIG. 6, when N is an even number equal to or greater than 2, when N is 4, the output of the fourth inverting differential amplifier 9d at the final stage is inverted to the first inverting differential amplifier 9a at the first stage. And returned. As shown in FIG. 7, when N is an odd number equal to or greater than 3, when N is 3, the output of the third inverting differential amplifier 9c at the final stage is returned to the first inverting differential amplifier 9a at the first stage.

The constant voltage V _cn1 input to the voltage controlled oscillator (VCO) 55 is described in the first embodiment in order to increase the ability of the bias generator (BG) 58 to compensate the operating current of the ring oscillator (RO) 9. It is desirable that the voltage is higher than the constant voltage V _cn1 input to the voltage controlled oscillator (VCO) 5.

  As shown in FIG. 8, the PLL circuit shown in FIG. 3 is replaced with the voltage controlled oscillator (VCO) 55 according to the second embodiment instead of the voltage controlled oscillator (VCO) 5 according to the first embodiment. Can be used. Here, in the PLL circuit using the voltage controlled oscillator (VCO) 55 according to the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals. The operation of the PLL circuit using the voltage controlled oscillator (VCO) 55 according to the second embodiment is the same as that of the PLL circuit using the voltage controlled oscillator (VCO) 5 according to the first embodiment.

  As described above, according to the voltage controlled oscillator (VCO) 55 according to the second embodiment, in addition to the effects of the first embodiment, the number of transistors is different from that of the voltage controlled oscillator (VCO) 5 according to the first embodiment. Therefore, the influence of manufacturing variations is reduced.

(Embodiment 3)
Next, a voltage controlled oscillator (VCO) according to Embodiment 3 will be described with reference to FIG.

  As shown in FIG. 9, the voltage controlled oscillator (VCO) 75 according to the third embodiment includes a ring oscillator (RO) 79 and a level converter (LC) 7. Here, in the voltage controlled oscillator (VCO) 75 according to the third embodiment, the same components as those in the first embodiment are denoted by the same reference numerals. Further, the operation of the voltage controlled oscillator (VCO) 75 according to the third embodiment is the same as that of the voltage controlled oscillator (VCO) 5 according to the first embodiment, and thus the description thereof is omitted.

A voltage controlled oscillator (VCO) 5 according to the first embodiment, addition and bias generator (BG) 8 current _{I cn1} corresponding to the value of the constant voltage _{V cn1,} and a current _{I cnt} corresponding to the value of the voltage _{V cnt} Although the operating current of the ring oscillator (RO) 9 is compensated by the current thus generated, the voltage controlled oscillator (VCO) 75 according to the third embodiment does not require the bias generator (BG) 8, and the first or second embodiment. As compared with the first and second embodiments, the circuit configuration can be simplified by using a PMOS transistor as an active element of the ring oscillator (RO) 9 in FIG. Thereby, in addition to the effect of the first embodiment, the voltage controlled oscillator (VCO) 75 according to the third embodiment does not use the current mirror circuit, and thus can further suppress the variation in the oscillation frequency.

  Next, the configuration of the ring oscillator (RO) 79 will be described.

As shown in FIG. 9, when N is 4, the ring oscillator (RO) 79 includes a first inverting differential amplifier 79a, a second inverting differential amplifier 79b, a third inverting differential amplifier 79c, and a fourth inverting difference. A dynamic amplifier 79d is provided. Each of the first inverting differential amplifier 79a to the fourth inverting differential amplifier 79d operates in accordance with an external constant voltage V _cn1 and an external voltage V _cnt, and the resistive elements 81, 82, has NMOS transistors 25 and 26, and a NMOS transistor 27, NMOS transistor 28 which is driven by a voltage _{V cnt} driven by constant voltage _{V cn1} as a current source connected to the differential unit. Each of the operating current of the first inverting differential amplifier 79a~ fourth inverting differential amplifier 79d is summed with current _{I cn1} corresponding to the value of the constant voltage _{V cn1,} and a current _{I cnt} corresponding to the value of the voltage _{V cnt} The direct current is determined.

  The configuration of each of the first inverting differential amplifier 79a to the fourth inverting differential amplifier 79d will be described.

A high voltage source is connected to one terminal of both ends of the resistance elements 81 and 82, and the power supply voltage V _DD is input / supplied. A constant voltage _Vcn1 is input / supplied to the gate electrode of the NMOS transistor 27 from the outside. The source electrode of the NMOS transistor 27 is connected to the lower power supply and is usually grounded. A voltage V _cnt is input / supplied to the gate electrode of the NMOS transistor 28 from the outside. The source electrode of the NMOS transistor 28 is connected to the lower power supply and is usually grounded. The drain electrode of the NMOS transistor 28 is connected to the drain electrode of the NMOS transistor 27 and the source electrodes of the NMOS transistors 25 and 26. The drain electrode of the NMOS transistor 25 is connected to the other terminal of the resistance element 81. The drain electrode of the NMOS transistor 26 is connected to the other terminal of the resistance element 82.

  The gate electrode of the NMOS transistor 25 of the second inverting differential amplifier 79b is connected to the drain electrode of the NMOS transistor 25 of the first inverting differential amplifier 79a. The gate electrode of the NMOS transistor 26 of the second inverting differential amplifier 79b is connected to the drain electrode of the NMOS transistor 26 of the first inverting differential amplifier 79a.

  The gate electrode of the NMOS transistor 25 of the third inverting differential amplifier 79c is connected to the drain electrode of the NMOS transistor 25 of the second inverting differential amplifier 79b. The gate electrode of the NMOS transistor 26 of the third inverting differential amplifier 79c is connected to the drain electrode of the NMOS transistor 26 of the second inverting differential amplifier 79b.

  The gate electrode of the NMOS transistor 25 of the fourth inverting differential amplifier 79d is connected to the drain electrode of the NMOS transistor 25 of the third inverting differential amplifier 79c. The gate electrode of the NMOS transistor 26 of the fourth inverting differential amplifier 79d is connected to the drain electrode of the NMOS transistor 26 of the third inverting differential amplifier 79c.

  The gate electrode of the NMOS transistor 25 of the first inverting differential amplifier 79a is connected to the drain electrode of the NMOS transistor 26 of the fourth inverting differential amplifier 79d. The gate electrode of the NMOS transistor 26 of the first inverting differential amplifier 79a is connected to the drain electrode of the NMOS transistor 25 of the fourth inverting differential amplifier 79d. The drain electrode of the NMOS transistor 25 of the fourth inverting differential amplifier 79d is connected to the level converter (LC) 7 through the first output terminal OUT1. The drain electrode of the NMOS transistor 26 of the fourth inverting differential amplifier 79d is connected to the level converter (LC) 7 via the second output terminal OUT2.

  Thus, the output of the fourth inverting differential amplifier 9d at the final stage is inverted and returned to the first inverting differential amplifier 9a at the first stage. Further, as shown in FIG. 10, when N is an odd number of 3 or more, when N is 3, the output of the third inverting differential amplifier 9c at the final stage is returned to the first inverting differential amplifier 9a at the first stage. .

  Thereby, in addition to the effect of the first embodiment, the voltage controlled oscillator (VCO) 75 according to the third embodiment does not use the current mirror circuit, and thus can further suppress the variation in the oscillation frequency.

  As shown in FIG. 11, the PLL circuit shown in FIG. 3 has a voltage controlled oscillator (VCO) 75 according to the third embodiment instead of the voltage controlled oscillator (VCO) 5 according to the first embodiment. Can be used. Here, in the PLL circuit using the voltage controlled oscillator (VCO) 75 according to the third embodiment, the same components as those in the first embodiment are denoted by the same reference numerals. The operation of the PLL circuit using the voltage controlled oscillator (VCO) 75 according to the third embodiment is the same as that of the PLL circuit using the voltage controlled oscillator (VCO) 5 according to the first embodiment.

  As described above, according to the voltage controlled oscillator (VCO) 75 according to the third embodiment, in addition to the effect of the first embodiment, since the current mirror circuit is not used, the variation in the oscillation frequency can be further suppressed. it can.

1 Phase frequency comparator (PFD)
2 Charge pump 3 Loop filter 4 Offset circuit (OFST)
5 Voltage controlled oscillator (VCO)
6 Divider 7 Level converter (LC)
8 Bias generator (BG)
9 Ring oscillator (RO)
9a 1st inverting differential amplifier 9b 2nd inverting differential amplifier 9c 3rd inverting differential amplifier 9d 4th inverting differential amplifier 11 P channel MOS transistor 12, 13 N channel MOS transistor 21, 22, 23, 24 P channel MOS Transistors 25, 26, 27, 28 N-channel MOS transistor 55 Voltage controlled oscillator (VCO)
58 Bias generator (BG)
75 Voltage controlled oscillator (VCO)
79 Ring Oscillator (RO)
79a First inverting differential amplifier 79b Second inverting differential amplifier 79c Third inverting differential amplifier 79d Fourth inverting differential amplifier 81, 82 Resistance element 101 Phase frequency comparator (PFD)
102 Charge pump 103 Loop filter 104 Offset circuit (OFST)
105 Voltage controlled oscillator (VCO)
106 Frequency divider 107 Level converter (LC)
108 Bias generator (BG)
109 Ring Oscillator (RO)
109a First inversion differential amplifier 109b Second inversion differential amplifier 109c Third inversion differential amplifier 109d Fourth inversion differential amplifier 111 P channel MOS transistors 112, 113 N channel MOS transistors 114, 121, 122, 123, 124 P Channel MOS transistors 125, 126, 129 N-channel MOS transistor DOWN Decrement signal F _fb feedback signal F _ref input signal F _VCO output signal OUT1 first output terminal OUT2 second output terminal UP incremental signal V _cn1 constant voltage V _cnt voltage V _DD Power-supply voltage

Claims (6)

A plurality of currents connected in series and corresponding to a constant voltage for giving an offset frequency and a current corresponding to a control voltage for controlling the oscillation frequency are added and oscillated at a frequency corresponding to the added current . and the inverting differential amplifier,
A level converter that outputs the output of the inverting differential amplifier at the final stage of the plurality of inverting differential amplifiers as an output signal;
A bias generator for compensating an operating current of each of the plurality of inverting differential amplifiers;
Comprising
Each of the plurality of inverting differential amplifiers includes:
First and second output stage transistors whose gates are supplied with the output of the preceding inverting differential amplifier;
A first N-type transistor having a drain connected to the first and second output stage transistors and a gate supplied with the constant voltage;
A second N-type transistor having a drain connected to the first and second output stage transistors and a gate supplied with the control voltage;
First and second P-type transistors each having a power supply voltage supplied to a source and the first and second output stage transistors connected to a drain;
Comprising
The bias generator is
Third and fourth N-type transistors whose gates are supplied with the constant voltage and the control voltage, respectively;
The source voltage is supplied to the source, the drains of the third and fourth N-type transistors are connected to the drain, and the gates of the first and second P-type transistors are connected to the gate and drain so as to form a current mirror. A connected third P-type transistor and
A voltage controlled oscillator comprising: Each of the plurality of inverting differential amplifiers includes:
Fourth and fifth P-type transistors having gates and drains connected, and connected in parallel with the first and second P-type transistors, respectively.
The voltage controlled oscillator according to claim 1, further comprising: The first and second output stage transistors are N-type transistors, the drains of the first and second N-type transistors are connected to the sources, and the drains of the first and second P-type transistors are connected to the drains, respectively. ,
The drains of the first and second output stage transistors are used as an output to the next-stage inverting differential amplifier.
The voltage controlled oscillator according to claim 1 or 2. If the N is even number, the output of the inverting differential amplifier of the last stage of the plurality of inverting differential amplifier is inverted to the first stage inverting differential amplifier of the plurality of inverting differential amplifier Returned
The voltage controlled oscillator according to claim 1 . If the N is an odd integer greater than 3, the output of the inverting differential amplifier of the last stage of the plurality of inverting differential amplifier, the first stage of inverting differential amplifier of the plurality of inverting differential amplifier Returned
The voltage controlled oscillator according to claim 1 . A voltage controlled oscillator according to any one of claims 1 to 5;
Comparing the phase and frequency of the input signal and the feedback signal to generate said control voltage based on a result of the comparison, a control voltage generator for outputting to said voltage controlled oscillator,
And an offset circuit for said generating a constant voltage, and outputs to the voltage controlled oscillator,
PLL circuit and a frequency divider for the output signal outputted from the pre-Symbol voltage controlled oscillator by dividing outputs as the feedback signal to the control voltage generator.

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