JP2002198784A - Ring oscillator voltage controlled oscillator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ring oscillator voltage controlled oscillator that can obtain a clock signal of a desired duty ratio by means of a comparatively simple circuit requiring less number of components independently of the level of a frequency control voltage or other factors. SOLUTION: The ring oscillator voltage controlled oscillator is provided with a threshold voltage control circuit BB that receives the frequency control voltage and increases/decreases the threshold voltage depending on the level of the frequency control voltage at a post-stage of a feedback loop consisting of inverters BA1-BAn. Thus, the threshold voltage control circuit BB can correct the duty ratio changed depending on the level of the frequency control voltage to make it constant.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an odd number having a feedback loop for inputting a frequency control voltage for controlling the level of a frequency in accordance with the magnitude of a voltage and sequentially connecting the input and output to generate a clock signal. Changing the threshold value of the inverters according to the magnitude of the frequency control voltage,
The present invention relates to a ring oscillator type voltage controlled oscillation circuit which changes the oscillation frequency of a clock signal according to the magnitude of the frequency control voltage by changing the length of the signal delay time of these inverters. The present invention relates to a ring oscillator type voltage controlled oscillation circuit which is relatively simple and has a small number of elements and can obtain a clock signal having a desired duty ratio regardless of the magnitude of a frequency control voltage and the like.

[0002]

2. Description of the Related Art FIG. 7 shows a general PLL (Phase-locked L) using a ring oscillator type voltage controlled oscillation circuit.
3 is a circuit diagram of an oop) circuit.

[0003] As shown in the figure, a PLL circuit usually has a phase frequency (PFD (Phase & Frequency Detector)).
Circuit 10 and charge pump (CP)
p)) A phase comparison circuit composed of a circuit 12, a low-pass filter circuit (LPF (Low Pass Filter)) 14, and a voltage controlled oscillator circuit VCO (Voltage Controlled Oscilla).
tor) 16.

In such a ring oscillator type voltage controlled oscillation circuit, the low-pass filter circuit 14 can be constituted by resistors R5 and R6 and a capacitor C as shown as an example in FIG. Further, as the voltage controlled oscillation circuit 16,
For example, a ring oscillator type voltage controlled oscillation circuit as shown in FIG. 9 as an object of the present invention can be used.

In FIG. 9, a ring oscillator type voltage controlled oscillation circuit receives a frequency control voltage VCT for controlling the level of the frequency depending on the magnitude of the voltage.
Further, it has an odd number n of inverters BA1 to BAn that are sequentially connected at the input and the output and constitute a feedback loop for generating the clock signal CLK. In such a ring oscillator type voltage controlled oscillation circuit, the threshold values of the inverters BA1 to BAn are changed according to the magnitude of the frequency control voltage VCT, and the inverters BA1 to BAn are changed.
By changing the length of the signal delay time An, the clock signal CL is changed according to the magnitude of the frequency control voltage VCT.
The oscillation frequency of K is raised and lowered. The clock signal CLK is output via the buffer B.

FIG. 10 is a circuit diagram showing an example of the inverters BA1 to BAn.

[0007] As shown in FIG.
An is a P-channel MOS transistor TP
21 and N-channel MOS transistors TN21 and T
It is composed of N22 and a resistor R7. The inverter B
In A1 to BAn, Si is an input, Su is an output, and VCT is an input of a frequency control voltage. The threshold values of the inverters BA1 to BAn are changed according to the frequency control voltage VCT.

[0008]

FIG. 11 is a time chart of signals at point P2 in the circuit diagram of FIG.

In FIG. 11, a waveform S21 and a waveform S
22, the waveform S23 and the waveform S24 show that the frequency control voltage VCT is 0.0 volt, 0.5 volt, 0.7
Bolts and 1.8 volts. As is apparent from this figure, the oscillation frequency of the clock signal CLK can be raised or lowered according to the magnitude of the frequency control voltage VCT.

However, when the frequency control voltage VCT is low and the oscillation frequency of the clock signal CLK is low, for example, the waveforms S21 and S22 fall slowly,
On the other hand, the frequency control voltage VCT is high and the clock signal CL is high.
When the oscillation frequency of K is high, for example, the waveforms S23 and S24
In such cases, the fall becomes steep, so that the clock signal CLK
Changes depending on the magnitude of the frequency control voltage VCT.

In the following description, the duty ratio is the ratio of the time during which the state is H in one cycle. That is, assuming that the cycle is Tc, and the time during which the H state is reached in one cycle is Th, the duty ratio R is (Th / Tc). However, for example, assuming negative logic, the duty ratio R is changed to the ratio R (= (Tl / T
c)).

FIG. 12 is a time chart of signals at point P1 in the circuit diagram of FIG. 9, that is, at the output of the ring oscillator type voltage controlled oscillation circuit.

In FIG. 12, a waveform S31, a waveform S
32, the waveform S33, and the waveform S34 indicate that the frequency control voltage VCT is 0.0 volt, 0.5 volt, 0.7
Bolts and 1.8 volts. As is apparent from this figure, the oscillation frequency of the clock signal CLK can be raised or lowered according to the magnitude of the frequency control voltage VCT.

However, the duty ratio of the clock signal CLK, which is targeted at 50.0%, changes according to the magnitude of the frequency control voltage VCT. Waveform S31, waveform S32, waveform S33, waveform S
34, each has a duty ratio as shown,
63.9 percent, 59.2 percent, 53.4 percent, and 45.6 percent.

In JP-A-7-66693, inverters BA1 to BA1 used in a feedback loop for oscillating a clock signal are disclosed.
n is constituted by three stages of inverters, and the duty ratio is improved in each of the inverters BA1 to BAn. However, high frequency operation is difficult because the inverter has many stages.

In Japanese Patent Application Laid-Open No. 11-243327, a clock signal having a desired duty ratio can be obtained regardless of the magnitude of the frequency control voltage and the like. However, the circuit to be used is complicated, such as using two differential amplifiers as a comparator, and there are problems in that the number of elements is large, the circuit area is increased, and the degree of integration is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and is a relatively simple circuit having a small number of elements, and a clock having a desired duty ratio irrespective of the magnitude of a frequency control voltage and the like. It is an object of the present invention to provide a ring oscillator type voltage controlled oscillation circuit capable of obtaining a signal.

[0018]

According to the present invention, a feedback loop for inputting a frequency control voltage for controlling the level of a frequency in accordance with the magnitude of a voltage and sequentially connecting the input and output to form a clock signal is provided. The threshold value of the odd number of inverters is changed according to the magnitude of the frequency control voltage, and the length of the signal delay time of these inverters is changed. In a ring oscillator type voltage controlled oscillation circuit configured to raise or lower an oscillation frequency of a signal, a threshold voltage control circuit that inputs the frequency control voltage and raises or lowers a threshold voltage according to the magnitude of the voltage is provided by the feedback control circuit. The above-mentioned problem is solved by providing at the subsequent stage of the loop.

Hereinafter, the operation of the present invention will be briefly described.

In the present invention, a frequency control voltage for controlling the level of the frequency of the clock signal CLK obtained from the ring oscillator type voltage controlled oscillation circuit is input according to the magnitude of the voltage, and the magnitude of the voltage is controlled. In response to the,
A threshold voltage control circuit for raising and lowering the threshold voltage is provided at a stage subsequent to the feedback loop. The threshold voltage control circuit is, for example, as described in an embodiment described later,
This circuit is simpler and has a smaller number of elements than the two differential amplifiers used in the circuit 27.

The threshold voltage control circuit raises or lowers the threshold voltage according to the magnitude of the frequency control voltage, and adjusts the duty ratio of the generated clock signal. Therefore,
In the conventional ring oscillator type voltage controlled oscillation circuit, the threshold voltage control circuit can correct the duty ratio changed according to the magnitude of the frequency control voltage so as to be constant.

When a threshold voltage control circuit according to the present invention is a semiconductor integrated circuit, it can be formed together with other circuits in a ring oscillator type voltage controlled oscillation circuit such as a circuit constituting a feedback loop. Therefore, it is also possible to suppress fluctuations in the duty ratio due to various factors such as fluctuations in the ambient temperature during operation and fluctuations in the manufacturing process of the semiconductor integrated circuit.

As described above, according to the present invention, a clock signal having a desired duty ratio can be obtained with a relatively simple circuit having a small number of elements regardless of the magnitude of the frequency control voltage and the like.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a ring oscillator type voltage controlled oscillation circuit according to an embodiment to which the present invention is applied.
In this embodiment, a threshold voltage control circuit BB and an inverter BC are provided instead of the buffer B in the conventional example of FIG. Also, an odd number of inverters BA1 to BA1 constituting the ring oscillator type voltage controlled oscillation circuit of the present embodiment.
For n, the same one as in the prior art can be used, that is, for example, a circuit as shown in FIG. 10 can be used.
Further, as the inverters BA1 to BAn, circuits of first to third examples of a threshold voltage control circuit BB to be described later can also be used.

FIG. 2 is a circuit diagram of a first example of the threshold voltage control circuit BB used in the present embodiment. FIG. 3 is a circuit diagram of a second example of the threshold voltage control circuit BB used in the present embodiment. FIG. 4 is a circuit diagram of a third example of the threshold voltage control circuit BB used in the present embodiment. In each case, Si is an input for the clock signal, and Su
Is an output related to a clock signal, and VCT is an input of a frequency control voltage. The resistors R1 to R4 are provided as needed.

In the threshold voltage control circuit BB of the first example, an N-channel MOS transistor TN12 for inputting a frequency control voltage VCT to the gate is connected to a P-channel MOS transistor TN12.
By adding to a normal inverter composed of the transistor TP11 and the N-channel MOS transistor TN11, the threshold value for inputting the clock signal output from the feedback loop is changed according to the magnitude of the frequency control voltage VCT. I have. The threshold is set to a frequency control voltage VC.
In the threshold voltage control circuit BB of the second example, the P-channel MOS transistor TP1 which inputs the frequency control voltage VCT to the gate is changed in accordance with the magnitude of T in the second example.
2 is added to a normal inverter composed of a P-channel MOS transistor TP11 and an N-channel MOS transistor TN11. In the third example of the threshold voltage control circuit BB, changing the threshold value in accordance with the magnitude of the frequency control voltage VCT is performed by a P-channel MO that inputs the frequency control voltage VCT to the gate.
The S transistor TP12 and the N channel MOS transistor TN12 are replaced by a P channel MOS transistor TP1.
This is performed by adding to a normal inverter composed of one and N-channel MOS transistors TN11.

FIG. 5 is a circuit diagram of a fourth example of the threshold voltage control circuit BB used in the present embodiment.

In the threshold voltage control circuit BB of the fourth example, a plurality of the threshold voltage control circuits BB of the first to third examples described above are used. That is, BB1 to BBm illustrated in FIG. 5 are the first to third examples described above, respectively.
One of the example threshold voltage control circuits BB. In the threshold voltage control circuit BB of the fourth example, the threshold voltage control circuits BB of the first to third examples may be mixed as a plurality of threshold voltage control circuits BB1 to BBm.

In this embodiment, in order to obtain a clock signal CLK having a desired duty ratio regardless of the magnitude of the frequency control voltage VCT, it is necessary to appropriately correct the duty ratio by a threshold voltage control circuit. .

That is, the threshold voltage control circuit is designed to cancel the tendency of the change in the duty ratio according to the magnitude of the frequency control voltage VCT in the signal obtained from the feedback loop of the oscillation circuit for obtaining the clock signal CLK. It is necessary to appropriately correct the duty ratio according to the magnitude of the frequency control voltage VCT.

The characteristics and degree of the duty ratio correction in the threshold voltage control circuit can be determined by which of the threshold voltage control circuits BB of the first to fourth examples described above and the resistances R1 to R4.
It depends on the presence or absence of R4 and its resistance value. or,
When the threshold voltage control circuit BB of the fourth example is used, the number of the threshold voltage control circuits BB1 to BBm and the threshold voltage control circuits of the first to third examples described above are added to the respective threshold voltage control circuits BB1 to BBm. It depends on which one of BB is used. Therefore, in order to appropriately correct the duty ratio, such a dependent element may be appropriately selected.

FIG. 6 is a time chart of signals at the output when the threshold voltage control circuit BB of the first example is used in the present embodiment. That is, it is a time chart of the signal at point P1 in the circuit diagram of FIG.

In FIG. 6, the waveform S11 and the waveform S1
2. Waveforms S13 and S14 are obtained when the frequency control voltage VCT is 0.0 volt, 0.5 volt, 0.7 volt, and 1.8 volt, respectively. As is apparent from this figure, the oscillation frequency of the clock signal CLK can be raised or lowered according to the magnitude of the frequency control voltage VCT.

Further, the duty ratio of the clock signal CLK, which is targeted at 50.0%, is almost properly corrected by applying the present invention regardless of the magnitude of the frequency control voltage VCT. That is, the waveform S1
1, the waveforms S12, S13, and S14 have the duty ratios of 50.6%, 51.8%, 53.3%, and 49.
1 percent.

In the case of FIG. 12 of the conventional example described above, the duty ratio is 45.6% to 63.9%. On the other hand, in the case of FIG. 6 of the present embodiment, the duty ratio is 49.0% to 53.3%. Further, in the present embodiment, such a change in the duty ratio can be further suppressed by appropriately selecting the dependent element as described above.

As described above, in the present embodiment, the present invention can be effectively applied. Therefore, in the present embodiment, a clock signal having a desired duty ratio can be obtained by a relatively simple circuit having a small number of elements, regardless of the magnitude of the frequency control voltage and the like.

[0038]

According to the present invention, a clock signal having a desired duty ratio can be obtained with a relatively simple circuit having a small number of elements, regardless of the magnitude of the frequency control voltage or the like.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a ring oscillator type voltage controlled oscillator circuit according to an embodiment to which the present invention is applied.

FIG. 2 is a circuit diagram of a first example of a threshold voltage control circuit used in the embodiment.

FIG. 3 is a circuit diagram of a second example of the threshold voltage control circuit;

FIG. 4 is a circuit diagram of a third example of the threshold voltage control circuit;

FIG. 5 is a circuit diagram of a fourth example of the threshold voltage control circuit;

FIG. 6 is a time chart of a signal at an output when the threshold voltage control circuit of the first example is used in the embodiment.

FIG. 7 is a circuit diagram of a general PLL circuit using a ring oscillator type voltage controlled oscillator.

FIG. 8 is a circuit diagram illustrating an example of a low-pass filter circuit used in the PLL circuit;

FIG. 9 is a circuit diagram of an example of a conventional ring oscillator type voltage controlled oscillation circuit used for the PLL circuit.

FIG. 10 is a circuit diagram of an example of an inverter used in the ring oscillator type voltage controlled oscillation circuit.

11 is a time chart of a signal at a point P2 in the circuit diagram of FIG. 9;

FIG. 12 is a time chart of signals at the output of a conventional ring oscillator type voltage controlled oscillator.

[Explanation of symbols]

BA1 to BAn, BC: Inverter B: Buffer BB, BB1 to BBm: Threshold voltage control circuit TP11, TP12, TP21: P-channel MOS transistor TN11, TN12, TN21, TN22: N-channel MOS transistor R1 to R7: Resistor C: Capacitor VCT: Frequency control voltage CLK: Clock signal 10: Phase frequency detection circuit 12: Charge pump circuit 14: Low-pass filter circuit 16: Voltage controlled oscillator circuit

Claims (1)

[Claims] An input of a frequency control voltage for controlling the level of a frequency according to the magnitude of a voltage, and the threshold of an odd number of inverters forming a feedback loop for sequentially connecting input and output to generate a clock signal is set. By changing the length of the signal delay time of these inverters according to the magnitude of the frequency control voltage, the oscillation frequency of the clock signal is raised or lowered according to the magnitude of the frequency control voltage. In the ring oscillator type voltage controlled oscillation circuit described above, a threshold voltage control circuit that inputs the frequency control voltage and raises or lowers a threshold voltage according to the magnitude of the voltage is provided at a subsequent stage of the feedback loop. A ring oscillator type voltage controlled oscillator circuit characterized by the above.