JPH07321649A - Voltage controlled oscillator and pll circuit - Google Patents

Abstract

PURPOSE:To make PLL operation stable regardless of fluctuation in a power supply voltage by using a voltage without a voltage difference and a fluctuation for a power supply voltage regardless of the fluctuation of voltage in the PLL circuit using the voltage controlled oscillator and applying the power supply voltage to the oscillator. CONSTITUTION:A complete differential amplifier circuit 22 is used to apply a control voltage VC between a noninverting input terminal 23 and an inverting input terminal 24. Since the fluctuation in the power supply voltage appears between a noninverting output terminal 25 and an inverting output terminal 26 in the amplifier 22 as an in-phase output, a voltage difference of (VA-VB) between the terminals 25, 26 is unchanged. Thus, a stable oscillation is attained for the voltage controlled oscillator 57 regardless of fluctuation in a power supply voltage and an oscillated output OUT with a stable frequency is acquired.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage controlled oscillator and a phase locked loop circuit using the voltage controlled oscillator, that is, a so-called PLL (phase-locked loop) circuit.

[0002]

2. Description of the Related Art Conventionally, as a voltage controlled oscillator, a multivibrator type voltage controlled oscillator having a circuit diagram shown in FIG. 11 is known.

In FIG. 11, VDD is the power supply voltage on the high voltage side,
VSS is the power supply voltage on the low voltage side, 1-4 are MESFETs
(Metal Semiconductor Field Effect Transisto
r), 5 to 8 are resistors, and 9 is a capacitor.

This voltage controlled oscillator controls the control voltage VC to M
Supply to the gates of ESFET1 and ESFET2,
The charging and discharging of the capacitor 9 is repeated by using the current flowing through T1 and T2, and the MESFETs 3 and 4 are alternately conducted,
By non-conducting, the oscillation outputs OUT and / OUT having a frequency corresponding to the control voltage VC are obtained.

[0005]

In the voltage controlled oscillator shown in FIG. 11, when noise is superimposed on the power supply voltage VDD and the power supply voltage VDD fluctuates, the oscillation outputs OUT, /
There is a problem that the frequency of OUT fluctuates.

Therefore, in the PLL circuit using the voltage controlled oscillator shown in FIG. 11, there is a problem that stable PLL operation cannot be ensured.

In view of the above points, the present invention provides a voltage controlled oscillator capable of obtaining a stable oscillation output with a frequency regardless of the fluctuation of the power source voltage, and a stable voltage controlled oscillator regardless of the fluctuation of the power source voltage. It is an object of the present invention to provide a PLL circuit capable of ensuring PLL operation.

[0008]

[Means for Solving the Problems]

FIG. 1 is a diagram for explaining the principle of the voltage controlled oscillator of the present invention. In FIG. 1, 11 is a non-inverting output terminal and an inverting output with respect to the non-inverting input terminal and the inverting input terminal. And a fully differential amplifier with terminals.

In this fully differential amplifier 11, reference numerals 12 and 13 denote one input terminal and the other input terminal, for example, a non-inverting input terminal and an inverting input terminal, and 14 and 15, respectively.
Are one and the other output terminal, for example, a non-inverting output terminal and an inverting output terminal, respectively.

Reference numeral 16 is an oscillator which operates using the voltages VA and VB output to the output terminals 14 and 15 of the fully differential amplifier 11 as one and the other power supply voltages.

That is, the voltage controlled oscillator of the present invention includes a fully differential amplifier 11 to which a control voltage VC is supplied between one and the other input terminals 12 and 13, and one and the other output of the fully differential amplifier 11. Voltage V output to terminals 14 and 15
The oscillator 16 is configured to operate with A and VB as one and the other power supply voltages.

PLL circuit of the present invention: FIG. 2 FIG. 2 is a diagram for explaining the principle of the PLL circuit of the present invention.
In FIG. 2, 18 is the voltage controlled oscillator of the present invention shown in FIG.
Reference numerals 9 and 20 are impedance circuits that form a loop filter together with a fully differential amplifier.

That is, the PLL circuit of the present invention includes a fully differential amplifier 11 to which a control voltage VC is supplied between one and the other input terminals 12 and 13, and one and the other output terminals of the fully differential amplifier 11. The voltage VA output to 14, 15
Oscillator 1 operating with VB as one and the other power supply voltage
6 and impedance circuits 19 and 20 that form a loop filter together with the fully differential amplifier 11, and are configured to include a voltage controlled oscillator.

[0014]

In the fully differential amplifier 11, the fluctuation of the power supply voltage appears at the output terminals 14 and 15 as an in-phase output, so that the voltage difference VA-VB between the output terminals 14 and 15 does not change. That is, the fully differential amplifier 11 has an extremely high noise rejection ratio PSRR (power supply rejection ratio) = power supply fluctuation / output fluctuation ratio.

Therefore, according to the voltage controlled oscillator of the present invention, the voltage difference VA is generated even when the power supply voltage fluctuates.
Since the voltages VA and VB having no change in −VB can be supplied to the oscillator 16 as the power supply voltage, the oscillation output OUT with a stable frequency can be obtained regardless of the change in the power supply voltage.

Therefore, according to the PLL circuit of the present invention using the voltage controlled oscillator of the present invention, even if the power supply voltage changes, the voltage differences VA and VB can be changed to the voltages VA and VB which do not change. Since it can be supplied to the oscillator 16 as a power supply voltage, regardless of fluctuations in the power supply voltage,
It is possible to secure stable PLL operation.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 3 to 10, the first and second embodiments of the voltage controlled oscillator of the present invention and the PL of the present invention will be described below.
An example of using the first to third embodiments of the L circuit and the third embodiment of the PLL circuit of the present invention will be described.

First Embodiment of Voltage Controlled Oscillator of the Present Invention
3 and 4 FIG. 3 is a circuit diagram showing a first embodiment of the voltage controlled oscillator according to the present invention. In the figure, 22 is a fully differential amplifier, 23 is a non-inverting input terminal, 24 is an inverting input terminal, 25 is a non-inverting output terminal, and 26 is an inverting output terminal.

In this embodiment, the non-inverting input terminal 2
The control voltage VC is supplied between the 3 and the inverting input terminal 24, and the fully differential amplifier 22 can be configured as shown in FIG. 4, for example.

In FIG. 4, 28 is an input circuit section, and 29,
30 is a depletion type ME which forms an input transistor
SFETs 31, 31 and 32 are Schottky diodes composed of depletion type MESFETs for level shift, and 33 and 34 are depletion type M which form a constant current source.
ESFET.

Reference numeral 35 is a differential amplifier circuit section, and 3
Reference numerals 6 and 37 are load resistors, 38 and 39 are enhancement type MESFETs that form drive transistors, and 40 is an enhancement type MESFET that forms a current source.

Reference numeral 41 is a common mode feedback circuit section, and 42 and 43 are enhancement type MESFETs to which the output of the differential amplifier circuit section 35 is supplied.
Reference numerals 4 and 45 are load resistances, and 46 and 47 are depletion type MESFETs for level shift.
The diode 48 is an enhancement type MESFE which constitutes a current mirror circuit together with the MESFET 40.
T.

The common mode feedback circuit section 41 increases the current flowing through the differential amplification circuit section 35 when the output of the differential amplification circuit section 35 is high, and the output of the differential amplification circuit section 35. When is low, the current flowing through the differential amplifier circuit unit 35 is reduced and the output of the differential amplifier circuit unit 35 is controlled so as to be within a certain range.

Reference numeral 49 denotes an output circuit section, which is 50, 5
1 is an enhancement type ME that forms an output transistor
SFETs, 52 and 53 are Schottky diodes composed of depletion type MESFETs for level shift, and 54 and 55 are enhancement type M which form a current source.
ESFET and VE are bias voltages.

An enhancement type MESFET
55 is noise rejection ratio PSRR, common mode rejection ratio CMRR (co
It is intended to improve the mmon-mode rejection ratio) and is not necessarily required.

Further, in FIG. 3, reference numeral 57 is a ring oscillator, and this ring oscillator 57 converts the voltage VA output to the non-inverting output terminal 25 of the fully differential amplifier 22 into a power supply voltage on the high voltage side and a fully differential voltage. The voltage VB output to the inverting output terminal 26 of the amplifier 22 is configured to operate as a low-voltage side power supply voltage.

Reference numerals 58 to 62 are inverters, and
3 to 67 are resistors, 68 to 72 are enhancement type M
ESFET.

Here, in the fully differential amplifier 22,
Since the fluctuation of the power supply voltage appears as an in-phase output at the non-inverting output terminal 25 and the inverting output terminal 26, a voltage difference VA− between the non-inverting output terminal 25 and the inverting output terminal 26.
VB does not change.

Therefore, according to the voltage controlled oscillator of this embodiment, it is possible to cause the oscillator 57 to perform a stable oscillation operation regardless of the fluctuation of the power supply voltage, and to obtain the oscillation output OUT with a stable frequency. .

Second Embodiment of Voltage Controlled Oscillator of the Present Invention
5 is a circuit diagram showing a second embodiment of the voltage controlled oscillator according to the present invention. The voltage controlled oscillator of this embodiment is provided with a multivibrator 74 instead of the ring oscillator 57 shown in FIG. Is configured in the same manner as the voltage controlled oscillator shown in FIG.

In the multivibrator 74, 75 is an oscillation circuit section, 76 and 77 are resistors, and 78 is a resistor.
˜81 are enhancement type MESFETs, and 82 is a capacitor.

Further, 83 is the MESFE of the oscillation circuit section 75.
A common mode feedback circuit section for supplying a control voltage to the gates of T80 and 81, and 84 and 85 are enhancement type MEs to which the output of the oscillation circuit section 75 is supplied.
SFET, 86, 87 are resistors, 88 is MESFET8
This is an enhancement type MESFET that forms a current mirror circuit together with 0 and 81.

Here, in the fully differential amplifier 22,
Since the fluctuation of the power supply voltage appears as an in-phase output at the non-inverting output terminal 25 and the inverting output terminal 26 as described above, the voltage difference VA-VB between the non-inverting output terminal 25 and the inverting output terminal 26. Does not change.

Therefore, also with the voltage controlled oscillator of this embodiment, the ring oscillator 57 can be caused to perform a stable oscillation operation regardless of the fluctuation of the power supply voltage, and the oscillation output OUT with a stable frequency can be obtained. .

First Embodiment of PLL Circuit of the Present Invention FIG. 6 FIG. 6 is a circuit diagram showing a first embodiment of the PLL circuit of the present invention. In FIG. 6, 90 is a reference clock input terminal to which the reference clock Cref is input, 91 is a phase comparator, and 92
Is an EX-OR / NOR circuit that constitutes the phase comparator 90.

Further, 93 and 94 are charge pump circuits, and 95 to 98 are enhancement type MESFE.
T.

Further, 99 to 102 are resistors, 103 and 10
4 is a capacitor, 105 is the voltage controlled oscillator shown in FIG. 3 (first embodiment of the voltage controlled oscillator of the present invention), and the resistors 99 to 102 and the capacitors 103 and 104 form a loop filter together with the fully differential amplifier 22. It is what constitutes.

In the fully differential amplifier 22 also in the PLL circuit of this embodiment, the fluctuation of the power supply voltage appears as an in-phase output at the non-inverting output terminal 25 and the inverting output terminal 26. The voltage difference VA-VB between 25 and the inverting output terminal 26 does not change.

Therefore, according to the PLL circuit of this embodiment, the ring oscillator 5 is irrespective of the fluctuation of the power supply voltage.
Since it is possible to cause 7 to perform a stable oscillation operation, it is possible to secure a stable PLL operation and obtain a stable oscillation output OUT having the same frequency as the reference clock Cref.

Second Embodiment of PLL Circuit of the Present Invention FIG. 7 FIG. 7 is a circuit diagram showing a second embodiment of the PLL circuit of the present invention. This PLL circuit is a phase comparator 91 shown in FIG. Instead of the above, a phase frequency comparator 107 is provided, and the other components are configured similarly to the PLL circuit shown in FIG.

In the phase frequency comparator 107,
Reference numerals 108 to 116 are NOR circuits, 117 and 118 are inverters, and the NOR circuits 108 to 116 can be replaced with NAND circuits.

Also in the PLL circuit of this embodiment, in the fully differential amplifier 22, the fluctuation of the power supply voltage appears at the non-inverting output terminal 25 and the inverting output terminal 26 as an in-phase output. The voltage difference VA-VB between 25 and the inverting output terminal 26 does not change.

Therefore, the PLL circuit of this embodiment can also cause the ring oscillator 57 to perform a stable oscillation operation regardless of the fluctuation of the power supply voltage.
A stable PLL operation can be ensured, and a stable oscillation output OUT having the same frequency as the reference clock Cref can be obtained.

Third Embodiment of PLL Circuit of the Present Invention FIG. 8 and FIG. 9 FIG. 8 is a circuit diagram showing a third embodiment of the PLL circuit of the present invention. In FIG. 8, 120 is a reference clock Cref. Input reference clock input terminal, reference clock Cref 121
An inversion clock input terminal to which an inversion reference clock / Cref having an inversion relation is input, and 122 is a differential inverter forming a buffer.

Reference numeral 123 is a phase frequency comparator,
This phase frequency comparator is configured as shown in FIG. 9, and in the figure, 124 to 132 are NOR circuits 133, 1
Reference numeral 34 is an inverter.

Further, 135 and 136 are charge pump circuits, and 137 to 140 are enhancement type M.
ESFET.

Further, 141 to 144 are resistors, 145, and 1
Reference numeral 46 is a capacitor, 147 is the voltage controlled oscillator shown in FIG. 5 (the second embodiment of the voltage controlled oscillator of the present invention), and the resistors 141 to 144 and the capacitors 145 and 146 form a loop filter together with the fully differential amplifier 22. To do.

Further, 148 is a buffer circuit, 149 is an oscillation output OUT supplied through the buffer circuit 147,
It is a 1 / n frequency divider that divides the frequency of / OUT into 1 / n.

In the fully differential amplifier 22 also in the PLL circuit of this embodiment, the fluctuation of the power supply voltage appears as an in-phase output at the non-inverting output terminal 25 and the inverting output terminal 26. The voltage difference VA-VB between 22 and the inverting output terminal 26 does not change.

Therefore, according to the PLL circuit of this embodiment, the multivibrator 74 can perform a stable oscillation operation regardless of the fluctuation of the power supply voltage.
The stable PLL operation is secured and the reference clock Cref is set to n.
Stable oscillation output OUT with a frequency doubled, /
OUT can be obtained.

Example of use ... FIG. 10 FIG. 10 shows a third embodiment of the PLL circuit of the present invention in parallel /
It is a circuit diagram which shows the example used for the serial conversion circuit.

In FIG. 10, 151 is the P of the present invention shown in FIG.
A third embodiment of the LL circuit, reference numeral 152 is a third embodiment of the PLL circuit of the present invention through the buffer circuit 148 shown in FIG.
1 is a differential inverter that generates clocks CLK and / CLK by inverting oscillation outputs OUT and / OUT that are obtained by multiplying the reference clock Cref output from 1 by n times.

153 is an 8-bit parallel
The buffer circuit 1 to which the data D0 to D7 are input, and the buffer circuit 154 are synchronized with the clocks CLK and / CLK supplied from the differential inverter 152.
It is a parallel / serial converter that converts the parallel data D0 to D7 output from 53 into serial data.

In this example of use, an oscillation output O with a stable frequency is obtained from the third embodiment 151 of the PLL circuit of the present invention.
Since UT and / OUT can be obtained, clocks CLK and / CLK with stable frequencies can be obtained and supplied to the parallel / serial converter 154, so that serial data with stable frequencies can be obtained. You can

In the above embodiment, MESF is used.
Although the case has been described where the ET is used for the configuration, a MOS transistor or a bipolar transistor may be used instead.

[0056]

As described above, according to the voltage controlled oscillator of the present invention, the voltage output to one and the other output terminals of the fully differential amplifier to which the control voltage is supplied between the one and the other input terminals. By adopting a configuration in which an oscillator that operates as one and the other of the power supply voltages is provided, even if the power supply voltage changes, it is possible to supply to the oscillator two voltages with no fluctuation in the voltage difference as the power supply voltage. Therefore, it is possible to obtain an oscillation output with a stable frequency regardless of the fluctuation of the power supply voltage.

According to the voltage controlled oscillator of the present invention,
In this way, an oscillation output with a stable frequency can be obtained regardless of fluctuations in the power supply voltage, so that the integrated circuit equipped with the voltage controlled oscillator of the present invention can be made large-scale and the PLL circuit can be used as a general-purpose macro. The effect of being able to do so can also be obtained.

Further, according to the PLL circuit of the present invention, since the voltage controlled oscillator of the present invention which can obtain the oscillation output with stable frequency is used regardless of the fluctuation of the power supply voltage, the fluctuation of the power supply voltage is used. Regardless of this, stable PLL operation can be ensured.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of a voltage controlled oscillator according to the present invention.

FIG. 2 is a diagram illustrating the principle of the PLL circuit of the present invention.

FIG. 3 is a circuit diagram showing a first embodiment of the voltage controlled oscillator according to the present invention.

FIG. 4 is a circuit diagram showing a configuration example of a fully differential amplifier provided in the first embodiment of the voltage controlled oscillator of the present invention.

FIG. 5 is a circuit diagram showing a second embodiment of the voltage controlled oscillator according to the present invention.

FIG. 6 is a circuit diagram showing a first embodiment of a PLL circuit of the present invention.

FIG. 7 is a circuit diagram showing a second embodiment of the PLL circuit of the present invention.

FIG. 8 is a circuit diagram showing a third embodiment of the PLL circuit of the present invention.

FIG. 9 is a circuit diagram showing a circuit configuration of a phase frequency comparator provided in a third embodiment of the PLL circuit of the present invention.

FIG. 10 is a circuit diagram showing a usage example of a third embodiment of the PLL circuit of the present invention.

FIG. 11 is a circuit diagram showing an example of a conventional voltage controlled oscillator.

[Explanation of symbols]

 11 Fully differential amplifier 16 Oscillator 19 and 20 Impedance circuit

Claims (3)

[Claims] 1. A fully differential amplifier (1) in which a control voltage (VC) is supplied between one and the other input terminals (12, 13).
1) and the voltages (VA, V) output to one and the other output terminals (14, 15) of the fully differential amplifier (11).
A voltage-controlled oscillator, comprising: an oscillator (16) that operates with B) as one and the other power supply voltages. 2. The voltage controlled oscillator according to claim 1, wherein a feedback circuit is connected to the fully differential amplifier (11). 3. A fully differential amplifier (1) in which a control voltage (VC) is supplied between one and the other input terminals (12, 13).
1) and the voltages (VA, V) output to one and the other output terminals (14, 15) of the fully differential amplifier (11).
An impedance circuit (19, 2) that forms a loop filter together with an oscillator (16) that operates using B) as one and the other power supply voltages and the fully differential amplifier (11).
0) and a voltage controlled oscillator configured to include a PLL circuit.