JP3597961B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor device having both high speed and low power.
[0002]
[Prior art]
FIG. 2 shows a conventional technique described in Japanese Patent Application Laid-Open No. 8-274620. (Hereinafter, this conventional example is referred to as Conventional Example A)
The oscillating circuit OSC0 is configured to receive a control signal from a control circuit at a terminal B1 and change the oscillating frequency according to the value of the signal. The control circuit CNT0 is configured to receive the reference clock CLK0 from outside and the oscillation output of the oscillation circuit OSC0. Here, the closed circuit system including the variable frequency oscillation circuit OSC0 and the control circuit CNT0 to which the output S0 of the variable frequency oscillation circuit OSC0 is input is configured to be a stable system to which negative feedback is applied to each other. . With this closed circuit system, the oscillation frequency of the output S0 of the variable frequency oscillation circuit OSC0 becomes a frequency corresponding to the frequency of the reference clock CLK0. For example, the oscillation frequency of the output S0 and the frequency of the external clock are synchronized at the same frequency. Become.
[0003]
The oscillation circuit OSC0 includes an N-type MOSFET (NMOSFET) and a P-type MOSFET (PMOSFET) formed on a semiconductor substrate, and a control voltage from the control circuit CNT0 changes the substrate bias of the MOSFET. The threshold value of the MOSFET is changed by the change, and the oscillation frequency of the oscillation circuit OSC0 is changed.
[0004]
Further, the main circuit LOG0 is configured to receive a control signal of the control circuit CNT0 at the terminal B0. The control signal controls a substrate bias of a MOSFET constituting the main circuit LOG0 to control a threshold voltage of the MOSFET. It is composed.
[0005]
With such a configuration. The threshold voltage of the MOSFET in the main circuit LOG0 can be controlled by the reference clock CLK0, and the threshold voltage of the MOSFET constituting the main circuit can be controlled according to the frequency of the reference clock (adapted to the operating frequency). Thus, power consumption and operating speed can be made variable.
[0006]
[Problems to be solved by the invention]
(1) In the conventional example A, there is no limitation on the method of distributing the signal B0 to the MOSFETs in the main circuit. However, the method of distributing the substrate bias to the main circuit largely depends on the power consumption and the mounting density of the main circuit.
[0007]
(2) In the conventional example A, the main circuit LOG0 is controlled by the signal of B0 corresponding to the signal of the terminal B1. This correspondence greatly depends on the stability and the stabilization time of the substrate bias control circuit.
[0008]
The present invention is an invention that solves the above two problems.
[0009]
[Means for Solving the Problems]
(1) The main circuit LOG0 of Conventional Example A is divided into a plurality of substrate control blocks using a PMOS substrate bias switch and an NMOS substrate bias switch, and the substrate bias of each circuit block is independent of the substrate bias control circuit. Control.
[0010]
(2) In the embodiment of the conventional example A, the signal B0 input to the main circuit LOG0 is a signal corresponding to the signal B1 input to the variable frequency oscillation circuit OSC0. Specifically, in the embodiment of the present invention, the substrate bias corresponding to the signal B0 is generated from the substrate bias corresponding to the signal B1 by using a substrate bias buffer. The input of the substrate bias buffer has a high impedance and the output has a lower impedance.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.
[0012]
FIG. 1 is a diagram showing an embodiment of the first invention of the present invention.
[0013]
Reference numeral 100 denotes a substrate bias control circuit described in the conventional example A, which comprises a variable frequency oscillation circuit OSC0 and a control circuit CNT0. Reference numerals 310 and 311 denote substrate control blocks each including a circuit block 300 including a plurality of MOSFETs, a PMOS substrate bias switch circuit 200, and an NMOS substrate bias switch circuit 201. 120 is a power control circuit.
[0014]
The substrate bias control circuit 100 outputs a PMOS substrate bias 110 and an NMOS substrate bias 111 adapted to the operating frequency by the structure of the conventional example A. The PMOS substrate bias switch 200 is supplied to the circuit blocks 300 in the substrate control blocks 310 and 311 respectively. And through the NMOS substrate bias switch 201.
[0015]
The input PMOS substrate bias 112 and NMOS substrate bias 113 are connected to the back gate of the MOSFET in the circuit block 300. (The back gate here means a terminal to which the substrate bias of the MOSFET is applied. Therefore, it is obvious that there is a possibility that power is actually supplied to the N-type well or the P-type well.)
The substrate bias control circuit 100 is controlled by the standby signal 400 from the power control circuit 120. The substrate bias control circuit 100 is in the operating state when the standby signal 400 is “H”, and is stopped when the standby signal 400 is “L”.
[0016]
The difference between the operation state and the stop state is that the power consumption of the substrate bias control circuit 100 is smaller in the stop state than in the operation state, and other than that, there is no particular limitation. Of course, when the substrate bias control circuit 100 has only the operating state, the standby signal 400 may not be provided.
[0017]
The PMOS substrate bias switch 200 and the NMOS substrate bias switch 201 are controlled by standby signals 401 and 402 output from the power control circuit 120. When the standby signals 401 and 402 are “H”, the potentials of the substrate biases 110 and 111 are set. To the substrate biases 112 and 113 as they are. When the standby signals 401 and 402 are “L”, the potentials of the substrate biases 112 and 113 become substrate bias potentials deeper than the substrate bias value when the standby signal is “H”.
[0018]
For example, assuming that the power supply voltage is 1.0 V and the substrate biases 110 and 111 are 1.2 V and −0.2 V, respectively, when the standby signals 401 and 402 are “H”, the substrate biases 112 and 113 respectively have 1. 2 V and -0.2 V are applied, and when the standby signals 401 and 402 are "L", 3.3 V and -2.3 V are applied to the substrate biases 112 and 113, respectively.
[0019]
As shown in FIG. 1, the main circuit LOG0 of the conventional example A is divided into a plurality of substrate control blocks 310 and 311 by using a PMOS substrate bias switch 200 and an NMOS substrate bias switch 201. Can be controlled independently of the substrate bias control circuit 100.
[0020]
For example, the standby signal 401 is set to “H” while the circuit block 300 is operating. Since the potentials of the substrate biases 110 and 111 are transmitted as they are to the substrate biases 112 and 113, a substrate bias suitable for the operating frequency is applied to the substrate bias of the MOSFET in the circuit block 300.
[0021]
Further, while the circuit block 300 is stopped, the standby signal is set to “L”. Substrate biases are output to substrate biases 112 and 113 more deeply than during operation, respectively, so that the threshold voltage of the MOSFET in circuit block 300 increases, and subthreshold leakage current can be reduced.
[0022]
Further, the method is not particularly limited. However, if a clock is supplied to the circuit block 300 only during the operation of each circuit block 300, the power consumption of the stopped circuit block can be reduced.
[0023]
As described above, by dividing the conventional main circuit LOG0 into a plurality of circuit blocks and individually controlling the substrate bias, the sub-threshold leakage current of the stopped circuit block can be reduced, and the entire main circuit can be reduced. Effective power consumption can be reduced.
[0024]
Furthermore, since the substrate bias of the circuit block 300 can be controlled independently of the substrate bias control circuit 100 by using the PMOS substrate bias switch 200 and the NMOS substrate bias switch 201, the circuit block 300 operates from the stopped state. The time required for shifting from the state or the operation state to the stop state can be shortened. Although it depends on the substrate drive capability of the substrate bias switches 200 and 201, it becomes possible in a short time of about several hundred nanoseconds. Therefore, even if the standby signals 401 and 402 are frequently changed to change the operation state of the circuit block frequently, the performance of the system is not reduced.
[0025]
FIG. 3 shows an embodiment of the substrate bias control circuit 100 of FIG. Although there is an embodiment in the conventional example A, what is shown here is another embodiment having the same basic operation.
[0026]
OSC1 is a variable frequency oscillation circuit, which is a ring oscillator composed of an inverter array and a two-input NAND circuit. PFD, CP, and LPF are a phase frequency comparison circuit, a charge pump circuit, and a low-pass filter described in the conventional example A, respectively. RCLK is a reference clock input to the variable frequency oscillation circuit OSC1.
[0027]
CNV1 and CNV2 are voltage level converters. The high level 'H' is Vdd (positive power supply voltage potential, for example, 1.0 V), and the low level 'L' is Vss (negative power supply voltage potential, for example, 0.1 V). 0V) is converted into a digital signal having a high level “H” of Vdd and a low level “L” of Vssq (a second negative power supply voltage potential, for example, −2.3 V).
[0028]
MP1 to MP4 are PMOSFETs, MN1 to MN4 are NMOSFETs, and CM1 to CM3 are differential amplifiers. SBUF1 and SBUF2 are substrate bias buffers. When 400 is at "H", it receives the substrate biases Vbp0 and Vbn0 with high impedance, and outputs them with low impedance to 110 and 111 with a gain of 1.
[0029]
When 400 is “L”, Vddq (second positive power supply voltage potential, for example, 3.3 V) and Vssq are output to 110 and 111, respectively, and at the same time, the constant current in differential amplifiers CM1 and CM2 is output. The current of the source is turned off, and the power consumption of the substrate bias buffers SBUF1 and SBUF2 decreases.
[0030]
SBM is a substrate bias mirror circuit which receives a substrate bias Vbn0 as an input and outputs a substrate bias Vbp0 as shown in FIG. The detailed operation of this SBM will be described with reference to FIG.
[0031]
The reference clock RCLK and the output OCLK of the variable frequency oscillation circuit OSC1 are input to the phase frequency comparison circuit PFD, and the UP signal and the DN signal are output according to the phase or frequency difference. Each signal is input to the charge pump CP through the voltage level converters CNV1 and CNV2, and the substrate bias Vbn0 is generated through the low-pass filter LPF. The substrate bias Vbn0 is input to the above-described substrate bias mirror circuit SBM, and the substrate bias Vbp0 is generated. The generated substrate biases Vbp0 and Vbn0 are connected to the back gate of the MOSFET as the substrate biases of the PMOSFET and the NMOSFET of the MOSFET constituting the variable frequency oscillation circuit OSC1, respectively.
[0032]
With this phase locked loop system, the oscillation frequency of the variable frequency oscillation circuit OSC1 becomes the same as the frequency of the reference clock, and the substrate clocks Vbp0 and Vbn0 can be controlled by the reference clock.
[0033]
In the embodiment of the conventional example A shown in FIG. 2, the signal B0 input to the main circuit LOG0 is a signal corresponding to the signal B1 input to the variable frequency oscillation circuit OSC0. Specifically, in the embodiment of FIG. 3, the substrate biases 110 and 111 corresponding to the signal B0 are generated from the substrate biases Vbp0 and Vbn0 corresponding to the signal B1 by using the substrate bias buffers SBUF1 and SBUF2.
[0034]
In this way, even if a large load is connected to substrate biases 110 and 111, substrate biases Vbp0 and Vbn0 are not affected. Therefore, the design of the phase locked loop system is facilitated, and the time during which the phase locked loop system is stabilized (lock time) can be reduced.
[0035]
The structure of the substrate bias buffers SBUF1 and SBUF2 is not particularly limited to that shown in FIG. 3, but may be any as long as it can receive the substrate biases Vbp0 and Vbn0 with high impedance and output them to 110 and 111 with low impedance.
[0036]
FIG. 5 shows still another embodiment of the embodiment of the substrate bias control circuit 100 of FIG. 1 shown in FIG.
[0037]
OSC2 is a variable frequency oscillating circuit, which is composed of a ring oscillator composed of an inverter array and a two-input NAND circuit. PFD1 and PFD2 are phase frequency comparison circuits, CP1 and CP2 are charge pump circuits, and LPF1 and LPF2 are low-pass filters. RCLK is a reference clock whose duty ratio (the ratio of the 'H' period in one cycle of the clock) is 50%. SBUF1 and SBUF2 are the substrate bias buffers shown in FIG.
[0038]
The falling of the oscillation output OCLK1 of the variable frequency oscillation circuit OSC2 and the rising edge of the reference clock RCLK by a phase locked loop system composed of the variable frequency oscillation circuit OSC2, the phase frequency comparison circuit PFD1, the charge pump circuit CP1, and the low-pass filter LPF1. The substrate bias Vbp1 changes so that the falling timing is the same.
[0039]
Similarly, the rising edge of the oscillation output OCLK1 of the frequency-variable oscillation circuit OSC2 and the reference clock are generated by a phase-locked loop system including the frequency-variable oscillation circuit OSC2, the phase frequency comparison circuit PFD2, the charge pump circuit CP2, and the low-pass filter LPF2. The substrate bias Vbn1 changes so that the rise of RCLK becomes the same timing.
[0040]
After all, the substrate biases Vbn1 and Vbn1 are changed by the two phase-locked loop systems so that the rise and fall of the oscillation output OCLK1 of the variable frequency oscillation circuit OSC2 coincide with the rise and fall of the reference clock RCLK. become. In other words, the substrate biases Vbn1 and Vbn1 are changed so that the phase, frequency, and duty ratio of the oscillation output OCLK1 of the variable frequency oscillation circuit OSC2 become equal to the phase, frequency, and duty ratio (50%) of the reference lock RCLK. Will do.
[0041]
The substrate biases Vbp1 and Vbn1 are not to be determined independently of each other. For example, the drain currents (driving capabilities) of the PMOSFET and the NMOSFET having the substrate bias applied to the back gate are set to an appropriate ratio such as 2: 1. You need to keep it.
[0042]
The "H" period of the oscillation output OCLK1 of the variable frequency oscillation circuit OSC2 mainly depends on the driving capability of the PMOSFET in the variable frequency oscillation circuit OSC2 (the threshold value of the PMOSFET, that is, the substrate bias Vbn1 applied to the PMOSFET. ), And the 'L' period is mainly determined by the driving capability of the NMOSFET in the variable frequency oscillation circuit OSC2 (which depends on the threshold voltage of the NMOSFET, that is, the substrate bias Vbp1 applied to the NMOSFET). Therefore, the fact that the duty ratio of the oscillation output OCLK1 of the variable frequency oscillation circuit OSC2 is 50% means that the driving capability of the PMOSFET and the NMOSFET is equal to the w (gate width) ratio of the PMOSFET and the NMOSFET in the variable frequency oscillation circuit OSC2. This means that the balance between the substrate biases Vbp1 and Vbn1 is maintained.
[0043]
As described above, in the embodiment of FIG. 5, the values of the substrate biases Vbp1 and Vbn1 are determined by the frequency of the reference clock RCLK, and the balance between the substrate biases Vbp1 and Vbn1 is determined by the w ratio of the PMOSFET and the NMOSFET in the variable frequency oscillation circuit OSC2. Will be determined.
[0044]
In FIG. 5, as in FIG. 3, the substrate biases 110 and 111 are generated from the substrate biases Vbp1 and Vbn1 using the substrate bias buffers SBUF1 and SBUF2.
[0045]
Therefore, as in the case of FIG. 3, even if a large load is connected to substrate biases 110 and 111, substrate biases Vbp1 and Vbn1 are not affected. Therefore, the design of the phase locked loop system is facilitated, and the time during which the phase locked loop system is stabilized (lock time) can be reduced.
[0046]
Of course, as in the case of FIG. 3, the structure of the substrate bias buffers SBUF1 and SBUF2 is not particularly limited to that shown in FIG. It is sufficient that the substrate biases Vbp1 and Vbn1 can be received at high impedance and output to 110 and 111 at low impedance.
[0047]
6A and 6B show examples of the substrate bias switches 200 and 201 of FIG. 1, respectively. It can be realized by the same one as the substrate bias buffers SBUF1 and SBUF2 shown in FIG. 3 and FIG.
[0048]
When “401” is “H”, the substrate biases 110 and 111 are received at high impedance, and are output at low gain to 112 and 113 with a gain of 1.
[0049]
When 400 is “L”, Vddq and Vssq are output to 112 and 113, respectively, and at the same time, the current of the low current source supplied to the differential amplifiers CM1 and CM2 is turned off. Power consumption is reduced.
[0050]
FIG. 7 shows another embodiment of the present invention.
[0051]
In FIG. 1, the PMOS substrate bias 110 and the NMOS substrate bias 111 adapted to the operating frequency are output from the substrate bias control circuit 100, but in FIG. 3, only the bias 120 is output. When the power control signal 401 or 402 is “H”, the PMOS substrate bias 112 and the NMOS substrate bias 113 are output from the bias 120 by the PMOS substrate bias switch 204 and the NMOS substrate bias switch 205. The PMOS substrate bias 112 and the NMOS substrate bias 113 are input to the back gate of the MOSFET in the circuit block 300.
[0052]
The bias 120 may be one of the PMOS substrate bias 110 and the NMOS substrate bias 111 of FIG. For example, if the bias 120 is the same signal as the PMOS substrate bias 110 of FIG. 1, the substrate bias switch 204 may be the same as the substrate bias switch 200 of FIG. Further, when the power control signal 401 or 402 is “H”, the substrate bias switch 205 can generate an equivalent to the NMOS substrate bias 111 from the bias 120 (in this case, the same as the PMOS substrate bias 110) and output the same to the substrate bias 113. Anything should do.
[0053]
Exactly the same effect as in the case of FIG. 1 can be obtained. Further, in the case of FIG. 1, two wirings of the substrate biases 110 and 111 are required, whereas in the embodiment of FIG. 7, the substrate bias is supplied to the substrate control blocks 310 and 311 by one wiring of the bias 120. Therefore, there is an advantage that the wiring efficiency is improved.
[0054]
FIG. 8 shows an embodiment of the substrate bias control circuit 100 of FIG.
[0055]
This can be realized by removing the substrate bias buffer SBUF1 from FIG. That is, the bias 120 becomes the same signal as the NMOS substrate bias 111 of FIG. The circuit operation of FIG. 8 is the same as that of FIG.
[0056]
FIG. 9 shows an embodiment of the substrate bias 205 of FIG. 7 when the circuit of FIG. 8 is used for the substrate bias control circuit 100 of FIG. In this case, the circuit shown in FIG. 6B can be used as the substrate bias switch 204 as it is.
[0057]
The circuit of FIG. 9 is the same as the substrate bias mirror circuit in the embodiment of FIGS.
With the substrate bias 120 as an input, a substrate bias 113 is output. Here, this operation will be described in detail.
[0058]
Although not particularly limited, it is assumed that 401 is “H” and Vddq = 3.3 V, Vdd = 1.0 V, Vss = 0.0 V, and Vssq = −2.3 V for the sake of simplicity.
[0059]
MP3 to MP5 are PMOSFETs, and MN3 to MN5 are NMOSFETs. The gate lengths of MP3 and MN3 are equal and the w (gate width) ratio is m: 1. Similarly, the gate lengths of MP5 and MN5 are equal and the w (gate width) ratio is set to m: 1. CM3 is a differential amplifier that amplifies the potential difference between Vh1 and Vh2 and inputs the output Vh3 to the gate of MP5.
[0060]
A voltage corresponding to the driving capability of MP3 and MN3 is output to Vh1 by the voltage divider composed of MP3 and MN3. That is, when Vh1 is 0.5 V (= (Vdd + Vss / 2) + Vss), it means that the driving capabilities of MP3 and MN3 are equal. Now, it is assumed that the driving capabilities of MP3 and MN3 are equal, and that Vh1 is 0.5V.
[0061]
Since the output Vh3 of the differential amplifier CM3 controls the substrate bias of MP4, thereby controlling the potential of Vh2, the differential amplifier CM3 is subjected to negative feedback. Therefore, in the steady state, the potential of Vh2 becomes the same potential as Vh1, that is, 0.5V.
[0062]
Since a voltage corresponding to the driving capability of MP3 and MN3 is output to Vh2 by the voltage divider composed of MP4 and MN4, the fact that the potential of Vh2 is 0.5 V means that the driving capabilities of MP4 and MN4 are equal. Means that.
[0063]
Therefore, by setting the w ratio of MP3 to MN3 and the w ratio of MN4 of MP4 to the same value, input is performed while maintaining the driving capability ratio of MN4 of MP4 when the substrate bias is set to the same potential as the source potential. In response to the substrate bias 120, the potential of the substrate bias 113 is output.
[0064]
As described above, the substrate biases 120 and 113 are not to be determined independently of each other. For example, the drain current (driving capability) per unit gate width of the PMOSFET and the NMOSFET whose substrate bias is applied to the back gate Must be kept at an appropriate ratio, such as 2: 1. This can be realized by the circuit of FIG.
[0065]
In general, the dependence of the threshold voltage on the substrate bias differs between the PMOSFET and the NMOSFET, and also the dependence of the drain current per unit gate width on the change in the power supply voltage. For example, as the power supply voltage decreases, the driving capability of the PMOSFET decreases more remarkably than that of the NMOSFET. By using the substrate bias mirror circuit SBM of FIG. 9 of the present invention, the above difference in dependency can be compensated.
[0066]
FIG. 9 shows that when 401 is “L”, Vddq is output to the substrate bias 113, and the current supplied to the voltage divider composed of MP3 and MN3 and MP4 and MN4 and the current supplied to the differential amplifier CM3 are turned off and consumed. The power is reduced.
[0067]
FIG. 10 shows an embodiment of the power supply wiring for the substrate biases 110 and 111 shown in FIG. The power control circuit and the standby signal output from it are omitted for simplicity.
[0068]
Reference numeral 500 denotes a microcomputer, for example, and the internal power supply of the microcomputer is supplied by Vdd and Vss. Reference numeral 501 denotes an I / O circuit for an external interface, to which a voltage Vddq higher than Vdd is supplied. Although the power supply voltage potential is not particularly limited, for example, Vddq = 3.3 V, Vdd = 1.0 V, Vss = 0.0 V, and Vssq = −2.3 V. With this voltage setting, Vddq−Vss and Vdd−Vssq have the same potential difference, and there is an advantage that device design becomes easy.
[0069]
The circuit in the microprocessor is divided into four board control blocks MA1 to MA4. Reference numerals 200 and 201 are the same as those of the substrate bias switch of FIG. The supply source of the reference clock RCLK is not limited, but may be generated from a clock signal in the microprocessor 500.
[0070]
Here, the substrate biases 110 and 111 are supplied using the method of the invention of Japanese Patent Application No. 8-314506. That is, the substrate bias of each transistor is supplied by the surface high concentration diffusion layer DL for obtaining the substrate potential through the third metal layer M3 to the second metal layer M2.
[0071]
Since the first layer of metal is not used, each transistor can be mounted at a high density.
[0072]
The method of using the metal of this embodiment is not particularly limited.
[0073]
FIG. 11 shows an example of a sectional view of a substrate structure (well structure) for realizing FIG. On the substrate surface, n-wells and p-wells are alternately arranged, and a circuit can be mounted by forming a transistor on the surface. The m well is a well having n polarity.
[0074]
The n-well in substrate control block MA1 and the n-well in substrate control block MA2 are electrically separated by a p-substrate, and the p-well in substrate control block MA1 and the p-well in substrate control block MA2 have n polarity. Are electrically separated by a corresponding m-well.
[0075]
Therefore, independent substrate biases can be applied to the PMOSFET in the substrate control block MA1 and the PMOSFET in the substrate control block MA2, and to the NMOSFET in the substrate control block MA1 and the NMOSFET in the substrate control block MA2. Can be realized.
[0076]
In FIG. 3, FIG. 5, or FIG. 8, when 400 is “H”, the above operation is performed, but when “L”, the oscillation of the frequency variable oscillator circuit OSC1 or OSC2 is stopped, The mirror circuit SBM and the substrate bias buffers SBUF1, SBUF2 enter the low power state. Therefore, the power consumption of the entire circuit is reduced.
[0077]
In the microprocessor using the present invention, if the signal 400 is connected to the standby signal of the microprocessor, the power consumption of the microprocessor at the time of standby can be reduced.
[0078]
Alternatively, 400 may be set to “L” during the IDDQ test of the microprocessor. Since the leakage current flowing through the circuit of FIG. 3, FIG. 5 or FIG. 8 is reduced and a large substrate bias value is output to the substrate biases 110 and 111, the MOSFET whose threshold value is controlled by the substrate biases 110 and 111 Can be reduced.
[0079]
Further, when 400 is "L", the outputs UP and DN of the phase frequency comparators PFD, PFD1, and PFD2 may be fixed to "H" and "L", respectively. The discharge of the capacitance C1 in the low-pass filters LPF, LPF1, and LPF2 when 400 is set to “L” is suppressed. Since the potential of the capacitance C1 is maintained even when switching is frequently performed at 400, the power consumption for charging and discharging the capacitance C1 can be reduced.
[0080]
In the above embodiments, the structure of the transistor and its substrate structure are not particularly limited. A MOS transistor having an SOI structure as described in IAD, Technical Digest, pages 35 to 38, 1992 (1992 IEDM Technical Digest, pp. 35-38) may be used. In short, any transistor having a structure in which the threshold value can be controlled may be used.
[0081]
【The invention's effect】
(1) The main circuit LOG0 of the conventional example A is divided into a plurality of substrate control blocks using a PMOS substrate bias switch and an NMOS substrate bias switch, so that the substrate bias of each circuit block is defined as a substrate bias control circuit. Can be controlled independently.
[0082]
By controlling the substrate bias individually for each circuit block, the sub-threshold leakage current of that circuit block can be reduced by controlling the substrate bias of the circuit block that is stopped, and the effective main circuit Power consumption can be reduced.
[0083]
Furthermore, since the substrate bias of the circuit block can be controlled independently of the substrate bias control circuit by using the PMOS substrate bias switch and the NMOS substrate bias switch, the circuit block is switched from the stop state to the operation state or from the operation state. The time required for shifting to the stop state can be shortened. Therefore, even if the standby signals 401 and 402 are frequently changed to change the operation state of the circuit block frequently, the performance of the system is not reduced.
[0084]
(2) In the embodiment of the conventional example A, the signal B0 input to the main circuit LOG0 is a signal corresponding to the signal B1 input to the variable frequency oscillation circuit OSC0. Specifically, in the embodiment of the present invention, the substrate bias corresponding to the signal B0 is generated from the substrate bias corresponding to the signal B1 by using a substrate bias buffer. In this way, even if a large load is connected to the substrate bias corresponding to the signal B0, the substrate bias corresponding to the signal B1 is not affected. Therefore, the design of the phase locked loop system that generates the substrate bias corresponding to the signal B1 is facilitated, and the time during which the phase locked loop system is stabilized (lock time) can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram of the simplest embodiment of the present invention.
FIG. 2 is a diagram showing a conventional example.
FIG. 3 is a diagram of an embodiment of the substrate bias control circuit of FIG. 1;
FIG. 4 is a diagram illustrating an operation of the substrate bias mirror circuit of FIG. 1;
FIG. 5 is a diagram of another embodiment of the substrate bias control circuit of FIG. 1;
6A is a diagram of an embodiment of a PMOS substrate bias switch, and FIG. 6B is a diagram of an embodiment of an NMOS substrate bias switch.
FIG. 7 is a diagram of another embodiment of the present invention.
FIG. 8 is a diagram of an embodiment of the substrate bias control circuit of FIG. 7;
FIG. 9 is a diagram of an embodiment of the PMOS substrate bias switch of FIG. 7;
FIG. 10 is a diagram of an embodiment showing a substrate bias distribution method when the present invention is applied to a microprocessor.
FIG. 11 is a diagram showing an example of a substrate structure for realizing the present invention.
[Explanation of symbols]
100: substrate bias control circuit,
110, 112, Vbp0, Vbp1... PMOS substrate bias,
111, 113, Vbn0, Vbn1 ... NMOS substrate bias,
120 ... power control circuit,
310, 311 ... board control block,
200: PMOS substrate bias switch,
201 ... NMOS substrate bias switch,
300 circuit block,
LOG0: Main circuit,
OSC0, OSC1, OSC2 ... variable frequency oscillation circuit,
CNT0 ... control circuit,
CLK0, RCLK: Reference clock,
400, 401, 402 ... standby signal,
MP1, MP2, MP3, MP4, MP5 ... P-type MOSFET,
MN1, MN2, MN3, MN4, MN5 ... N-type MOSFET,
CM1, CM2, CM3 ... operating amplifier,
SBM: substrate bias mirror circuit,
Vddq: second positive power supply potential,
Vdd: first positive power supply potential,
Vss: first negative power supply potential,
Vssq: second negative power supply potential,
CNV1, CNV2 ... voltage level converter,
CP, CP1, CP2 ... charge pump circuit,
LPF, LPF1, LPF2 ... low-pass filter,
PFD, PFD1, PFD2 ... Phase frequency comparison circuit,
R1, R2 ... resistance,
C1 ... capacitance,
SBUF1... PMOS substrate bias buffer,
SBUF2 ... NMOS substrate bias buffer,
204, 205 ... substrate bias switch,
MA1, MA2, MA3, MA4 ... board control block,
M3: Third layer metal,
M2: Second layer metal,
500 ... microprocessor,
501 I / O circuit.

Claims (6)

A plurality of circuit blocks including an MIS transistor formed on a semiconductor substrate;
A plurality of bias switch circuits provided corresponding to each of the plurality of circuit blocks;
An oscillation output circuit including an MIS transistor formed on the semiconductor substrate, configured to be able to vary the frequency of the oscillation output,
A buffer circuit;
A control circuit;
A power control circuit;
The control circuit is supplied with a clock signal having a predetermined frequency and an oscillation output of the oscillation output circuit,
The control circuit generates a first control signal by comparing the frequency of the oscillation output with the frequency of the clock signal,
The oscillation output circuit is controlled by the first control signal so that the frequency of the oscillation output corresponds to the frequency of the clock signal,
The control of the frequency of the oscillation output is performed by controlling the threshold voltage of the MIS transistor configuring the oscillation output circuit, by the first control signal,
The buffer circuit receives the first control signal and outputs a second control signal corresponding to the first control signal.
The second control signal is input to the plurality of bias switch circuits, and outputs a plurality of third control signals,
Each of the plurality of third control signals is input to a corresponding circuit block,
The third control signal controls a threshold voltage of an MIS transistor configuring the circuit block,
By the first power control signal from the power control circuit, the buffer circuit outputs the value of the second control signal as a value unrelated to the value of the first control signal,
By the second control signal output as a value unrelated to the value of the first control signal, power consumption of the plurality of circuit blocks is controlled to be small,
By the second power control signal from the power control circuit, the bias switch circuit outputs the value of the third control signal as a value unrelated to the value of the second control signal,
A semiconductor integrated circuit wherein power consumption of a circuit block corresponding to the bias switch circuit is controlled to be small by the third control signal output as a value unrelated to the value of the second control signal. apparatus. The semiconductor integrated circuit device according to claim 1,
The first control signal is input to the buffer circuit at a first impedance,
The semiconductor integrated circuit device, wherein the buffer circuit outputs the second control signal at a second impedance lower than the first impedance. The semiconductor integrated circuit device according to claim 1 or 2,
The second control signal is input to the bias switch circuit with a third impedance,
The semiconductor integrated circuit device, wherein the bias switch circuit outputs the third control signal at a fourth impedance lower than the third impedance. 4. The semiconductor integrated circuit device according to claim 1, wherein:
The first control signal controls the substrate bias of the MIS transistor constituting the oscillation output circuit,
A semiconductor integrated circuit device, wherein the third control signal controls a substrate bias of an MIS transistor forming a corresponding circuit block. The semiconductor integrated circuit device according to claim 1, wherein
The buffer circuit receives the first control signal, and outputs the second control signal with a gain of 1,
The semiconductor integrated circuit device, wherein the bias switch circuit receives the second control signal and outputs the third control signal with a gain of 1. 6. The semiconductor integrated circuit device according to claim 1, wherein:
When the third control signal output as a value unrelated to the value of the second control signal is applied, the threshold voltage of the MIS transistor configuring the circuit block is equal to the second control signal. A semiconductor integrated circuit device, wherein the threshold voltage of the MIS transistor forming the circuit block when the third control signal corresponding to the above is applied is set higher than the threshold voltage.

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