JP3767697B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having both high speed and low power.

The prior art described in Japanese Patent Laid-Open No. 8-274620 is shown in FIG. (Hereinafter, this conventional example will be referred to as Conventional Example A)
The oscillation circuit OSC0 is configured such that the terminal B1 receives a control signal from the control circuit and the oscillation frequency changes depending on the value of the signal. The control circuit CNT0 is configured to receive the reference clock CLK0 from the outside and the oscillation output of the oscillation circuit OSC0. Here, the closed circuit system including the variable frequency oscillation circuit OSC0 and the control circuit CNT0 that receives the output S0 of the variable frequency oscillation circuit OSC0 is configured to be a stable system to which negative feedback is applied. . By this closed circuit system, the oscillation frequency of the output S0 of the frequency variable oscillation circuit OSC0 becomes a frequency corresponding to the frequency of the reference clock CLK0.For example, the oscillation frequency of the output S0 and the frequency of the external clock are synchronized at the same frequency. Become.

  The oscillation circuit OSC0 is composed of an N-type MOSFET (NMOSFET) and a P-type MOSFET (PMOSFET) formed on a semiconductor substrate, and the control voltage from the control circuit CNT0 changes the substrate bias of the MOSFET. Due to the change, the threshold value of the MOSFET changes, and the oscillation frequency of the oscillation circuit OSC0 changes.

  Further, the main circuit LOG0 is configured to receive the control signal of the control circuit CNT0 at the terminal B0, and by this control signal, the substrate bias of the MOSFET constituting the main circuit LOG0 is controlled, and the threshold voltage of the MOSFET is controlled. It is configured.

  With such a configuration. The threshold voltage of the MOSFET in the main circuit LOG0 can be controlled by the reference clock CLK0, and the threshold voltage of the MOSFETs constituting the main circuit is adjusted according to the frequency of the reference clock (adapted to the operating frequency). As a result, power consumption and operation speed can be made variable.

JP-A-8-274620

  (1) In the conventional example A, there is no limitation on the method of distributing the signal B0 to the MOSFET in the main circuit, but the method of distributing the substrate bias to the main circuit is largely related to the power consumption and mounting density of the main circuit.

  (2) In the conventional example A, the main circuit LOG0 is controlled by the signal B0 corresponding to the signal at the terminal B1. This correspondence is greatly related to the stability and stabilization time of the substrate bias control circuit.

  The present invention solves the above two problems.

  (1) The main circuit LOG0 of Conventional Example A is divided into a plurality of substrate control blocks using a PMOS substrate bias switch and an NMOS substrate bias switch, and the substrate bias of each circuit block is independent of the substrate bias control circuit. Control.

  (2) In the embodiment of Conventional Example A, the signal B0 input to the main circuit LOG0 is a signal corresponding to the signal B1 input to the variable frequency oscillation circuit OSC0. Specifically, in the embodiment of the present invention, the substrate bias corresponding to the signal B0 is generated from the substrate bias corresponding to the signal B1 using a substrate bias buffer. The substrate bias buffer input is high impedance and the output is lower impedance.

  (1) By dividing the main circuit LOG0 of Conventional Example A into a plurality of substrate control blocks using a PMOS substrate bias switch and an NMOS substrate bias switch, the substrate bias of each circuit block is defined as a substrate bias control circuit. It can be controlled independently.

  By controlling the substrate bias for each circuit block individually, by controlling the substrate bias of the stopped circuit block, the sub-threshold leakage current of that circuit block can be reduced, and the entire main circuit can be effectively Power consumption can be reduced.

  Furthermore, since the substrate bias of the circuit block can be controlled independently of the substrate bias control circuit using the PMOS substrate bias switch and the NMOS substrate bias switch, the circuit block can be moved from the stopped state to the operating state or the operating state. The time required for shifting to the stop state can be increased. Therefore, even if the standby signals 401 and 402 are changed frequently to change the operation state of the circuit block frequently, the system performance does not deteriorate.

  (2) In the embodiment of Conventional Example A, the signal B0 input to the main circuit LOG0 is a signal corresponding to the signal B1 input to the variable frequency oscillation circuit OSC0. Specifically, in the embodiment of the present invention, the substrate bias corresponding to the signal B0 is generated from the substrate bias corresponding to the signal B1 using a substrate bias buffer. By doing so, even if a large load is connected to the substrate bias corresponding to the signal B0, the substrate bias corresponding to the signal B1 is not affected. Therefore, the design of the phase-locked loop system that generates the substrate bias corresponding to the signal B1 is facilitated, and the time during which the phase-locked loop system is stabilized (lock time) can be shortened.

  Hereinafter, specific embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram showing an embodiment of the first invention of the present invention.

  Reference numeral 100 denotes a substrate bias control circuit described in the conventional example A, which includes a variable frequency oscillation circuit OSC0 and a control circuit CNT0. Reference numerals 310 and 311 denote substrate control blocks, which include a circuit block 300 made up of a plurality of MOSFETs, a PMOS substrate bias switch circuit 200, and an NMOS substrate bias switch circuit 201. 120 is a power control circuit.

  With the structure of the conventional example A, the PMOS substrate bias 110 and the NMOS substrate bias 111 adapted to the operating frequency are output from the substrate bias control circuit 100, and the PMOS substrate bias switch 200 is supplied to the circuit block 300 in each of the substrate control blocks 310 and 311. And is input through the NMOS substrate bias switch 201.

  The input PMOS substrate bias 112 and NMOS substrate bias 113 are connected to the back gate of the MOSFET in the circuit block 300. (The back gate here means the terminal to which the substrate bias of the MOSFET is applied. Therefore, it is obvious that there is a possibility that power is actually supplied to the N-type well or P-type well.)

  The substrate bias control circuit 100 is controlled by a standby signal 400 from the power control circuit 120. The substrate bias control circuit 100 is in an operating state when the standby signal 400 is “H”, and is in a stopped state when the standby signal 400 is “L”.

  The difference between the operation state and the stop state is that the power consumption of the substrate bias control circuit 100 is smaller in the stop state than in the operation state, and otherwise there is no particular limitation. Of course, when the substrate bias control circuit 100 has only an operating state, the standby signal 400 may be omitted.

  The PMOS substrate bias switch 200 and the NMOS substrate bias switch 201 are controlled by standby signals 401 and 402 output from the power control circuit 120. When the standby signals 401 and 402 are 'H', the potentials of the substrate bias 110 and 111 are set. Is sent to the substrate biases 112 and 113 as they are. When the standby signals 401 and 402 are “L”, the potentials of the substrate biases 112 and 113 are substrate bias potentials deeper than the substrate bias value when the standby signal is “H”.

  For example, assuming that the power supply voltage is 1.0 V and the substrate biases 110 and 111 are 1.2 V and −0.2 V, respectively, when the standby signals 401 and 402 are “H”, the substrate biases 112 and 11 are 1.2 V and −0.2 V, respectively. When V is applied and the standby signals 401 and 402 are “L”, the substrate biases 112 and 113 are applied with 3.3V and −2.3V, respectively.

  As shown in FIG. 1, the main circuit LOG0 of the conventional example A is divided into a plurality of substrate control blocks 310 and 311 using the PMOS substrate bias switch 200 and the NMOS substrate bias switch 201, whereby the substrate bias of each circuit block 300 is obtained. Can be controlled independently of the substrate bias control circuit 100.

  For example, the standby signal 401 is set to “H” while the circuit block 300 is operating. Since the potentials of the substrate biases 110 and 111 are directly transmitted to the substrate biases 112 and 113, a substrate bias suitable for the operating frequency is applied to the substrate bias of the MOSFET in the circuit block 300.

  Further, the standby signal is set to “L” while the circuit block 300 is stopped. Substrate bias is output to substrate biases 112 and 113 deeper than in operation, respectively, and the threshold voltage of the MOSFET in circuit block 300 is increased, so that the subthreshold leakage current can be reduced.

  Further, the method is not particularly limited. However, if the clock is supplied to the circuit block 300 only when each circuit block 300 is operating, the power consumption of the stopped circuit block can be reduced.

  As described above, the main circuit LOG0 of the conventional example is divided into a plurality of circuit blocks, and the substrate bias is individually controlled, so that the subthreshold leakage current of the stopped circuit block can be reduced, and the entire main circuit The effective power consumption can be reduced.

  Furthermore, since the substrate bias of the circuit block 300 can be controlled independently of the substrate bias control circuit 100 using the PMOS substrate bias switch 200 and the NMOS substrate bias switch 201, the circuit block 300 is operated from a stopped state. The time required to shift from the state or the operation state to the stop state can be increased. Although it depends on the substrate drive capability of the substrate bias switches 200 and 201, it is possible in a short time of about several hundred nanoseconds. Therefore, even if the standby signals 401 and 402 are changed frequently to change the operation state of the circuit block frequently, the system performance does not deteriorate.

  FIG. 3 shows an embodiment of the substrate bias control circuit 100 of FIG. The conventional example A also has an embodiment, but the example shown here is the other embodiment although the basic operation is the same.

  OSC1 is a variable frequency oscillation circuit, which is a ring oscillator composed of an inverter array and a 2-input NAND circuit. PFD, CP, and LPF are a phase frequency comparison circuit, a charge pump circuit, and a low-pass filter, which are also described in Conventional Example A. RCLK is a reference clock input to the frequency variable oscillation circuit OSC1.

  CNV1, CNV2 are voltage level converters, high level 'H' is Vdd (positive power supply voltage potential, for example 1.0V), low level 'L' is Vss (negative power supply voltage potential, for example 0.0V) The digital signal is converted into a digital signal having a high level 'H' of Vdd and a low level 'L' of Vssq (second negative power supply voltage potential, for example, -2.3V).

  MP1 to MP4 are PMOSFETs, MN1 to MN4 are NMOSFETs, and CM1 to CM3 are differential amplifiers. SBUF1 and SBUF2 are substrate bias buffers. When 400 is 'H', substrate biases Vbp0 and Vbn0 are received with high impedance, and are output to 110 and 111 with gain 1 with low impedance.

  When 400 is 'L', Vddq (second positive power supply voltage potential, for example, 3.3V) and Vssq are output to 110 and 111 respectively, and at the same time, constant current sources in the differential amplifiers CM1 and CM2 Current is turned off, and the power consumption of the substrate bias buffers SBUF1 and SBUF2 is reduced.

  SBM is a substrate bias mirror circuit, which receives the substrate bias Vbn0 and outputs the substrate bias Vbp0 as shown in FIG. The detailed operation of this SBM is described in FIG.

  The reference clock RCLK and the output OCLK of the frequency variable oscillation circuit OSC1 are input to the phase frequency comparison circuit PFD, and an UP signal and a DN signal are output according to the phase or frequency difference. Each signal is input to the charge pump CP through the voltage level converters CNV1 and CNV2, and the substrate bias Vbn0 is generated through the low-pass filter LPF. The substrate bias Vbn0 is input to the aforementioned substrate bias mirror circuit SBM, and the substrate bias Vbp0 is generated. The generated substrate biases Vbp0 and Vbn0 are connected to the back gate of the MOSFET as the substrate bias of the PMOSFET and NMOSFET of the MOSFET constituting the variable frequency oscillation circuit OSC1, respectively.

  By this phase-locked loop system, the oscillation frequency of the variable frequency oscillation circuit OSC1 becomes the same as the frequency of the reference clock, and the substrate biases Vbp0 and Vbn0 can be controlled by the reference clock.

  In the embodiment of Conventional Example A shown in FIG. 2, the signal B0 input to the main circuit LOG0 is a signal corresponding to the signal B1 input to the variable frequency oscillation circuit OSC0. Specifically, in the embodiment of FIG. 3, the substrate biases 110 and 111 corresponding to the signal B0 are generated from the substrate biases Vbp0 and Vbn0 corresponding to the signal B1 using the substrate bias buffers SBUF1 and SBUF2.

  By doing so, even if a large load is connected to the substrate biases 110 and 111, the substrate biases Vbp0 and Vbn0 are not affected. Therefore, the design of the phase-locked loop system is facilitated, and the time (lock time) during which the phase-locked loop system is stabilized can be shortened.

  The structure of the substrate bias buffers SBUF1 and SBUF2 is not particularly limited to that shown in FIG. 3, but any substrate that can receive the substrate biases Vbp0 and Vbn0 with high impedance and output them to 110 and 111 with low impedance may be used.

  FIG. 5 shows still another embodiment of the substrate bias control circuit 100 of FIG. 1 shown in FIG.

  OSC2 is a variable frequency oscillation circuit, and is composed of a ring oscillator composed of an inverter array and a 2-input NAND circuit. PFD1 and PFD2 are phase frequency comparison circuits, CP1 and CP2 are charge pump circuits, and LPF1 and LPF2 are low-pass filters. RCLK is a reference clock having a duty ratio (the ratio of the “H” period in one cycle of the clock) of 50%. SBUF1 and SBUF2 are the substrate bias buffers shown in FIG.

  The fall of the oscillation output OCLK1 of the frequency variable oscillation circuit OSC2 and the rise of the reference clock RCLK are achieved by a phase-locked loop system composed of the frequency variable oscillation circuit OSC2, the phase frequency comparison circuit PFD1, the charge pump circuit CP1, and the low-pass filter LPF1. The substrate bias Vbp1 is changed so that the drops are at the same timing.

  Similarly, the rising edge of the oscillation output OCLK1 of the frequency variable oscillation circuit OSC2 and the reference clock are generated by the phase-locked loop system including the frequency variable oscillation circuit OSC2, the phase frequency comparison circuit PFD2, the charge pump circuit CP2, and the low pass filter LPF2. The substrate bias Vbn1 changes so that the rising edges of RCLK are at the same timing.

  After all, the above two phase-locked loop systems change the substrate biases Vbn1 and Vbn1 so that the rising and falling edges of the oscillation output OCLK1 of the frequency variable oscillation circuit OSC2 are the same timing as the rising and rising edges of the reference clock RCLK. become. In other words, the substrate biases Vbn1 and Vbn1 change so that the phase, frequency, and duty ratio of the oscillation output OCLK1 of the variable frequency oscillation circuit OSC2 and the phase, frequency, and duty ratio (50%) of the reference lock RCLK are the same. Will do.

  The substrate biases Vbp1 and Vbn1 should not be determined independently.For example, the drain current (drive capability) of the PMOSFET and NMOSFET with the substrate bias applied to the back gate is set to an appropriate ratio such as 2: 1. It is necessary to keep it.

  The 'H' period of the oscillation output OCLK1 of the variable frequency oscillation circuit OSC2 mainly depends on the drive capability of the PMOSFET in the variable frequency oscillation circuit OSC2 (which depends on the threshold of the PMOSFET, that is, the substrate bias Vbn1 applied to the PMOSFET) The 'L' period is mainly determined by the driving capability of the NMOSFET in the variable frequency oscillation circuit OSC2 (which depends on the threshold of the NMOSFET, that is, the substrate bias Vbp1 applied to the NMOSFET). Therefore, the duty ratio of the oscillation output OCLK1 of the variable frequency oscillation circuit OSC2 is 50%, which means that the drive capability of the PMOSFET and NMOSFET is equal to the w (gate width) ratio of the PMOSFET and NMOSFET in the variable frequency oscillation circuit OSC2. This means that the balance between the substrate biases Vbp1 and Vbn1 is maintained.

  Thus, in the embodiment of FIG. 5, the values of the substrate biases Vbp1 and Vbn1 are determined by the frequency of the reference clock RCLK, and the balance of the substrate biases Vbp1 and Vbn1 is determined by the w ratio of the PMOSFET and NMOSFET in the frequency variable oscillation circuit OSC2. Will be decided.

  In FIG. 5, similarly to FIG. 3, the substrate biases 110 and 111 are generated from the substrate biases Vbp1 and Vbn1 using the substrate bias buffers SBUF1 and SBUF2.

  Therefore, as in the case of FIG. 3, even if a large load is connected to the substrate biases 110 and 111, the substrate biases Vbp1 and Vbn1 are not affected. Therefore, the design of the phase-locked loop system is facilitated, and the time (lock time) during which the phase-locked loop system is stabilized can be shortened.

  Of course, as in the case of FIG. 3, the structure of the substrate bias buffers SBUF1 and SBUF2 is not particularly limited to that shown in FIG. Any substrate that can receive the substrate biases Vbp1 and Vbn1 with high impedance and output them to 110 and 111 with low impedance may be used.

  FIGS. 6A and 6B are embodiments of the substrate bias switches 200 and 201 in FIG. 1, respectively. This can be realized with the same substrate bias buffers SBUF1 and SBUF2 as shown in FIGS.

  When 401 is “H”, substrate biases 110 and 111 are received with high impedance, and are output to 112 and 113 with gain 1 at low impedance.

  When 400 is 'L', Vddq and Vssq are output to 112 and 113, respectively, and at the same time, the current of the low current source supplied to the differential amplifiers CM1 and CM2 is turned off, and the substrate bias switches 200 and 201 Power consumption is reduced.

  FIG. 7 shows another embodiment of the present invention.

  In FIG. 1, a PMOS substrate bias 110 and an NMOS substrate bias 111 adapted to the operating frequency are output from the substrate bias control circuit 100, but only the bias 120 is output in FIG. When the power control signal 401 or 402 is “H”, the PMOS substrate bias switch 204 and the NMOS substrate bias switch 205 output the PMOS substrate bias 112 and the NMOS substrate bias 113 from the bias 120. The PMOS substrate bias 112 and the NMOS substrate bias 113 are input to the MOSFET back gate of the circuit block 300.

  The bias 120 may be one of the PMOS substrate bias 110 and the NMOS substrate bias 111 of FIG. For example, if the bias 120 is the same signal as the PMOS substrate bias 110 in FIG. 1, the substrate bias switch 204 may be the same as the substrate bias switch 200 in FIG. Further, when the power control signal 401 or 402 is “H”, the substrate bias switch 205 can generate a signal corresponding to the NMOS substrate bias 111 from the bias 120 (in this case, the same as the PMOS substrate bias 110), and can output it to the substrate bias 113. Anything is acceptable.

  The same effect as in the case of FIG. 1 can be obtained. Further, in the case of FIG. 1, the substrate bias is supplied to the substrate control blocks 310 and 311 by one wire of the bias 120 in the embodiment of FIG. Therefore, there is an advantage that the wiring efficiency is improved.

  FIG. 8 shows an embodiment of the substrate bias control circuit 100 of FIG.

  This can be realized by removing the substrate bias buffer SBUF1 from FIG. That is, the bias 120 is the same signal as the NMOS substrate bias 111 of FIG. The circuit operation of FIG. 8 is the same as that of FIG.

  FIG. 9 shows an embodiment of the substrate bias 205 of FIG. 7 when the circuit of FIG. 8 is used for the substrate bias control circuit 100 of FIG. Note that the circuit shown in FIG. 6B can be used as it is for the substrate bias switch 204 in that case.

  The circuit of FIG. 9 is the same as the substrate bias mirror circuit in the embodiment of FIGS. 3 and 8, and receives the substrate bias 120 and outputs the substrate bias 113. This operation is described in detail here.

  Although not particularly limited, for simplicity of explanation, 401 is assumed to be “H”, and Vddq = 3.3V, Vdd = 1.0V, Vss = 0.0V, and Vssq = −2.3V.

  MP3 to MP5 are PMOSFETs, and MN3 to MN5 are NMOSFETs. The gate lengths of MP3 and MN3 are equal and the w (gate width) ratio is m: 1. Similarly, the gate lengths of MP5 and MN5 are equal and the w (gate width) ratio is set to m: 1. CM3 is a differential amplifier, amplifies the potential difference between Vh1 and Vh2, and inputs the output Vh3 to the gate of MP5.

  A voltage corresponding to the driving ability of MP3 and MN3 is output to Vh1 by the voltage divider consisting of MP3 and MN3. That is, when Vh1 is 0.5V (= (Vdd + Vss / 2) + Vss), it means that the drive capacities of MP3 and MN3 are equal. Now, it is assumed that the driving capabilities of MP3 and MN3 are equal, and Vh1 is assumed to be 0.5V.

  Since the output Vh3 of the differential amplifier CM3 controls the substrate bias of the MP4 and thereby the potential of Vh2 is controlled, the differential amplifier CM3 is negatively fed back. Therefore, in the steady state, the potential of Vh2 becomes the same potential as Vh1, and becomes 0.5V.

  Since the voltage corresponding to the driving capacity of MP3 and MN3 is output to Vh2 by the voltage divider consisting of MP4 and MN4, the potential of Vh2 of 0.5V means that the driving capacity of MP4 and MN4 is equal. means.

  Therefore, by setting the w ratio of MP3 and MN3 and the w ratio of MN4 of MP4 to the same value, it is input while maintaining the drive capacity ratio of MN4 of MP4 when the substrate bias is set to the same potential as the source potential. The potential of the substrate bias 113 is output with respect to the substrate bias 120.

  As described above, the substrate biases 120 and 113 should not be determined independently, for example, the drain current (driving capability) per unit gate width of the PMOSFET and the NMOSFET in which those substrate biases are applied to the back gate. 9 must be kept at an appropriate ratio such as 2: 1, but this can be realized by the circuit of FIG.

  In general, the substrate bias dependency of the threshold voltage is different between the PMOSFET and the NMOSFET, and the dependency of the drain current per unit gate width due to the change of the power supply voltage is also different. For example, as the power supply voltage decreases, the driving capability of the PMOSFET is significantly lower than that of the NMOSFET. By using the substrate bias mirror circuit SBM of FIG. 9 of the present invention, the difference in dependency can be compensated.

  FIG. 9 shows that when 401 is “L”, Vddq is output to the substrate bias 113, and the current supplied to the voltage divider consisting of MP3 and MN3, MP4 and MN4, and the differential amplifier CM3 is turned off and consumed. Electric power is reduced.

  FIG. 10 shows an embodiment of the power supply wiring of the substrate biases 110 and 111 of FIG. The power control circuit and the standby signal output therefrom are omitted for simplicity.

  500 is a microcomputer, for example, and the internal power supply of the microcomputer is supplied by Vdd and Vss. Reference numeral 501 denotes an I / O circuit for an external interface, to which a voltage Vddq higher than Vdd is supplied. The power supply voltage potential is not particularly limited. For example, Vddq = 3.3V, Vdd = 1.0V, Vss = 0.0V, and Vssq = −2.3V. This voltage setting has the advantage that Vddq-Vss and Vdd-Vssq have the same potential difference, and device design is facilitated.

  The circuit in the microprocessor is divided into four board control blocks MA1 to MA4. Reference numerals 200 and 201 are the same as those of the substrate bias switch of FIG. The source of the reference clock RCLK is not limited, but may be generated from a clock signal in the microprocessor 500.

  Here, the substrate biases 110 and 111 are fed using the method of the invention of Japanese Patent Application No. 8-314506. That is, the substrate bias of each transistor is supplied by the surface high-concentration diffusion layer DL for taking the substrate potential from the metal third layer M3 to the metal second layer M2.

  Since the first layer of metal is not used, each transistor can be mounted with high density.

  The method of using the metal of this embodiment is not particularly limited.

  FIG. 11 shows an example of a cross-sectional view of a substrate structure (well structure) for realizing FIG. N wells and p wells are alternately arranged on the surface of the substrate, and a circuit can be mounted by forming transistors on the surface. The m well is an n-polar well.

  The n well in the substrate control block MA1 and the n well in the substrate control block MA2 are electrically separated by the p substrate, and the p well in the substrate control block MA1 and the p well in the substrate control block MA2 have n polarity. It is electrically isolated by the m-well.

  Therefore, independent substrate biases can be applied to the PMOSFET in the substrate control block MA1, the PMOSFET in the substrate control block MA2, and the NMOSFET in the substrate control block MA1 and the NMOSFET in the substrate control block MA2. Can be realized.

  In FIG. 3, FIG. 5 or FIG. 8, the operation as described above is performed when 400 is “H”, but when it is “L”, the oscillation of the variable frequency oscillation circuit OSC1 or OSC2 is stopped and the substrate bias is applied. The mirror circuit SBM and the substrate bias buffers SBUF1 and SBUF2 are in a low power state. Therefore, the power consumption of the entire circuit is reduced.

  In the microprocessor using the present invention, the power consumption of the microprocessor during standby can be reduced by connecting 400 signals to the standby signal of the microprocessor.

  Alternatively, 400 may be set to “L” during the microprocessor IDDQ test. Since the leakage current flowing through the circuit of FIG. 3, FIG. 5 or FIG. 8 is reduced and a large substrate bias value is output to the substrate bias 110, 111, the MOSFET whose threshold is controlled by the substrate bias 110, 111 The subthreshold leakage current can be reduced.

  Further, when 400 is “L”, the outputs UP and DN of the phase frequency comparators PFD, PFD1, and PFD2 may be fixed to “H” and “L”, respectively. The discharge of the capacitance C1 in the low-pass filters LPF, LPF1, and LPF2 when the 400 is set to “L” is suppressed. Since the potential of the capacitance C1 is maintained even when the switching is performed at a high frequency of 400, power consumption for charging and discharging the capacitance C1 can be reduced.

  In the above embodiments, the transistor structure and the substrate structure are not particularly limited. A MOS transistor having an SOI structure as described in IDM, Technical Digest, pages 35 to 38, 1992 (1992 IEDM Technical Digest, pp 35-38) may be used. In short, any transistor having a structure in which the threshold value can be controlled may be used.

1 is a diagram of the simplest embodiment of the present invention. It is a figure which shows a prior art example. It is a figure of the Example of the substrate bias control circuit of FIG. It is a figure showing operation | movement of the substrate bias mirror circuit of FIG. FIG. 4 is a diagram of another embodiment of the substrate bias control circuit of FIG. 1. (A) is a diagram of an embodiment of a PMOS substrate bias switch, (B) is a diagram of an embodiment of an NMOS substrate bias switch. It is a figure of another Example of this invention. FIG. 8 is a diagram of an embodiment of the substrate bias control circuit of FIG. 7. FIG. 8 is a diagram of an example of the PMOS substrate bias switch of FIG. 7. It is a figure of the Example which shows the substrate bias distribution method when this invention is applied to a microprocessor. It is a figure which shows the board | substrate structure example which implement | achieves this invention.

Explanation of symbols

100 …… Substrate bias control circuit,
110, 112, Vbp0, Vbp1 ... PMOS substrate bias,
111, 113, Vbn0, Vbn1 …… NMOS substrate bias,
120 …… Power control circuit,
310, 311 …… Board control block,
200 …… PMOS substrate bias switch,
201 …… NMOS substrate bias switch,
300 …… Circuit block,
LOG0 …… Main circuit,
OSC0, OSC1, OSC2 …… Variable frequency oscillation circuit,
CNT0 …… Control circuit,
CLK0, RCLK ...... reference clock,
400, 401, 402 …… Standby signal,
MP1, MP2, MP3, MP4, MP5 …… P-type MOSFET,
MN1, MN2, MN3, MN4, MN5 …… N-type MOSFET,
CM1, CM2, CM3 …… Operating amplifier,
SBM …… Board bias mirror circuit,
Vddq …… Second positive power supply potential
Vdd …… First positive power supply potential,
Vss …… First negative power supply potential
Vssq …… Second negative power supply potential,
CNV1, CNV2 …… Voltage level converter,
CP, CP1, CP2 …… Charge pump circuit,
LPF, LPF1, LPF2 …… Low-pass filter,
PFD, PFD1, PFD2 …… Phase frequency comparison circuit,
R1, R2 …… resistance,
C1 …… Capacitance,
SBUF1 …… PMOS substrate bias buffer,
SBUF2 …… NMOS substrate bias buffer,
204, 205 …… Substrate bias switch,
MA1, MA2, MA3, MA4 …… Board control block,
M3 …… Third layer metal,
M2 …… Second layer metal,
500 …… Microprocessor,
501 …… I / O circuit.

Claims (12)

A logic circuit including a first MIS transistor of a first conductivity type and a second MIS transistor of a second conductivity type;
A substrate bias control circuit for generating a first substrate bias voltage to be applied to the first MIS transistor and a second substrate bias voltage to be applied to the second MIS transistor;
The substrate bias control circuit determines the magnitude of the second substrate bias voltage with respect to the first substrate bias voltage so as to maintain the drive capability ratio of the second MIS transistor to the first MIS transistor when the source potential is applied to the substrate. A semiconductor integrated circuit device. In claim 1,
A semiconductor integrated circuit device in which the driving capability is defined by a drain current per unit gate width In claim 1,
The substrate bias control circuit has a differential amplifier,
One input of the differential amplifier is a voltage divided by a first conductivity type third MIS transistor and a second conductivity type fourth MIS transistor, each of which is turned on and whose source potential is applied to the substrate. Is entered,
The other input of the differential amplifier has an ON state and a first conductivity type fifth MIS transistor to which the first substrate bias voltage is applied to the substrate, and an ON state and the second input to the substrate. A voltage divided by the second conductivity type sixth MIS transistor to which the substrate bias voltage is applied is input,
A semiconductor integrated circuit device in which the magnitude of the second substrate bias voltage is controlled by the output of the differential amplifier. In claim 3,
The gate lengths of the third MIS transistor and the fourth MIS transistor are equal, and the gate width ratio is set to 1: m.
A semiconductor integrated circuit device in which the fifth MIS transistor and the sixth MIS transistor have the same gate length and a gate width ratio of 1: m. In claim 3,
An oscillation output circuit including a first conductivity type seventh MIS transistor and a second conductivity type eighth MIS transistor, and configured to be able to vary a frequency of oscillation output;
A semiconductor integrated circuit that receives a clock signal having a predetermined frequency and an oscillation output output from the oscillation output circuit, and compares the frequency of the clock signal with the frequency of the oscillation output to generate the first substrate bias voltage. Circuit device. In claim 5,
The semiconductor integrated circuit device, wherein the first substrate bias voltage and the second substrate bias voltage are respectively supplied to the first MIS transistor and the second MIS transistor via a buffer circuit. In claim 5,
The semiconductor integrated circuit device, wherein the first substrate bias voltage and the second substrate bias voltage are supplied to the seventh MIS transistor and the eighth MIS transistor without passing through a buffer circuit. A logic circuit including a first MIS transistor of a first conductivity type and a second MIS transistor of a second conductivity type;
A substrate bias control circuit for generating a first substrate bias voltage to be applied to the first MIS transistor and a second substrate bias voltage to be applied to the second MIS transistor;
The substrate bias control circuit has a differential amplifier,
One input of the differential amplifier is a voltage divided by a first conductivity type third MIS transistor and a second conductivity type fourth MIS transistor, each of which is turned on and whose source potential is applied to the substrate. Is entered,
The other input of the differential amplifier has an ON state and a first conductivity type fifth MIS transistor to which the first substrate bias voltage is applied to the substrate, and an ON state and the second input to the substrate. A voltage divided by the second conductivity type sixth MIS transistor to which the substrate bias voltage is applied is input,
A semiconductor integrated circuit device in which the magnitude of the second substrate bias voltage is controlled by the output of the differential amplifier. In claim 8,
The gate lengths of the third MIS transistor and the fourth MIS transistor are equal, and the gate width ratio is set to 1: m.
A semiconductor integrated circuit device in which the fifth MIS transistor and the sixth MIS transistor have the same gate length and a gate width ratio of 1: m. In claim 8,
An oscillation output circuit including a first conductivity type seventh MIS transistor and a second conductivity type eighth MIS transistor, and configured to be able to vary a frequency of oscillation output;
A semiconductor integrated circuit that receives a clock signal having a predetermined frequency and an oscillation output output from the oscillation output circuit, and compares the frequency of the clock signal with the frequency of the oscillation output to generate the first substrate bias voltage. Circuit device. In claim 10,
The semiconductor integrated circuit device, wherein the first substrate bias voltage and the second substrate bias voltage are respectively supplied to the first MIS transistor and the second MIS transistor via a buffer circuit. In claim 10,
The semiconductor integrated circuit device, wherein the first substrate bias voltage and the second substrate bias voltage are supplied to the seventh MIS transistor and the eighth MIS transistor without passing through a buffer circuit.

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