JP2001077685A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, capable of suppressing the variation of an operation delay time due to local power source fluctuations to be small with respect to the clock buffer of a clock supplying system using simple circuit constitution. SOLUTION: When local power source fluctuations occur in a semiconductor integrated circuit, a power source fluctuation detecting circuit 21A in a clock buffer 5 receiving its influence tries to control the mutual conductance of a current source MOS transistor Mn3 of amplifier circuits 11A, 12A in the buffer 5 in a direction of suppressing the variation of the current driving capability of the amplifier circuits. Thus, even if such local power source fluctuation occurs, the voltage between the gate and source of the transistor Mn3 is kept to be nearly constant to reduce the variation of the operation delay time of the clock buffer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to reduction of clock skew in a clock synchronous semiconductor integrated circuit.

[0002]

2. Description of the Related Art MOS (Metal Oxide Semiconductor)
Mold or MIS (Metal Insulate Semiconductor)
In a semiconductor integrated circuit in which a voltage-controlled transistor (hereinafter simply referred to as a MOS transistor) such as a field-effect transistor is formed, each time a switching state of a transistor constituting various circuits is switched, the transistor switches to a signal. The load on the wiring is charged or discharged, and a current for that flows to the power supply wiring. At this time, a relatively large charge / discharge current flows through the power supply wiring in a region where circuits with a large load and circuits with a high switching operation frequency are densely packed. Since the power supply wiring has a resistive component,
On the power supply wiring in and around the dense area, the ground voltage of the circuit as a low-level power supply voltage undesirably increases, and the power supply voltage as a high-level power supply voltage undesirably lowers. Such a local fluctuation of the power supply voltage affects the operation of the peripheral circuits.
For example, the delay time of the circuit operation varies.

Japanese Patent Application Laid-Open No. H10-15 / 15 discloses a technique which focuses on the variation of the delay time of the circuit operation due to the fluctuation of the power supply voltage.
There is one described in Japanese Patent No. 5011. This is because, in order to control the operation delay of an interface cell in which a plurality of inverters are arranged in series, a delay chain that simulates the operation delay time of the interface cell is provided, and the signal passes through the operation reference clock signal and the delay chain. A control signal corresponding to a phase difference from the operation reference clock signal is
When the phase of the operation reference clock signal generated by the L circuit is advanced, the operation current of the interface cell is increased so as to reduce the operation delay of the interface cell,
When the phase of the operation reference clock signal is delayed, the operation current of the interface cell is reduced so as to increase the operation delay of the interface cell.

[0004]

The present inventor has studied the case where the local power supply fluctuation affects the characteristics of a clock buffer included in a clock signal supply system in a clock synchronous semiconductor integrated circuit. If the operation characteristics of the clock buffer, especially the operation delay time, vary due to local power supply fluctuation, an undesired timing shift (skew) occurs in the clock signal supplied to the sequential circuits of the respective units to be synchronously operated. Cause. Further, it becomes an obstacle to improve the operation speed of the whole semiconductor integrated circuit.

[0005] The clock buffers are distributed over the entire area of the semiconductor integrated circuit, and the number thereof is large. The clock buffers cannot escape from local fluctuations in the power supply voltage. Since there is a possibility that different power supply fluctuations may occur for each clock buffer, when the above-described known technique is adopted, a delay chain or P
An LL circuit must be provided, and the area occupied by the chip due to the LL circuit is expected to be so large that it cannot be ignored.
Further, even if the clock buffer is formed of a differential amplifier circuit, if the power supply voltage fluctuates, the amount of current flowing through the current source changes, causing variations in the operation delay time.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the variation in the operation delay time due to the local power supply fluctuation with respect to the clock buffer of the clock supply system, and to realize it with a relatively simple circuit configuration. It is to provide a semiconductor integrated circuit which can be used.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the semiconductor integrated circuit is arranged in a plurality of logic circuits, a clock generation circuit, a clock supply path for supplying a clock signal generated by the clock generation circuit to the logic circuit, and a clock supply path. The clock buffer and the reference voltage generation circuit are provided on one semiconductor chip. The clock buffer includes an amplifier circuit having an input terminal and an output terminal connected to the clock supply path, a current source MOS transistor that supplies operating power to the amplifier circuit, and a power supply fluctuation detection circuit. The power supply fluctuation detection circuit receives a reference voltage output from the reference voltage generation circuit, forms a gate control signal for the current source MOS transistor, and detects a change in a current driving capability of the amplifier circuit due to a change in an operation power supply. The level of the gate control signal of the current source MOS transistor is changed in the direction of suppressing.

According to the above, when a local power supply fluctuation occurs in the semiconductor integrated circuit, the clock buffers affected by the power supply fluctuation detection individually detect the power supply fluctuation in a direction to suppress a change in the current driving capability of the amplifier circuit. The circuit is the current source MOS
Attempts to control the transconductance of the transistor. As a result, even if such a local power supply fluctuation occurs, the gate-source voltage of the current source MOS transistor is kept substantially constant, and the variation in the operation delay time of the clock buffer due to such a local power supply fluctuation. Is reduced. Therefore, the skew of the clock signal supplied to the sequential circuit of each unit to be synchronized can be reduced, and the operation speed of the entire semiconductor integrated circuit can be improved. Further, the reference for detecting power supply fluctuation is the reference voltage, and a circuit for forming such a reference voltage includes a PL
It is easy to adopt a simpler circuit than the L circuit,
Further, since it is not necessary to provide such a reference voltage generating circuit for each clock buffer, it is possible to suppress the variation in the operation delay time due to the local power supply fluctuation with respect to the clock buffer of the clock supply system. The operation and effect described above can be realized by a relatively simple circuit configuration.

If a signal line for supplying the reference voltage to the clock buffer is provided along the clock line of the clock supply system, the signal line for the reference voltage becomes a shield line of the clock line, and the noise resistance of the clock signal is reduced. improves.

The current source MOS transistor is, for example, an n-channel type MOS transistor connected to a ground line for supplying a low-level power supply voltage of the circuit to the amplifier circuit. A configuration of a level shift circuit that raises the level of the gate control signal by increasing the low-level power supply voltage on the line can be employed.

The current source MOS transistor is, for example, a p-channel type MOS transistor connected to a power supply line for supplying a high-level power supply voltage to the amplifier circuit. Of the level shift circuit that lowers the level of the gate control signal due to the fall of the high-level power supply voltage.

The amplifier circuit may employ a configuration including a differential amplifier circuit that receives a clock signal as a differential input at a complementary level. The amplifier circuit may have a configuration including an inverter circuit that inverts and amplifies a single-phase clock signal.

The reference voltage generating circuit has a relatively small power fluctuation due to the influence of the load on the semiconductor chip, for example, a region where operation power can be supplied from a power supply main line, or a relatively high degree of circuit integration. It may be formed in a sparse region. Alternatively, the reference voltage generating circuit may be constituted by a circuit having little dependency on the power supply voltage, for example, a circuit using a threshold voltage difference between MOS transistors of different conductivity types, a threshold voltage of a diode, and the like.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS << Semiconductor Integrated Circuit >> FIG. 2 shows a chip layout of a semiconductor integrated circuit according to an example of the present invention, mainly a clock supply system. The semiconductor integrated circuit 1
For example, it is formed on one semiconductor substrate (semiconductor chip) such as single crystal silicon by a CMOS integrated circuit manufacturing technique. Although not particularly limited, the semiconductor integrated circuit 1 is a system LSI in which a DRAM or the like is mounted together with a clock synchronous microcomputer or a data processing device.
Alternatively, it corresponds to a peripheral function LSI. A plurality of input / output buffers 3 and the like mainly for an external interface are arranged at a peripheral portion of the semiconductor chip 2. At the center of the semiconductor chip 2, a logic circuit as a functional module for realizing required data processing functions such as an arithmetic processing function and a data storage function is formed by a sequential circuit, a combination circuit, or the like.

The semiconductor integrated circuit 1 uses an external oscillator (not shown) as the original oscillation or inputs a system clock signal from the outside. The clock signal as such an original oscillation is not particularly limited, but is multiplied to a required frequency by a clock generation circuit 4 such as a PLL circuit and output as an operation reference clock signal CLK. Clock signal CLK
Are supplied to a sequential circuit of the functional module and the like via a clock supply system formed in an H shape by the clock buffers 5, 6, 7 and the clock wiring 8. In FIG. 2, the output of the clock buffer 7 at the end of the clock supply system is connected to the clock input terminal of the sequential circuit via a clock wiring in a functional module (not shown) although not particularly limited. In FIG. 2, the four clock buffers 7 are dedicated to the areas 9A to 9D, respectively.

In this semiconductor integrated circuit, as a basic configuration of a clock supply system for reducing clock skew,
For example, clock wirings of the same hierarchy have the same length and the same width. According to FIG. 2, the clock wiring from the clock buffer 5 to the clock buffer 6, the clock wiring from the clock buffer 6 to the clock buffer 7, and the clock wiring in the module from the clock buffer 7 to the sequential circuit have the same length. And it is made the same width.

It is needless to say that a similar H-shaped clock supply system may be further connected to the output of the clock buffer 7 at the end of the clock supply system to supply a clock signal to the sequential circuit. In short, FIG. 2 shows only one layer of the H-shaped clock supply system, but a plurality of H-shaped clock supply systems may be provided to form the clock supply system.

FIG. 1 shows an example of the clock buffer 5. The example in the figure assumes that the clock signal is transmitted as a complementary signal. The clock buffer 5 includes:
It has a pair of differential amplifier circuits 11A and 12A as an amplifier circuit. The differential amplifier circuits 11A and 12A have n-channel type differential input MOS transistors Mn1 and Mn2,
The drains of the MOS transistors Mn1 and Mn2 are connected to diode-connected p-channel load MOS transistors Mp1 and Mp2, and the common source of the MOS transistors Mn1 and Mn2 is connected to an n-channel current source MOS transistor Mn3. I have. The gates of the differential differential input MOS transistors Mn1 and Mn2 of the preceding differential amplifier circuit 11A are connected to the clock input terminal CIN.
t, CINb, and the output node of the preceding differential amplifier circuit 11A is connected to the differential differential input M of the subsequent differential amplifier circuit 12A.
Coupled to the gates of the OS transistors Mn1 and Mn2,
The output node of the subsequent differential amplifier circuit 12A is coupled to clock output terminals COUTt and COUTb.

The load M of the differential amplifier circuits 11A and 12A
The sources of the OS transistors Mp1 and Mp2 are connected to the power supply line 13, and the ground line 14 is connected to the sources of the current source MOS transistors Mn3 of the differential amplifier circuits 11A and 12A. The power supply line 13 has a power supply voltage VDD applied to the external power supply terminal 15 of the chip 2.
Are supplied via a power supply line 16. Similarly, a ground voltage VSS of a circuit applied to an external power supply terminal 17 of the chip 2 is supplied to the ground line 14 via a ground line 18. Power line 16, ground line 1
The resistors 16R and 18R shown in FIG.
8 are collectively referred to.

The other clock buffers 6 and 7 have the same basic circuit configuration as that of FIG. However, the driving capability of the second-stage differential amplifier circuit 12A may be different depending on the magnitude of the driving load, that is, the number of fan-outs of the clock buffer.

<< Countermeasures for Clock Skew Due to Power Supply Fluctuation >> In order to take measures against clock skew against local power supply fluctuation inside the semiconductor integrated circuit, a reference voltage generating circuit is provided in a peripheral area of the semiconductor chip 2 as shown in FIG. 1, and each of the clock buffers 5, 6, and 7 is provided with a power supply fluctuation detection circuit 21A, as illustrated in FIG.

Although not particularly limited, the reference voltage generation circuit 20 generates the reference voltage 22 by dividing the level of the power supply voltage VDD with respect to the ground voltage VSS by resistance. In the peripheral area of the semiconductor chip 2, the reference voltage generation circuit 2
The region where 0 is formed is a region where the operating power can be received from the power supply main line, the circuits are not densely packed, and the fluctuation of the power supply due to the influence of the load on the semiconductor chip is relatively small. Therefore, the reference voltage generating circuit 20
Regardless of the operation state of the semiconductor integrated circuit, there is little risk of receiving a local power supply fluctuation, and the reference voltage 22 can be maintained at a substantially constant level.

As the reference voltage generating circuit, a circuit having little dependency on the power supply voltage, for example, a circuit configuration utilizing a threshold voltage difference between MOS transistors of different conductivity types and a threshold voltage of a diode may be employed.

The signal wiring 10 for supplying the reference voltage 22 to the clock buffers 5, 6, and 7 is provided along the clock wiring 8 of the clock supply system as illustrated in FIG. Thus, the signal wiring 10 for the reference voltage 22 becomes a shield wiring for the clock wiring 8, and the noise resistance of the clock signal CLK can be improved.

The power supply fluctuation detecting circuit 21A is a current source type level shift circuit in which an n-channel switching MOS transistor Mn4 receiving the reference voltage 22 at its gate and a p-channel load MOS transistor Mp3 diode-connected are connected in series. Composed of
The drain voltage of the MOS transistor Mn4 is given as a gate control signal (gate bias signal) 23 for the current source transistor Mn3.

Here, before describing the operation of the power supply fluctuation detecting circuit 21A, a local power supply fluctuation will be described. FIG.
For example, when a relatively larger current flows in the region E1 in the semiconductor integrated circuit 1 than in the surroundings, for example, the power supply voltage VD
D drops, and the ground voltage VSS on the ground wiring rises in level. The cause is the resistance 16R of the power supply line 16 and the resistance 18R of the ground line 18, as shown in FIG. When a large current flows through the circuit in the region E1, the power supply voltage whose voltage has dropped by the resistive component 16R and the ground voltage whose level has increased by the resistance component 18R are used as the operating power supply for the circuit in the region E2.

The operation of the clock buffers 5, 6, and 7 for the above-mentioned local power supply fluctuation will be described with reference to FIG. In particular, the configuration of the clock buffer shown in FIG. 1 considers the following conditions. That is, a circuit that operates in synchronization with the operation reference clock signal CLK in the semiconductor integrated circuit 1 includes:
The charge and discharge of the load are repeated every clock cycle. Therefore, the current at that time flows through the power supply line 13 and the ground line 14, and a local power supply potential variation corresponding to the respective power supply line resistance occurs. The power fluctuation detecting circuit 21A of FIG. 1 copes with a local power fluctuation occurring on the ground line 14 among the fluctuations.

When a large current flows through the ground line 18 in a circuit near the clock buffers 5, 6, and 7, the ground voltage VSS rises in the module ground line 14 via the resistive component 18R as described above. I do.
At this time, the reference voltage 22 maintains a constant level.

When the level of the ground voltage VSS rises on the ground line 14 in the module, the MOS transistor M
The gate-source voltage of n4 decreases, and the drain current of the MOS transistor Mn4 decreases. As a result, the level of the gate control signal 23 rises, so that it is possible to prevent a situation in which the gate-source voltage of the current source MOS transistor Mn3 decreases by the rise of the source voltage of the MOS transistor Mn3. If the level of the gate control signal of the current source MOS transistor Mn3 is controlled to a constant level, the gate bias voltage of the MOS transistor Mn3 increases as the level of the ground voltage VSS on the ground line 14 in the module increases. The circuit current decreases, and the differential amplifier circuit 11A,
The transconductance of 12A, that is, the current driving capability decreases, and the amplification operation speed as a clock buffer decreases. In the example of FIG. 1, even when an undesired level rise occurs on the ground line 14 in the module, the differential amplifier circuit 1
The current driving capabilities of 1A and 12A are kept almost constant, and there is almost no fluctuation in the amplification operation speed as a clock buffer.

FIG. 5 shows another example of the clock buffer. The following conditions are considered in the circuit configuration of FIG. That is, in the semiconductor integrated circuit 1, the operation reference clock signal C
The circuit that operates in synchronization with the LK repeats charging and discharging of the load every clock cycle, and is similar to FIG. 1 in that local power fluctuations occur in the power supply line 13 and the ground line 14. The power fluctuation detecting circuit 21B in FIG. 5 copes with a local power fluctuation occurring in the power line 13 among the fluctuations.

The circuit configuration of FIG. 5 differs from the circuit configuration of FIG. 1 in that VDD, VSS, p-channel MOS transistors,
And a circuit configuration in which n-channel MOS transistors are replaced. That is, in FIG. 5, the differential amplifier circuits 11B and 12B include n-channel type load MOS transistors Mn11 and Mn12 and a p-channel type differential input M.
OS transistors Mp11 and Mp12 and a current source M
The OS transistor Mp3 is of a p-channel type. The power supply fluctuation detecting circuit 21B receives the reference voltage 22 at the gate of the p-channel MOS transistor Mp14, and includes an n-channel load MOS transistor Mn13.

The operation of the clock buffer 5 shown in FIG. 5 will be described. When the level of the power supply voltage VDD drops on the power supply line 13 in the module, the MOS transistor Mp
The voltage between the gate and source of the MOS transistor Mp14 decreases, and the drain current of the MOS transistor Mp14 decreases. As a result, the level of the gate control signal 23 decreases, so that it is possible to prevent a situation in which the gate-source voltage of the current source MOS transistor Mp13 decreases in accordance with the drop of the source voltage. If the level of the gate control signal of the current source MOS transistor Mp13 is controlled to a constant level, the drain current of the MOS transistor Mp13 decreases as the level of the power supply voltage VDD on the power supply line 13 in the module decreases. In addition, the current driving capability of the differential amplifier circuits 11B and 12B decreases, and the amplification operation speed as a clock buffer decreases. In the example of FIG. 5, even if an undesired level drop occurs on the power supply line 13 in the module, the current driving capabilities of the differential amplifier circuits 11B and 12B are kept almost constant, and the fluctuation of the amplification operation speed as a clock buffer is reduced. Almost no.

FIG. 6 shows still another example of the clock buffer. The clock buffer of FIG. 6 amplifies the operation reference clock signal CLK in a single phase and outputs it. A p-channel type current source MOS transistor Mp mainly includes a CMOS inverter 35 including a p-channel type MOS transistor Mp20 and an n-channel type MOS transistor Mn20.
22 and n-channel type voltage source MOS transistor Mn
Circuits 22 are connected in two stages in series to amplify the clock signal CLK. The power supply fluctuation detecting circuit 21A receives the gate control signal 2 of the voltage source MOS transistor Mp22.
Form 3 The gate control signal 31 of the voltage source MOS transistor Mn22 is generated by another reference voltage generation circuit 30, and is set to a substantially constant voltage. The circuit configuration of FIG.
The same condition as in the case of FIG. 1, that is, the condition that local power supply fluctuation occurs in the ground line 14 is addressed. Its operation is the same as that of FIG. 1 and a detailed description is omitted.
Even if an undesired level rise occurs on the gate 4, the current driving capability of the CMOS inverter 35 is kept almost constant, and there is almost no fluctuation in the amplification operation speed as the clock buffer 5 (6, 7).

FIG. 7 shows an example of a clock buffer applied to a semiconductor integrated circuit which amplifies an operation reference clock signal in a single phase as in FIG. 6 and operates under the same conditions as in FIG. The difference from FIG. 6 is that the power supply fluctuation detecting circuit 21B is a gate control signal 23 for the voltage source MOS transistor Mn22.
To form The gate control signal 33 for the voltage source MOS transistor Mp22 is generated by another reference voltage generation circuit 32 and is set to a substantially constant voltage. The circuit configuration of FIG. 7 deals with the same condition as that of FIG. 5, that is, the condition that local power supply fluctuation occurs in the power supply line 13.
The operation is the same as that of FIG. 5, and the detailed description is omitted. However, as described above, even if an undesired level drop occurs on the power supply line 13 in the module, the current driving capability of the CMOS inverter 35 is substantially constant. Thus, there is almost no change in the amplification operation speed as the clock buffer.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist thereof. No.

For example, the amplifier circuit provided in the clock buffer is not limited to the serial two-stage differential amplifier circuit or the CMOS inverter having the above-described circuit configuration, and can be appropriately changed.

The structure of the clock signal supply system is shown in FIG.
It is not limited to. For example, a clock tree structure other than the letter H may be employed. Further, the clock signal may be supplied to each functional module in a single phase, and a non-overlapping two-phase clock signal may be formed from the single-phase clock signal in the functional module and supplied to the terminal sequential circuit. Further, the configuration of the power supply fluctuation detecting circuit is not limited to the level shift circuit, and can be changed to an appropriate circuit configuration.

[0040]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, when a local power supply fluctuation occurs in the semiconductor integrated circuit, the clock buffers affected by the power supply fluctuation are individually controlled by the power supply fluctuation detection circuit in a direction to suppress a change in the current driving capability of the amplifier circuit. Current source MO
Since an attempt is made to control the drain current of the S transistor and the drain voltage of the voltage source MOS transistor, it is possible to reduce the variation in the operation delay time of the clock buffer due to such local power supply fluctuation.

As a result, the skew of the clock signal supplied to the sequential circuit of each section to be operated synchronously can be reduced, and the operation speed of the entire semiconductor integrated circuit can be improved.

Further, the reference for detecting power supply fluctuation is a reference voltage, and it is easy to employ a simple circuit as a circuit for forming such a reference voltage. Since it is not necessary to provide the buffer for each buffer, a relatively simple circuit configuration can be obtained in which the operation and effect that the variation in the operation delay time due to the local power supply fluctuation can be suppressed with respect to the clock buffer of the clock supply system. It can be realized by.

By providing a signal line for supplying the reference voltage to the clock buffer along the clock line of the clock supply system, the signal line for the reference voltage becomes a shield line for the clock line, and the noise resistance of the clock signal is reduced. Can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a clock buffer applied to a semiconductor integrated circuit according to the present invention, the circuit showing a clock buffer for coping with a local power supply fluctuation under a condition that a power supply fluctuation occurs on a ground line side. FIG.

FIG. 2 is a plan view mainly showing a clock supply system in a chip layout of a semiconductor integrated circuit according to an example of the present invention.

FIG. 3 is an explanatory diagram exemplarily showing a state of local power supply fluctuation.

FIG. 4 is an explanatory diagram exemplarily showing a resistive component causing local power supply fluctuation.

FIG. 5 is an explanatory diagram showing an example of a clock buffer for coping with a local power supply variation under a condition that a local power supply variation occurs in a power supply wiring.

FIG. 6 is an explanatory diagram illustrating an example of a clock buffer that amplifies a clock signal in a single phase and copes with local power supply fluctuation under the same conditions as in FIG. 1;

FIG. 7 is an explanatory diagram illustrating an example of a clock buffer that amplifies a clock signal in a single phase and copes with local power supply fluctuations under the same conditions as in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 Semiconductor chip 4 Clock generation circuit 5, 6, 7 Clock buffer 8 Clock wiring 10 Signal wiring for supply of reference voltage 11A, 11B, 12A, 12B Differential amplifier circuit 13 Power supply wiring in module 14 Ground wiring in module 15 power supply terminal 16 power supply line 17 ground terminal 18 ground line VDD power supply voltage VSS ground voltage 20 reference voltage generation circuit 21A, 21B power supply fluctuation detection circuit 22 reference voltage 23 gate control signal Mn3, Mp13 current source MOS transistor Mn21, Mp21 current source MOS Transistor 35 Inverter Mn22, Mp22 Voltage source MOS transistor

Claims (8)

[Claims] 1. A plurality of logic circuits, a clock generation circuit, a clock supply path for supplying a clock signal generated by the clock generation circuit to the logic circuit, and a plurality of clocks arranged in the clock supply path A buffer and a reference voltage generation circuit provided on a single semiconductor chip, wherein the clock buffer includes an amplification circuit having an input terminal and an output terminal connected to the clock supply path, and a current for supplying operating power to the amplification circuit. A gate control signal for the current source MOS transistor is formed based on a source MOS transistor and a reference voltage output from the reference voltage generation circuit, and a change in a current driving capability of the amplifier circuit due to a change in an operation power supply is suppressed. A power supply fluctuation detecting circuit for changing a level of the gate control signal of the current source MOS transistor in a direction. The semiconductor integrated circuit characterized in that made in. 2. The semiconductor integrated circuit according to claim 1, wherein a signal line for supplying the reference voltage to the clock buffer is provided along a clock line of the clock supply system. 3. The current source MOS transistor is an n-channel type MOS transistor connected to a ground line that supplies a low-level power supply voltage of a circuit to the amplifier circuit. 3. The semiconductor integrated circuit according to claim 1, further comprising a level shift circuit that raises the level of a gate control signal by increasing the low-level power supply voltage. 4. The power supply variation detection circuit according to claim 1, wherein the current source MOS transistor is a p-channel type MOS transistor connected to a power supply line for supplying a high-level power supply voltage to the amplifier circuit. 2. A level shift circuit for lowering the level of a gate control signal by a voltage drop.
Or the semiconductor integrated circuit according to 2. 5. The semiconductor device according to claim 1, wherein said amplifier circuit includes a differential amplifier circuit for differentially inputting a clock signal at a complementary level. Integrated circuit. 6. The semiconductor integrated circuit according to claim 1, wherein the amplifier circuit includes an inverter circuit that inverts and amplifies a single-phase clock signal. 7. The semiconductor device according to claim 1, wherein the reference voltage generation circuit is formed in a region where a power supply fluctuation caused by a load on a semiconductor chip is relatively small. The semiconductor integrated circuit according to the above. 8. The semiconductor integrated circuit according to claim 1, wherein said reference voltage generation circuit has a circuit configuration having little dependency on a power supply voltage.