JP3185773B2 - Clock signal generation system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock signal generation system, and more particularly to a clock signal generation system that generates an internal clock signal based on an oscillation signal or an external clock signal.

[0002]

2. Description of the Related Art Conventionally, a clock signal generation circuit for generating a clock signal to be input to a clock driver circuit has been known. This clock signal generation circuit is, for example, a one-chip large scale integrated circuit (LSI).
The clock signal is built in a microcomputer mainly composed of a microprocessor which is a ted circuit, and a clock signal is generated based on an oscillation signal from a crystal oscillator or an external clock signal input from the outside.

FIG. 8 shows a conventional clock signal generation circuit, and FIG. 8A is a block diagram in the case of using a crystal oscillator.
FIG. 3B is a block diagram when an external clock signal is used. As shown in FIG. 8, the clock signal generation circuit 1
An amplifier (Amp) 3, a waveform shaper 4, and a PLL (phase locked loop) built in the LSI 2.
It has a circuit 5, and an input side and an output side of the amplifier 3 are connected to external input terminals X1 and X2, respectively.

When a clock signal is generated by the clock signal generation circuit 1, a crystal oscillator 6 is connected to both external input terminals X1 and X2 (see (a)), or a level shifter 7 connected to the external input terminal X1. An external clock signal a is input from a tester (not shown) through the interface (see (b)). The internal clock signal generated by the clock signal generation circuit 1 is output from the PLL circuit 4 to the clock driver circuit 8.

The external input terminals X1 and X2 are also used as input terminals for a crystal oscillation signal, an external clock signal used by a user, a test clock signal, and the like. Further, a protection circuit 24 is provided between the amplifier 3 and the external input terminal X1 in order to prevent the internal circuit from being damaged by static electricity or surge voltage.

In recent years, in products incorporating a microcomputer, the drive voltage of the microcomputer has been changed from the conventional 5V system to the 3V system in order to reduce the current consumption due to an increase in demand for battery drive and the like. There is a tendency to lower the voltage.

[0007] The operating speed of microcomputers has been increasing year by year, and has been increasing to several hundred MHz. In order to realize high-speed operation, it is necessary to reduce the size of the transistors constituting the internal circuit as much as possible to reduce the parasitic capacitance and the parasitic resistance. As a result, the breakdown voltage of the transistor has become lower than the external power supply voltage, and the microcomputer has a step-down circuit inside so that the external power supply voltage is lowered and supplied to the internal circuit. Therefore, for example, even if the power supply voltage is 3V, the internal circuit operates at 2V.

[0008] Under such circumstances, the input / output (I / O) portion is currently the mainstream 5V system, whereas the drive voltage is internally 3V system or 3V or less. It is getting.

Although the above-mentioned microcomputer is designed so that the input / output terminals for the outside can input / output a signal having a 3V amplitude, the amplifier 3 for oscillating the clock must oscillate at a high frequency. It is composed of a low breakdown voltage transistor with a high breakdown voltage.

[0010] Under such circumstances, when a product is tested, an internal clock signal is usually generated by an external clock signal supplied from an externally connected tester to a clock signal generation circuit. When the internal clock signal is generated, a certain time (lock-up time) is required until the operation of the PLL circuit mounted on the clock signal generation circuit is stabilized, so that the test is started after the lock-up time has elapsed.

As a device for generating such a clock signal, for example, there is a microcomputer disclosed in Japanese Patent Application Laid-Open No. 9-237261. The microcomputer includes a switching circuit that switches between an output of an oscillation circuit and an output of a PLL circuit, a conversion circuit that converts a test mode setting voltage, and a holding circuit that holds an output of the conversion circuit and switches an output of the switching circuit. When a test clock having the same frequency as the system clock is applied together with the test mode setting voltage, the test clock is output.

[0012]

However, as described above, when an internal clock signal is generated from an external clock signal supplied from an externally connected tester, the level of the external clock signal is 5 V. It is necessary to supply an external clock signal via the level shifter (see FIG. 8B). With this level shifter,
The signal level is reduced from 5V to 3V.

In other words, the external clock signal has a high signal level of 5 V, and if it is input as it is, there is a risk of deterioration in characteristics, heat generation and disconnection of wiring, etc., so that the external clock signal must be supplied each time. , Signal level 3V
I had to connect a level shifter to lower the level.

In the conventional microcomputer, since the power supply voltage supplied from the outside and the power supply voltage of the internal circuit are the same, it is only necessary to provide a level shifter. However, the conventional level shifter 7 reduces the power supply voltage of the 5 V system used in the external circuit to 3 V, which is the power supply voltage supplied to the microcomputer, and is not applied to a recent high-speed microcomputer. Not considered. That is, it is assumed that the signal output from the tester has an amplitude of 5 V, and the level of the signal is adjusted by the level shifter 7 to an amplitude corresponding to the power supply voltage of the microcomputer of 3 V. At this time, since the substrate potential of the P-channel transistor of the protection circuit 24 connected to the external input terminal X1 is biased to the power supply voltage of 2 V, when the signal having the amplitude of 3 V is directly input to the amplifier 3, the drain becomes forward. Become bias, raise the substrate or well potential,
A new problem arises in that the microcomputer does not operate normally.

Further, since the PLL circuit requires a lock-up time, the PLL circuit may not respond to the supplied external clock signal.
It takes time for the circuits to synchronize, which increases the test time.

In the microcomputer, an external clock signal is input without passing through a PLL circuit, and a lock-up time is not required, but an external level shifter needs to be added.

It is an object of the present invention to provide a clock signal generating circuit having an internal power supply voltage lower than an externally supplied power supply voltage, in a product test, there is no restriction on the signal level of the external clock signal, Is to provide a clock signal generation system that can reduce the time.

[0018]

To achieve the above object, according to an aspect of the clock signal generation system according to the present invention, first
A circuit that operates with a voltage, and a second voltage that is lower than the first voltage.
And a circuit operating at pressure, and first and second external input terminals crystal oscillator is connected, said first and second external input
Terminals are input and output terminals, and operate at the second voltage.
An internal clock oscillator circuit, the first voltage and a ground potential
A third external input terminal for inputting an external clock signal having an amplitude of
Adjusting means for adjusting the amplitude between the voltage and the ground potential;
Internal oscillation clock generated by the internal clock oscillation circuit
Signal and one of the external clock signals
Selecting means for using an internal clock signal .

With the above configuration, the clock signal generation system can include the first and second external input terminals to which the crystal oscillator is connected, the first voltage and the external clock signal having the amplitude of the ground potential. have a third external input terminal for inputting the
And an internal clock operating at a second voltage lower than the first voltage.
The internal oscillation clock signal generated by the
Adjustment to the amplitude between the second voltage and the ground potential by the adjusting means
One of the external clock signals thus selected is selected as an internal clock signal .

In this way, when testing the product, the third external
The input signal level of the external clock signal input from the input terminal is adjusted by the adjusting means and adjusted to the signal level of the internal clock signal, so that the signal level of the external clock signal is not restricted, and the external clock signal is transmitted through the PLL circuit. The test time can be reduced by inputting the external clock signal without using the external clock signal.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a clock signal generation system according to an embodiment of the present invention. As shown in FIG. 1, the clock signal generation system 10 includes an amplifier circuit (A
mp) 11, feedback circuit 12, waveform shaping circuit 1
3, a PLL circuit 14, a level shifter 15, a clock signal detection circuit 16, and a NOR gate circuit 17.

The clock signal generation system 10 is built in a microcomputer mainly composed of a microprocessor which is, for example, a one-chip LSI 18,
The output from the NOR gate circuit 17 is input to the clock driver circuit 19.

The input and output sides of the amplifier circuit 11 are connected to a first external input terminal X1 and a second external input terminal X2, respectively.
, And the input side of the level shifter 15 is connected to the third external input terminal X3. Both external input terminals X1,
A crystal oscillator Xtal is connected to X2, an external clock signal a is input from a tester (not shown) to an external input terminal X3, or an external clock signal is output from a clock generation circuit (not shown) of another system. a is supplied.

A stop signal b is input from a stop signal input terminal S to an oscillation circuit including an amplifier circuit 11 and a feedback circuit 12 connected in parallel to the amplifier circuit 11. The stop signal b is a signal for stopping the operation of the transmission circuit, and the power consumption of the microcomputer in the standby state can be reduced by stopping the supply of the clock signal by stopping the oscillation circuit. .

Since the crystal oscillator Xtal is usually difficult to obtain a high oscillation frequency, the oscillation frequency is multiplied by using the PLL circuit 14 to be used as an internal clock signal.

Input signals from the external input terminals X1 and X2 are input from the amplifier circuit 11 to the NOR gate circuit 17 via the waveform shaping circuit 13 and the PLL circuit 14. The input signal from the external input terminal X3 is output from the level shifter 15
Input to the R gate circuit 17 and at the same time,
Is input to the PLL circuit 14 as the stop signal c via the clock signal detection circuit 16. The stop signal c is a clock oscillation stop signal for preventing the PLL circuit 14 transmitting at the free-running frequency from outputting a clock signal even when there is no input.

That is, the signal generated by the clock signal generation system 10 based on the output signal d of the oscillator using the crystal oscillator Xtal or the external clock signal a is
The signal can be switched by the NOR gate circuit 17 and input to the clock driver circuit 19 as the internal clock signal e. At this time, the external clock signal a is directly input to the NOR gate circuit 17 without passing through the PLL circuit 14.

FIG. 2 shows a specific example of the amplifier circuit of FIG.
(A) is an inverter type circuit diagram, (b) is a NOR gate type circuit diagram, and (c) is a clocked inverter type circuit diagram. As shown in FIG.
For example, an inverter type, a NOR gate type, or a clocked inverter type is used.

The inverter type has a power supply voltage terminal Vdd
N-channel type M connected in series between
An OS (hereinafter abbreviated as nMOS) transistor N1 and a p-channel MOS (hereinafter abbreviated as pMOS) transistor P1. Each gate is connected to the external input terminal X1, and the drain connection point is connected to the external input terminal X2, respectively (see (a)).

The NOR gate type has a power supply voltage terminal Vd
two pMOSs connected in series between d and the ground terminal
It comprises transistors P1, P2, one nMOS transistor N1, and an nMOS transistor N2 connected in parallel to the nMOS transistor N1.

The gates of the pMOS transistor P1 and the nMOS transistor N1 are connected to the external input terminal X1 by pM
The gates of the OS transistor P2 and the nMOS transistor N2 are connected to the stop signal input terminal S, and the drain connection points of the pMOS transistor P2 and the nMOS transistors N1 and N2 are connected to the external input terminal X2 (see (b)). ).

The clocked inverter type comprises two pMOS transistors P1 and P2 and two nMOS transistors N1 and N2 connected in series between a power supply voltage terminal Vdd and a ground terminal.

The gate of the pMOS transistor P1 is directly connected, and the gate of the nMOS transistor N2 is connected to the inverter I.
, The gates of the pMOS transistor P2 and the nMOS transistor N1 are connected to the external input terminal X1, and the drain connection point of the pMOS transistor P2 and the nMOS transistor N1 is connected to the external input terminal X2. , Respectively (see (c)).

FIGS. 3A and 3B show a specific example of the feedback circuit shown in FIG. 1, wherein FIG. 3A is a circuit diagram of a resistor type, and FIG. 3B is a circuit diagram of a transfer type. As shown in FIG. 3, for example, a resistance type or a transfer type is used for the feedback circuit 12, and the potential of the output terminal X2 is almost half of the power supply voltage Vdd or about the same as the threshold value of the inverter or the like constituting the amplifier circuit 11. So that

The resistance type includes two external input terminals X1, X2
A resistor R is connected between them (see (a)).

The transfer type has two external input terminals X
1 and X2, a pMOS transistor P connected in parallel
1 and an nMOS transistor N1. The gate of the pMOS transistor P1 is directly connected to the nMOS transistor N
The gates 1 are both connected to a stop signal input terminal S via an inverter I (see (b)). The transistors P1 and N1 forming the transfer gate
It is desirable that the current driving capability of the transistor formed by the amplifier circuit 11 be smaller by one digit or more.

FIGS. 4A and 4B show a specific example of the waveform shaping circuit of FIG. 1, wherein FIG. 4A is an inverter type circuit diagram, and FIG. 4B is a Schmitt type circuit diagram. As shown in FIG. 4, for the waveform shaping circuit 13, for example, an inverter type or a Schmitt type is used.

The inverter type has a power supply voltage terminal Vdd
And a pMOS transistor P1 and an nMOS transistor N1, and a pMOS transistor P2 and an nMOS transistor N2, which are connected in series between the power supply and the ground terminal.

The gates of the pMOS transistor P1 and the nMOS transistor N1 are connected to the external input terminal X2, and the drain connection points thereof are the pMOS transistors P2 and n.
The gate of the MOS transistor N2 is connected to each gate, and the drain connection point of the pMOS transistor P2 and the nMOS transistor N2 is connected to the output terminal X0 of the waveform shaping circuit 13 (see (a)).

The Schmidt type has a power supply voltage terminal Vdd
Between two pMOS transistors P1 and P2 and two nMOS transistors N1 and N2 connected in series between the power supply voltage terminal Vdd and the drain-source connection point of the two pMOS transistors P1 and P2. , A nMOS transistor N3 connected between the source / drain connection point of the nMOS transistors N1 and N2 and the ground terminal, and a series connection between the power supply voltage terminal Vdd and the ground terminal. pMO
It comprises an S transistor P4 and an nMOS transistor N4.

The gates of the pMOS transistors P1 and P2 and the nMOS transistors N1 and N2 are connected to the external input terminal X2, and the source / drain connection point of the pMOS transistor P2 and the nMOS transistor N1 is connected to the pMOS transistor P4 and the nMOS transistor N4. Each is connected to a gate. a gate of each of the pMOS transistor P3 and the nMOS transistor N3;
The source / drain connection points of the OS transistor P4 and the nMOS transistor N4 are both connected to the output terminal X0 of the waveform shaping circuit 13 (see (b)).

FIGS. 5A and 5B show a specific example of the level shifter of FIG. 1, wherein FIG. 5A is an inverter type circuit diagram, and FIG. 5B is a Schmitt type circuit diagram. As shown in FIG. 5, as the level shifter 15, for example, an inverter type or a Schmitt type is used.

The inverter type has a power supply voltage terminal Vdd
And a pMOS transistor P1 and an nMOS transistor N1, and a pMOS transistor P2 and an nMOS transistor N2, which are connected in series between the power supply and the ground terminal.

The gates of the pMOS transistor P1 and the nMOS transistor N1 are connected to the input terminal in of the level shifter 15 connected to the external input terminal X3, and the drain connection point is connected to the gates of the pMOS transistor P2 and the nMOS transistor N2, respectively. The drain connection point between the pMOS transistor P2 and the nMOS transistor N2 is connected to the output terminal out of the level shifter 15 (see (a)).

The pMOS transistor P1 and the nMOS transistor N1 correspond to a 5V high voltage input voltage,
A high voltage transistor is used, and a pMOS transistor P
As the 2 and nMOS transistors N2, low voltage transistors are used corresponding to a low voltage input voltage of 3V system. The high-voltage transistor and the low-voltage transistor are distinguished by a difference in the breakdown voltage between the drain oxide film and the gate oxide film, and the high-voltage transistor has a higher breakdown voltage.

The Schmidt type has a power supply voltage terminal Vdd
Between two pMOS transistors P1 and P2 and two nMOS transistors N1 and N2 connected in series between the power supply voltage terminal Vdd and the drain-source connection point of the two pMOS transistors P1 and P2. , And an nMOS transistor N3 connected between the source / drain connection point of the nMOS transistors N1 and N2 and the ground terminal.

By setting the power supply voltage of the level shifter 15 to a low voltage system, the input from the external input terminal X3 becomes zero.
Even if the voltage is within 5V, there is no deterioration of the characteristics,
Ｖ3V.

The gates of the pMOS transistors P1 and P2 and the nMOS transistors N1 and N2 are connected to the input terminal in of the level shifter 15, and the gates of the pMOS transistor P3 and the nMOS transistor N3 are directly connected to the pMOS transistor P2 and the nMOS transistor. The source / drain connection points of N1 are both connected to the output terminal out of the level shifter 15 via the inverter I (see (b)).

A high voltage transistor is used for both pMOS transistors P1 and P2 and both nMOS transistors N1 and N2 corresponding to a high voltage input voltage of 5V.
The S transistor P3 and the nMOS transistor N3 are
A low-voltage transistor is used corresponding to a low-voltage input voltage of a 3 V system.

FIGS. 6A and 6B illustrate the clock signal detection circuit of FIG. 1. FIG. 6A is a circuit diagram showing a specific example, and FIG. 6B is an output waveform diagram. As shown in FIG. 6, the clock signal detection circuit 1
6 is a pMOS transistor P1 and an nMOS transistor N1, and a pMOS transistor P2 and an nMOS connected in series between the power supply voltage terminal Vdd and the ground terminal.
A pMOS transistor P
1, a capacitor C is connected between the source / drain connection point of the nMOS transistor N1 and the ground terminal.

The gates of the pMOS transistor P1 and the nMOS transistor N1 are connected to the input terminal in of the clock signal detection circuit 16 connected to the output terminal out of the level shifter 15, and the drain connection point is connected to the gates of the pMOS transistor P2 and the nMOS transistor N2. Are connected respectively to the pMOS transistor P2 and the nMOS
The drain connection point of the transistor N2 is connected to the output terminal out of the clock signal detection circuit 16 ((a)
reference).

Here, the pMOS transistor P1 and nM
When the transistor sizes GmP1 and GmN1 of the OS transistor N1 satisfy GmP1 <GmN1, the input voltage from the external input terminal X3, the voltage V1 at the source / drain connection point of the clock signal detection circuit 16, and the output from the output terminal out The voltage is as shown in FIG. Note that the threshold value f is a threshold value set by an inverter composed of the pMOS transistor P2 and the nMOS transistor N2.

FIG. 7 is a circuit diagram showing a specific example of the clock signal generation system of FIG. As shown in FIG. 7, the clock signal generation system 20 is of an inverter type (FIG. 2).
Amplifying circuit 11, resistance type (see FIG. 3) feedback circuit 12, waveform shaping circuit 21, PLL circuit 1.
4, level shifter 22, clock signal detection circuit 16, N
In addition to the OR gate circuit 23, the protection circuits 24, 25, 2
6.

The waveform shaping circuit 21 has one of the pMOS transistors P1 and n of the inverter type (see FIG. 4).
The MOS transistor N1 has a gate connected to the amplifier circuit 11, a drain connection point connected to the PLL circuit 14,
Each is connected.

The level shifter 22 has one of the pMOS transistors P2 and n of the inverter type (see FIG. 5).
Each gate is connected to the protection circuit 26, and its drain connection point is connected to the clock signal detection circuit 16 and the NOR gate circuit 23, respectively.

The NOR gate circuit 23 includes two p-channel transistors connected in series between the internal power supply voltage terminal Vdd and the ground terminal.
It comprises MOS transistors P1, P2, one nMOS transistor N1, and an nMOS transistor N2 connected in parallel to the nMOS transistor N1.

The gates of the pMOS transistor P1 and the nMOS transistor N1 are connected to the PLL circuit 14 by pMO.
The gates of the S transistor P2 and the nMOS transistor N2 are connected to the level shifter 22 by the pMOS transistor P2.
2 and the drain connection point of the nMOS transistors N1 and N2 are connected to output terminals, respectively. Via this output terminal, the output of the clock signal generation system 20 is input as an internal clock signal e to a clock driver circuit (not shown).

Each of the protection circuits 24, 25 and 26 includes a p-type power supply connected in series between an internal power supply voltage terminal Vdd and a ground terminal.
MOS transistor P1 and nMOS transistor N1
The gate of the pMOS transistor P1 is connected to the internal power supply voltage terminal Vdd, and the gate of the nMOS transistor N1 is connected to the ground terminal. The pMOS transistor P1 and the nMOS transistor N1 of the protection circuit 26 use high-voltage transistors corresponding to a high-voltage input voltage of 5 V or 3 V, and
The well potential or substrate potential of the pMOS transistor is
It is necessary to set a voltage higher than the amplitude of the external clock.
For example, if the amplitude of the external clock is 3 V, 3 V is supplied to Vdd2, and if the amplitude is 5 V, Vdd2 is set to 5 V.

The external input terminal X1 is connected to the pM
The input terminal of the amplifier circuit 11 is connected to the input terminal of the amplifier circuit 11 via the drain connection point between the OS transistor P1 and the nMOS transistor N1, and the output terminal of the amplifier circuit 11 is similarly connected to the external input terminal X2 via the drain connection point of the protection circuit 25. Connected to terminal. Similarly, the external input terminal X3 is connected to the protection circuit 2
6 is connected to each gate of the level shifter 22 via the drain connection point.

In the clock signal generation system 20 having the above configuration, when using the oscillation signal from the crystal oscillator Xtal, the external input terminal X3 is set to a low level, and the crystal oscillator is connected between the external input terminals X1 and X2. Child X
Connect tal. Thus, the oscillation signal from the crystal unit Xtal is input to the clock driver circuit.
On the other hand, when using an external clock signal, the external input terminal X1 is set to low level, and the external clock signal a is input to the external input terminal X3. Thus, the external clock signal a is input to the clock driver circuit.

As described above, according to the present invention, the external input terminals X 1 and X 1 to which the crystal unit Xtal for the oscillation circuit is connected are connected.
Apart from X2, an independent external input terminal X3 is provided. This external input terminal X3 is provided with a level shifter built in the clock signal generation system 20, and
The protection circuit 26 does not leak due to the voltage of the external clock signal, and is not connected to the PLL circuit 14.

Thus, the level of the signal input from the external input terminal X3 can be determined independently of the oscillation amplitude of the crystal resonator Xtal. That is, the external input terminal X
Since the level of a signal supplied from the outside via the line 3 can be freely set, the drive voltage can be changed even if the input / output (I / O) section has a voltage configuration different from that of the 3V system and the 2V system in the 5V system. In addition, the signal level of the external clock signal a can be liberalized, and there is no need to externally connect a level shifter.

In the test, a high-speed clock signal input from the external input terminal X3 can be directly input to the clock driver circuit without passing through the PLL circuit 14, so that the lock-up time of the PLL circuit 14 waits. It is possible to speed up the test by shortening the test time.

[0065]

As described above, according to the present invention,
The clock signal generation system includes first and second external input terminals to which a crystal oscillator is connected, and a first voltage and a ground potential.
A third external input terminal for inputting an external clock signal having a width, and operating at a second voltage lower than the first voltage
Internal oscillation clock signal generated by the internal clock oscillation circuit
Signal between the second voltage and the ground potential by the adjusting means.
Select one of the width-adjusted external clock signals
Since the internal clock signal is used as an internal clock signal , the input signal level of the external clock signal input from the third external input terminal is adjusted by the adjusting unit during the product test, and the external clock signal is adjusted to the signal level of the internal clock signal. There is no restriction on the signal level of the external clock signal, and the test time can be reduced by inputting the external clock signal without passing through the PLL circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock signal generation system according to an embodiment of the present invention.

2A and 2B show a specific example of the amplifier circuit of FIG. 1, wherein FIG. 2A is an inverter type circuit diagram, FIG. 2B is a NAND gate type circuit diagram, and FIG. 2C is a clocked inverter type circuit diagram.

FIG. 3 shows a specific example of the feedback circuit of FIG. 1;
(A) is a circuit diagram of a resistance type, and (b) is a circuit diagram of a transfer type.

4A and 4B show a specific example of the waveform shaping circuit of FIG. 1, wherein FIG. 4A is an inverter type circuit diagram, and FIG. 4B is a Schmitt type circuit diagram.

5A and 5B show a specific example of the level shifter of FIG. 1, wherein FIG. 5A is an inverter type circuit diagram, and FIG. 5B is a Schmitt type circuit diagram.

FIG. 6 illustrates the clock signal detection circuit of FIG. 1;
Is a circuit diagram showing a specific example, and (b) is an output waveform diagram.

FIG. 7 is a circuit diagram showing a specific example of the clock signal generation system of FIG. 1;

8A and 8B show a conventional clock signal generation circuit, in which FIG. 8A is a block diagram when a crystal oscillator is used, and FIG. 8B is a block diagram when an external clock signal is used.

[Explanation of symbols]

 10, 20 clock signal generation system 11 amplifier circuit 12 feedback circuit 13, 21 waveform shaping circuit 14 PLL circuit 15, 22 level shifter 16 clock signal detection circuit 17, 23 NOR gate circuit 18 LSI 19 clock driver circuit 24, 25, 26 protection circuit C capacitor S stop signal input terminal N1, N2, N3, N4 nMOS transistor P1, P2, P3, P4 pMOS transistor R resistance Vdd power supply voltage terminal X1, X2, X3 external input terminal a external clock signal b, c stop signal d output Signal e Internal clock signal

Claims (10)

(57) [Claims] A circuit that operates at a first voltage; and a circuit that operates at the first voltage.
A circuit that operates at a second voltage lower than the voltage, a first and a second external input terminal to which a crystal oscillator is connected, and an input and an output terminal that connect the first and the second external input terminal to the first and second external input terminals.
And an internal clock oscillation circuit that operates at the second voltage
When a third external input terminal for inputting an external clock signal having an amplitude of said first voltage and a ground potential, the amplitude of the second voltage of the external clock signal and the ground electrostatic
Adjusting means for adjusting the amplitude to a value between the internal clock oscillation circuit and the internal oscillation clock generated by the internal clock oscillation circuit.
Clock signal and one of the external clock signals
A clock signal generation system comprising: a selection unit for setting an internal clock signal . 2. The clock signal generating system according to claim 1, wherein said adjusting means is a level shifter for adjusting a signal level of an external clock signal to a signal level of said internal clock signal. 3. The clock signal generation system according to claim 1, wherein the third connection terminal inputs the external clock signal without passing through a PLL circuit. 4. An input according to claim 1, wherein an input from said first and second external input terminals and an input from said third external input terminal are switched by a signal level of each terminal. A clock signal generation system according to any one of claims 1 to 3. 5. The switching between the input from the first and second external input terminals and the input from the third external input terminal is performed by a NAND gate that obtains a gate output corresponding to the signal level of the internal clock signal. The clock signal generation system according to claim 4, wherein the clock signal is generated. 6. A clock signal stopping means for receiving an output signal from said level shifter and stopping an output from a PLL circuit to which an oscillation signal is inputted. Clock signal generation system. 7. The clock signal generation system according to claim 1, wherein input signals from the first, second, and third external input terminals are input via a protection circuit. . 8. The clock signal generation system according to claim 7, wherein the protection circuit for the third connection terminal is formed by a high voltage transistor for a high voltage power supply. 9. A circuit operable at a first voltage, and a circuit operating at the first voltage.
A first and second external input terminal to which a crystal oscillator is connected, the first and second external input terminals being independent of the first and second external input terminals .
Input external clock signal with voltage and ground potential amplitude
A third external input terminal for causing the first and second external input terminals to be input and output terminals;
And the second consisting of the amplifier circuit and the feedback circuit
An internal clock oscillation circuit that operates with a voltage, a waveform shaping circuit that receives an output signal from the internal clock oscillation circuit, a PLL circuit that receives an output signal from the waveform shaping circuit, and a connection to the third external input terminal And the external clock signal
Signal amplitude to the amplitude between the second voltage and ground potential.
A level shifter to be adjusted, and an output signal from the level shifter,
A clock signal detection circuit that outputs a stop signal to a circuit; and an output signal from the PLL circuit and the clock signal detection circuit that are input and generated by the internal clock oscillation circuit.
The internal oscillation clock signal and the external clock signal
A NOR gate circuit for selecting one of the clock signals, wherein an output signal from the NOR gate circuit is input to a clock driver circuit as an internal clock signal. 10. The clock signal generation system according to claim 1, wherein the clock signal generation system is built in a one-chip LSI.