JP2006217162A - Ring oscillator circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a ring oscillator circuit capable of finely adjusting an oscillation period with a shorter variable width than before. <P>SOLUTION: The ring oscillator is constituted by connecting a plurality of logic gates in a ring shape and outputs a clock of designated frequency from one of the plurality of logic gates, and one of the plurality of logic gates is a switching circuit with two or more two inputs. The output signal of the switching circuit rises according to a 1st signal inputted through a 1st path and falls according to a 2nd signal which is inputted through a 2nd path and has the same polarity with the 1st signal, but differs in propagation delay time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a ring oscillator circuit used in a voltage controlled oscillator (VCO) of a PLL (phase locked loop), for example.

  The ring oscillator circuit outputs a clock with a predetermined frequency. For example, one NAND gate or NOR gate as a control circuit for controlling stop or oscillation of a clock and an even number of inverters as a delay circuit are provided. Connected in a ring shape. In the PLL VCO, a variable speed inverter whose speed (delay time) changes according to a control voltage is used as an inverter.

  Hereinafter, the problem of the conventional ring oscillator circuit will be described by taking as an example a case of a ring oscillator circuit composed of a 2-input NAND gate as a control circuit and 4-stage and 6-stage inverters as a delay circuit.

  The ring oscillator circuit 18 shown in FIG. 6 includes a NAND gate i0 serving as a control circuit and four inverters i1 to i4 serving as delay circuits. The enable signal Enable and the output signal of the inverter i4 are input to the NAND gate i0. The output signal of the NAND gate i0 is output as the clock OSCout and is input to the inverter i1, and the output signals of the inverters i1 to i3 are sequentially input to the inverters i2 to i4 in the next stage.

  In the case of the ring oscillator circuit 18, as shown in the timing chart of FIG. 7, the clock OSCout stops when Enable = 0 and oscillates when Enable = 1. When Enable = 0, the output signals of the logic gates i0 to i4 are as follows.

i0 = 1
i1 = 0
i2 = 1
i3 = 0
i4 = 1

  That is, the clock OSCout (= i0) is stopped at 1.

  On the other hand, when Enable changes from 0 to 1, as shown in the timing chart of FIG. 7, the output signals of the logic gates i0 to i4 sequentially change as follows.

i0: 1 → 0
i1: 0 → 1
i2: 1 → 0
i3: 0 → 1
i4: 1 → 0
i0: 0 → 1
i1: 1 → 0
i2: 0 → 1
i3: 1 → 0
i4: 0 → 1

  The above is one cycle, and the above cycle is repeated thereafter. That is, the oscillation period of the clock OSCout (= delay time required for one period) is NAND gate delay time × 2 stages + inverter delay time × 8 stages. Here, assuming that the delay time of the NAND gate is smaller than the delay time of the inverter and can be ignored, the oscillation period of the clock OSCout can be simply regarded as the delay time of the inverter × 8 stages. .

  Next, the ring oscillator circuit 20 shown in FIG. 8 is obtained by adding inverters i5 and i6 to the number of inverter stages in the ring oscillator circuit 18 shown in FIG. The output signals of the inverters i4 and i5 are sequentially input to the next-stage inverters i5 and i6, and the enable signal Enable and the output signal of the inverter i6 are input to the NAND gate i0. The operation is shown in the timing chart of FIG.

  As in the case of the ring oscillator circuit 18 shown in FIG. 6, the oscillation period of the clock OSCout output from the ring oscillator circuit 20 shown in FIG. 8 can be simply regarded as the inverter delay time × 12 stages. That is, it can be seen that in the ring oscillator circuit 20 having six stages of inverters, the oscillation period of the clock OSCout rapidly increases by 1.5 times compared to the ring oscillator circuit 18 having four stages of inverters.

  As described above, when using a ring oscillator circuit, such as changing the number of inverter stages from 4 to 6, it is common to change the number of inverter stages to achieve various oscillation frequencies. This is the method that is performed.

  For example, Patent Document 1 shows an example in which the oscillation frequency is changed in two ways by switching between seven inverters and a total of 11 inverters including four inverters. Patent Document 2 shows an example in which a wide range of oscillation frequencies is realized by switching the number of buffer stages in six ways. Further, Patent Document 3 shows a more specific circuit example for a method of switching the number of inverter stages.

  In the clock generation circuit disclosed in Patent Document 2, there is shown a diagram in which the number of stages can be switched in units of one buffer, but one buffer has two inverters connected in series. Since it is realized by connecting, it is the same as adjusting the delay time by adding an even number of inverters as a unit, like the ring oscillator circuit composed of the above four and six inverters. .

JP-A-3-217717 JP 63-2111919 A Japanese Patent No. 2933286

  As described above, in the ring oscillator circuits 18 and 20 using the NAND gate i0 as the control circuit, when the number of inverter stages is changed, it is necessary to change the number of inverter stages. This is because if the number of inverter stages is an odd number, the number of inversions of the signal in the entire ring oscillator circuit is an even number, and the clock OSCout does not oscillate. For this reason, when changing the number of inverter stages, it is necessary to change from 4 stages to 6 stages instead of 5 stages.

  Next, consider a case in which a PLL using a ring oscillator circuit composed of a variable speed inverter is configured as the VCO. In order to cope with various oscillation frequencies, the number of stages of the ring oscillator circuit is switched, but only discrete oscillation frequencies can be realized only by switching the number of stages. For this reason, the oscillation frequency between these discrete oscillation frequencies must be dealt with by adjusting the speed of the variable speed inverter according to the control voltage.

  As described above, the number of inverter stages must be changed to an even number, and when the number of inverter stages is changed from 4 to 6 as described above, the oscillation period increases rapidly by about 1.5 times. To do. Therefore, in a PLL using a VCO composed of this ring oscillator circuit, in order to cope with the frequency between them, it is necessary to design the delay time of each variable speed inverter to be variable up to about 1.5 times. There is.

  On the other hand, paying attention to PLL stability (such as jitter), an excessive variable width (variable sensitivity) of the VCO adversely affects the characteristics. When the variable width is widened, the variable sensitivity is increased, which is one of the causes of increasing jitter. That is, the fact that the oscillation cycle of the four-stage and six-stage ring oscillator circuits of the aforementioned inverter is about 1.5 times apart is a great demerit in terms of characteristics in using the ring oscillator circuit as a VCO.

  An object of the present invention is to provide a ring oscillator circuit that can solve the problems based on the prior art and finely adjust the oscillation period with a finer variable width than the conventional one.

In order to achieve the above object, the present invention is a ring oscillator circuit configured by connecting a plurality of logic gates in a ring shape and outputting a clock having a predetermined frequency from one of the plurality of logic gates. ,
One of the plurality of logic gates is a switching circuit having two or more inputs, and an output signal of the switching circuit rises in response to a first signal input through a first path, The present invention provides a ring oscillator circuit characterized by falling in response to a second signal that is input via a path and has the same polarity as the first signal but different propagation delay time.

  Here, the ring oscillator circuit is used in a voltage-controlled oscillator of a PLL, and the logic gate may change its delay time according to a control voltage input to the voltage-controlled oscillator. preferable.

  In the ring oscillator circuit of the present invention, the number of inverter stages can be equivalently changed in units of one stage, and the clock oscillation cycle can be finely adjusted with a finer variable width than in the prior art. Therefore, in the PLL using the voltage controlled oscillator to which the ring oscillator circuit of the present invention is applied, the speed variable range of the speed variable inverter can be narrower than that of the conventional one, so that the stability of the PLL can be improved, jitter, etc. The characteristics can be improved.

  Hereinafter, a ring oscillator circuit of the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

  FIG. 1 is a circuit diagram of an embodiment showing a configuration of a ring oscillator circuit of the present invention. The ring oscillator circuit 10 shown in the figure is configured by connecting a plurality of logic gates in a ring shape, and outputs a clock OSCout having a predetermined frequency from one of the logic gates, and serves as a control circuit / switching circuit 3 An input NAND gate i0 and six inverters i1 to i6 serving as delay circuits are provided.

  Here, the enable signal Enable and the output signals of the inverters i4 and i6 are input to the NAND gate i0. The output signal of the NAND gate i0 is output as the clock OSCout and is input to the inverter i1, and the output signals of the inverters i1 to i5 are sequentially input to the next-stage inverters i2 to i6.

  Also in the case of the ring oscillator circuit 10, as shown in the timing chart of FIG. 2, the clock OSCout stops when Enable = 0 and oscillates when Enable = 1. When Enable = 0, the output signals of the logic gates i0 to i6 are as follows.

i0 = 1
i1 = 0
i2 = 1
i3 = 0
i4 = 1
i5 = 0
i6 = 1

  That is, the clock OSCout (= i0) is stopped at 1.

  When Enable changes from 0 to 1, as shown in the timing chart of FIG. 2, the output signals of the logic gates i0 to i6 sequentially change as follows.

i0: 1 → 0
i1: 0 → 1
i2: 1 → 0
i3: 0 → 1
i4: 1 → 0
i0: 0 → 1 ... The change in which i0 becomes 0 → 1 propagates from i4.
i1: 1 → 0
i2: 0 → 1
i3: 1 → 0
i4: 0 → 1
i5: 1 → 0
i6: 0 → 1
i0: 1 → 0 ... The change in which i0 becomes 1 → 0 propagates from i6.

  The above is one cycle, and the above cycle is repeated thereafter. That is, the oscillation period of the clock OSCout output from the ring oscillator circuit 10 is NAND gate delay time × 2 stages + inverter delay time × 10 stages. Similarly, if the delay time of the NAND gate can be ignored, the oscillation period of the clock OSCout can be simply regarded as the delay time of the inverter × 10 stages.

  Here, in the ring oscillator circuit 10, a NAND gate i0 is used as a control circuit / switching circuit. Therefore, if at least one of the three input signals Enable, i4, and i6 is 0, the output signal of the NAND gate i0 is 1. On the other hand, the output signal of the NAND gate i0 does not become 0 unless all of the output signals of the three input signals Enable, i4 and i6 become 1.

  Therefore, as described above, the propagation path when i0 becomes 0 → 1 (= OSCout rises) becomes i0 → i1 → i2 → i3 → i4 → i0, whereas i0 becomes 1 → 0. (= OSCout falls), the propagation path is i0 → i1 → i2 → i3 → i4 → i5 → i6 → i0. That is, the signal propagation path differs between when the clock OSCout rises and when it falls.

  In other words, the ring oscillator circuit 10 has the same signal propagation path as the ring oscillator circuit with four stages of inverters at the rising edge of the clock OSCout, and the signal propagation path at the falling edge of the ring oscillator circuit with six stages of inverters. It operates as the same ring oscillator circuit as the circuit. As a result, the ring oscillator circuit 10 realizes a ring oscillator circuit equivalently having five stages of inverters.

  In the conventional ring oscillator circuit, for example, the number of inverter stages can only be changed from 4 to 6, and in that case, the change in the oscillation period of the clock OSCout is about 1.5 times as described above. . On the other hand, in the case of the ring oscillator circuit 10, since a ring oscillator circuit having five stages of inverters is equivalently realized, the change in the oscillation cycle of the clock is 1 in the case where the inverter is a four stage ring oscillator circuit. Stays 25 times.

  In other words, in the ring oscillator circuit 10, the number of inverter stages can be equivalently changed in units of one stage from four stages to five stages, and the oscillation period of the clock OSCout can be finely adjusted with a finer variable width than before. Can do.

  Therefore, in the PLL using the ring oscillator circuit 10 composed of a variable speed inverter as a voltage controlled oscillator, the speed (= delay time) of the variable speed inverter is set to 1 in order to cover a continuous frequency range. It only needs to be variable up to 25 times. That is, since the speed variable range may be narrower than before, the stability of the PLL increases and characteristics such as jitter can be improved.

  The ring oscillator circuit of the present invention is not limited to the configuration of the above embodiment.

  In other words, the ring oscillator circuit of the present invention is a switching circuit in which one of a plurality of logic gates connected in a ring shape has two or more inputs, and an output signal of the switching circuit is transmitted via a first path. Any signal may be used as long as it rises in response to the first input signal and is input through the second path and falls in response to the second signal having the same polarity as the first signal but having a different propagation delay time.

  In the ring oscillator circuit 10 shown in FIG. 1, the three-input NAND gate i0 functions as a control circuit for controlling the stop or oscillation of the clock OSCout output from the ring oscillator circuit 10 by the enable signal Enable, A control circuit / switching circuit having a function as a switching circuit for switching between the first and second signals input via the first and second paths is integrally configured.

  In the ring oscillator circuit 10, a three-input NAND gate is used as a control circuit and switching circuit, but the present invention is not limited to this. For example, as in the ring oscillator circuits 12 and 14 shown in FIGS. 3 and 4, various logic gates having three or more inputs such as a two-input OR-NAND composite gate and a three-input NOR gate are used instead of the three-input NAND gate. Even if it is used, the same function can be realized.

  In the ring oscillator circuit of the present invention, the control circuit and the switching circuit may be configured by separate logic gates. The control circuit is not an essential component for the ring oscillator circuit of the present invention, and may be omitted if not necessary.

  For example, when a control circuit is not required, the ring oscillator circuit 10 shown in FIG. 1 can use a 3-input NAND gate i0 as a control circuit / switching circuit as a 2-input NAND gate as a switching circuit. In the case of the ring oscillator circuits 12 and 14 shown in FIGS. 3 and 4, the 2-input OR-NAND composite gate and the 3-input NOR gate as the control circuit / switching circuit may be used as the 2-input NOR gate as the switching circuit. it can.

  Further, when the control circuit and the switching circuit are configured by separate logic gates, for example, as in the ring oscillator circuit 16 shown in FIG. 5, the enable signal Enable and the output signal of the inverter i6 are input as the control circuit 2 The same function can also be realized by using the input NAND gate i0 and using the 2-input NAND gate i5 to which the output signals of the inverters i2 and i4 are input as the switching circuit.

  That is, the first and second signals are input to the switching circuit. The first and second signals have the same polarity as the output signal of the first logic gate immediately preceding (immediately before) the switching circuit and the output signal of the first logic gate, and have different propagation delay times. This is the output signal of the second logic gate one stage or more before the one logic gate.

  Note that three or more signals can be input to the switching circuit. For example, in the ring oscillator circuit 10, it is also possible to input the output signal of the inverter i2 to the NAND gate i0 as the third signal. However, even if three or more signals are input to the switching circuit, the signal (i4) that changes between the signal (i2) that changes first and the signal (i6) that changes last will change the clock OSCout. Does not contribute. For this reason, it is necessary and sufficient to input only two signals, a first changing signal and a last changing signal, to the switching circuit.

  In the ring oscillator circuit 10, a 3-input NAND gate is used as a control circuit / switching circuit and an even-numbered inverter is used as a delay circuit, but this is not limited. For example, the NAND gate i0 and the inverter i1 in the next stage (immediately after) can be combined into an AND gate. In this case, the number of inverter stages is an odd number. It is also possible to configure a continuous two-stage inverter with a buffer.

  Further, the ring oscillator circuit of the present invention is not limited to the number of stages of inverters constituting two paths being four and six, and can be any even number. For example, when the number of stages of inverters of two paths is 8 and 10, the ring oscillator circuit having 9 stages of inverters can be equivalently realized. Conventionally, when the number of inverter stages is changed from 8 to 10, the change in the oscillation period of the clock OSCout is about 1.25 times, whereas in the present invention, the change is reduced to about 1.125 times. Is done.

  In the ring oscillator circuit 10, the difference in the number of stages of the inverters in the first and second paths is an even number in order to make the first and second signals have the same polarity. However, as the difference in the number of inverter stages between the two increases, the rate at which the duty of the clock OSCout (ratio between the high level pulse width and the low level pulse width) collapses also increases. For this reason, the difference in the number of inverter stages between the two paths is most preferably minimized (in the case of the ring oscillator circuit 10, the inverter has two stages).

  The present invention is not limited to a ring oscillator circuit configured by a variable speed inverter used in a PLL VCO or the like, and can be applied to various ring oscillator circuits configured by a normal inverter.

The present invention is basically as described above.
The ring oscillator circuit of the present invention has been described in detail above. However, the present invention is not limited to the above embodiment, and various modifications and changes may be made without departing from the spirit of the present invention. is there.

It is a circuit diagram of one embodiment showing composition of a ring oscillator circuit of the present invention. 2 is a timing chart illustrating an operation of the ring oscillator circuit illustrated in FIG. 1. It is a circuit diagram showing another structure of the ring oscillator circuit of this invention. It is a circuit diagram showing another structure of the ring oscillator circuit of this invention. It is a circuit diagram showing another structure of the ring oscillator circuit of this invention. It is an example circuit diagram showing the structure of the conventional ring oscillator circuit. 7 is a timing chart illustrating an operation of the ring oscillator circuit illustrated in FIG. 6. It is a circuit diagram of another example showing the structure of the conventional ring oscillator circuit. 9 is a timing chart illustrating the operation of the ring oscillator circuit illustrated in FIG. 8.

Explanation of symbols

10, 12, 14, 16, 18, 20 Ring oscillator circuit i0-i6 Logic gate

Claims (2)

A ring oscillator circuit configured by connecting a plurality of logic gates in a ring shape and outputting a clock of a predetermined frequency from one of the plurality of logic gates;
One of the plurality of logic gates is a switching circuit having two or more inputs, and an output signal of the switching circuit rises in response to a first signal input through a first path, A ring oscillator circuit characterized by falling according to a second signal that is input via a path and has the same polarity as the first signal but a different propagation delay time.   The ring oscillator circuit is used in a voltage controlled oscillator of a PLL, and the logic gate has a delay time that changes according to a control voltage input to the voltage controlled oscillator. The ring oscillator circuit according to claim 1.

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