JPH112662A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate the measurement of delay characteristics by enabling a ring oscillator controlling oscillation and connecting a plurality of FFs to the front step and the rear step of a delay measurement circuit. SOLUTION: A terminal 102 and an input terminal 101 are set to a logical value 1 and a ring oscillator is made to oscillate with a period (x). With a start up pulse of the oscillator, the normal rotation output of the FFs 104 and 107 becomes a logical value 1 and the output of a delay measurement circuit 105 becomes a logical value 1 after a delay time (y). In the case x>y, with the next start up pulse, the normal rotation outputs of the FFs 106 and 107 respectively become logical values 1 and 0 and the reverse rotation output of the FF 106 becomes logical value 0 and oscillation terminates and an output terminal 103 becomes a logical value 1. In the case x<=y, the normal rotation output of FFs 106 and 107 become a logical value 0 and the reverse rotation output of FF 106 becomes a logical value 1 and the oscillation continues. With the next start up pulse, the normal rotation outputs of FF 106 and 107 becomes a logical value of 1 and the reverse rotation output of FF 106 becomes a logical value 0, oscillation terminates and the output terminal 103 becomes a logical value 0. From this logical value of the output terminal 103, delay selection is possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a delay time measuring function.

[0002]

2. Description of the Related Art Measurement of delay time and characteristics of a semiconductor device requires L
This is performed using an apparatus such as an SI tester.

The measurement of the delay characteristic is disclosed in
No. 176963. This will be described below with reference to FIG. 501 is a test terminal, 502 and 505 are input buffers, 503 is an inverter, 504 is an input terminal, 506 is a delay measurement circuit, 507 and 510 are 3-state buffers, 508 is an output buffer, 509 is a logic circuit, and 511 is an output terminal. Show.

In a normal state, the terminal 501 is set to a logical value "0".
Holds, the logic circuit 509 becomes effective. When testing the semiconductor device, the terminal 501 is set to the logical value “1”.
, The three-state buffer 507 is enabled, and the delay circuit 506 is enabled. At this time, the three-state buffer 51 is
0 is masked and the logic circuit 509 becomes invalid. Then, a signal having a predetermined pattern is input to the input terminal 504, and the signal is compared with a signal appearing at the output terminal 511 to determine a delay characteristic of the semiconductor device.

The above is the method for measuring the delay characteristics of a semiconductor device.

[0006]

The measurement of the delay characteristic of a semiconductor device is performed using a device such as an LSI tester of a semiconductor maker. There is a problem that a user who purchases and uses a semiconductor device cannot easily measure the delay of the semiconductor device.

Accordingly, the present invention provides a semiconductor device in which a user can easily measure delay characteristics by providing flip-flops at the front and rear stages of any combinational circuit required by the user. It is intended to provide a device.

[0008]

[Means for Solving the Problems]

(Means 1) A ring oscillator capable of controlling oscillation, a delay measuring circuit composed of an arbitrary combinational circuit, one flip-flop connected before the delay measuring circuit, and a subsequent stage of the delay measuring circuit , And a delay discriminating circuit.

(Means 2) In the means 1, a ring oscillator capable of controlling the oscillation period and oscillation, a delay measuring circuit constituted by an arbitrary combinational circuit, and one flip-flop connected to the preceding stage of the delay measuring circuit A flip-flop, two flip-flops connected downstream of the delay measuring circuit, and a delay discriminating circuit;

(Means 3) In the means 1, a delay measuring circuit comprising a ring oscillator capable of controlling the oscillation cycle and oscillation, a frequency divider, and an optional combination circuit, and connected to a stage preceding the delay measuring circuit The delay measuring circuit, two flip-flops connected downstream of the delay measuring circuit, and a delay discriminating circuit.

(Means 4) In the means 1, a delay measuring circuit composed of a ring oscillator capable of controlling the oscillation cycle and oscillation, a frequency divider, an arbitrary combinational circuit, and , One flip-flop connected before the previous selector, and two flip-flops connected after the previous selector.
It has a flop and a delay determination circuit.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing one embodiment of the means 1. First, the configuration will be described. 101 is a data input terminal, 102 is an enable terminal of the ring oscillator, and 103 is an output terminal for delay determination. 104, 1
Reference numerals 06 and 107 denote flip-flops, 108 denotes a two-input AND gate for performing a delay determination, and 105 denotes a delay measuring circuit constituted by an arbitrary combinational circuit. 109 is 3 input N
AND gates 110 to 113 constitute an inverter, and a ring oscillator whose oscillation can be controlled by these inverters.

Flip flops 104, 106, 10
It is assumed that the non-inversion output of No. 7 has a logical value “0”. The following description is given on the assumption that the arbitrary delay measuring circuit 105 operates equivalently to a buffer.

First, when the logic value of the terminal 102 is set to “1”, the ring oscillator starts oscillating at an oscillation cycle x. Next, a logical value “1” is set to the input terminal 101.
104, 10 with rising pulse of ring oscillator
7 has a logical value "1". Delay measurement circuit 10
The output of 5 becomes a logical value “1” after the delay time y. If x> y at the next rising pulse of the ring oscillator, the non-inverted outputs of the flip-flops 106 and 107 have logical values “1” and “0”, respectively. Flip
Since the inverted output of the flop 106 has the logical value “0”,
The ring oscillator stops oscillating. Since the normal output and the inverted output of the flip-flops 106 and 107 have the logical value “1”, the output terminal 103 has the logical value “1”.

If x = <y, flip flop 10
The non-inverting outputs of 6, 107 have a logical value "0". Since the inverted output of flip-flop 106 remains at logic "1", the ring oscillator continues to oscillate. At the next rising pulse of the ring oscillator, the non-inverted outputs of 106 and 107 become logical value “1”. Flip flop 10
Since the inverted output of 6 becomes the logical value “0”, the ring oscillator stops oscillating. Flip flop 106,
Since the non-inversion output and the inversion output of 107 are logic values “1” and “0”, respectively, the output terminal 103 has a logic value “0”.
Becomes Sorting can be performed by measuring the logical value appearing at the output terminal 103 by the method described above.

FIG. 2 is a circuit diagram showing an embodiment of the means 2. First, the configuration will be described. 201 is a data input terminal, 202 is an n-bit selector control input terminal (n is an arbitrary integer), 203 is an enable terminal of the ring oscillator, and 204 is a delay determination output terminal. 20
Reference numerals 5, 207, and 208 denote flip-flops, 209 denotes a two-input AND gate for performing delay determination, and 206 denotes a delay measurement circuit formed by an arbitrary combinational circuit. 210 is m
Selector of input 1 output (m is an arbitrary integer), 211
Is a 3-input NAND gate, 212 to 215 are inverters, and these constitute a ring oscillator whose oscillation cycle can be controlled.

Flip flops 205, 207, 20
It is assumed that the normal output of 8 is a logical value “0”. The following description is made on the assumption that the optional delay measuring circuit 206 operates equivalently to a buffer.

The terminal 202 is set to an arbitrary logical value. When the terminal 203 is set to the logical value “1”, the ring oscillator starts oscillating at the oscillation cycle x. Next, input terminal 2
A logical value “1” is set to 01. With the rising pulse of the ring oscillator, the non-inverted outputs of 205 and 208 have a logical value “1”. The output of the delay measurement circuit 206 becomes a logical value “1” after the delay time y. If x> y at the next rising pulse of the ring oscillator, the non-inverted outputs of the flip-flops 207 and 208 have logical values “1” and “0”, respectively. Since the inverted output of the flip-flop 207 becomes the logical value “0”, the ring oscillator stops oscillating. Flip flop 207, 20
Since the non-inverting output and the inverting output of No. 8 have the logical value “1”, the output terminal 204 has the logical value “1”.

If x = <y, flip flop 20
The normal rotation output of each of 7 and 208 has a logical value “0”.
Since the inverted output of the flip-flop 207 remains at the logical value “1”, the ring oscillator continues to oscillate. 207, 2 at the next rising pulse of the ring oscillator
The non-inversion output of 08 has the logical value “1”. Since the inverted output of the flip-flop 207 becomes the logical value “0”, the ring oscillator stops oscillating. Since the normal output and the inverted output of the flip-flops 208 and 209 are logical values “1” and “0”, respectively, the output terminal 204 has the logical value “0”.

By setting the terminal 202 to an arbitrary logical value so that the oscillation cycle of the ring oscillator becomes small, it is possible to make a detailed judgment of the delay measuring circuit.

FIG. 3 is a circuit diagram showing an embodiment of the means 3. First, the configuration will be described. 301 is a data input terminal, 302 is an n-bit selector control input terminal (n is an arbitrary integer), 303 is a ring oscillator enable terminal, 304 is an l-bit frequency division control terminal (l is an arbitrary integer), 305 is an output terminal for delay determination. 30
Reference numerals 6, 308, and 309 denote flip-flops, 310 denotes a two-input AND gate that performs delay determination, and 307 denotes a delay measurement circuit formed by an arbitrary combinational circuit. 311 is m
Input 1 output selector (m is an arbitrary integer), 312
Is a three-input NAND gate, 313 to 316 are inverters, 317 is a frequency divider, and these constitute a ring oscillator that can be divided and whose oscillation cycle can be controlled.

Flip flops 306, 308, 30
It is assumed that the forward rotation output of No. 9 has a logical value “0”. Description will be made below assuming that the optional delay measurement circuit 307 operates equivalently to a buffer.

The terminals 302 and 304 are set to arbitrary logical values. When the terminal 303 is set to the logical value “1”, the ring oscillator starts oscillating at the oscillation cycle x. Next, a logical value “1” is set to the input terminal 301. With the rising pulse of the ring oscillator, the non-inverted outputs of 306 and 309 have a logical value “1”. The output of the delay measurement circuit 307 is
The logic value becomes “1” after the delay time y. If x> y at the next rising pulse of the ring oscillator, the non-inversion outputs of the flip-flops 308 and 309 have logical values “1” and “0”, respectively. Flip flop 30
Since the inverted output of 8 becomes the logical value “0”, the ring oscillator stops oscillating. Flip flop 308,
Since the non-inversion output and the inversion output of 309 have the logical value “1”, the output terminal 305 has the logical value “1”.

If x = <y, flip flop 30
The normal output of each of 8, 309 has a logical value "0".
Since the inverted output of flip-flop 308 remains at logic "1", the ring oscillator continues to oscillate. 308, 3 at the next rising pulse of the ring oscillator
The non-inverting output of 09 has the logical value “1”. Since the inverted output of the flip-flop 308 becomes a logical value “0”, the ring oscillator stops oscillating. Since the normal output and the inverted output of the flip-flops 308 and 309 are logical values "1" and "0", respectively, the output terminal 305 has the logical value "0".

By setting the terminals 302 and 304 to arbitrary logical values and setting the oscillation cycle of the ring oscillator to be small, the setting range of the delay time of the delay measuring circuit can be widened. Determination is possible.

FIG. 4 is a circuit diagram showing one embodiment of the means 4. First, the configuration will be described. Reference numeral 401 denotes a data input terminal, 402 denotes an n-bit selector control input terminal (n is an arbitrary integer), 403 denotes a ring oscillator enable terminal, and 404 denotes an l2-bit frequency division control input terminal (l
Reference numeral 405 denotes an 11-bit selector control input terminal (11 is an arbitrary integer), and 406 denotes a delay determination output terminal. 407, 413, and 414 are flip-flops, 415 is a two-input AND gate that performs delay determination, 409, 410, and 411 are delay measurement circuits each formed of an arbitrary combinational circuit, and 408 and 412 are one-input m1 output selectors. , M1 input and 1 output selectors. (M1 is an arbitrary integer) 416 is m
2 input 1 output selector (m2 is an arbitrary integer), 4
18 is a 3-input NAND gate, 419 to 422 are inverters, 417 is a frequency divider, and these constitute a ring oscillator which can be divided and whose oscillation cycle can be controlled. In this description, three delay measuring circuits are used.

Flip flops 407, 413, 41
It is assumed that the non-inversion output of No. 4 has a logical value “0”. Arbitrary delay measurement circuits 409, 410, and 411 will be described below assuming that they operate equivalently to buffers.

The terminals 402, 404 and 405 are set to arbitrary logical values. When the terminal 403 is set to the logical value “1”, the ring oscillator starts oscillating at the oscillation period x set by the frequency divider. Next, a logical value “1” is set to the input terminal 401. With the rising pulse of the ring oscillator, the non-inverted outputs of 407 and 414 have the logical value “1”. The output of one of the delay measurement circuits 409, 410, 411 connected to the selector 408 is
The output of the selector 412 becomes a logical value "1" after the delay time y1, y2, or y3. At the next rising pulse of the divider, x> (y1, y
2, y3), the normal output of the flip-flop 413 is a logical value “1”, and the normal output of the flip-flop 414 is a logical value “0”
Becomes Since the inverted output of the flip-flop 413 becomes a logical value “0”, the ring oscillator stops oscillating. Since the normal output and the inverted output of the flip-flops 413 and 414 have the logical value “1”, the output terminal 406 has the logical value “1”.

If x = <(y1, y2, y3), the non-inverted outputs of the flip-flops 413 and 414 have the logical value "0". Since the inverted output of the flip-flop 413 remains at the logical value “1”, the ring oscillator continues to oscillate. At the next rising pulse of the ring oscillator, the non-inverting outputs of 413 and 414 become the logical value “1”.
Since the inverted output of the flip-flop 413 becomes a logical value “0”, the ring oscillator stops oscillating. Since the normal output and inverted output of the flip-flops 413 and 414 are logical values "1" and "0" respectively, the output terminal 4
06 is a logical value “0”.

By using the selector as described above, it is possible to measure a plurality of delay measuring circuits, and it is possible to make a detailed judgment even if the delay times are different.

[0031]

According to the invention described in the means 1, the flip-flops are provided before and after the delay measuring circuit, and the output of the ring oscillator is used as the clock input of the flip-flop, so that the delay time can be measured and selected. It can be carried out.

According to the invention described in the means 2, the flip-flop is provided before and after the delay measuring circuit, and the output of the ring oscillator which can change the number of stages is used as the clock input of the flip-flop, so that the delay time can be specified in detail. Measurement and sorting can be performed.

According to the invention described in the means 3, the output of the ring oscillator having a flip-flop provided before and after the delay measuring circuit and having a variable number of stages is inputted to the frequency divider, and the output of the frequency divider is outputted to the flip-flop. With this clock input, a wide range of delay time settings and detailed measurement and selection can be performed.

According to the invention described in Means 4, the front and rear of the plurality of delay measuring circuits are connected by the selector, and the front and rear of the selector are connected by the flip-flop, and the output of the ring oscillator which can change the number of stages is divided. By inputting the output of the frequency divider to the clock input of the flip-flop, the delay time measurement and selection of a plurality of delay circuits can be measured at one output terminal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor device according to Means 1 of the present invention.

FIG. 2 is a circuit diagram showing one embodiment of a semiconductor device according to means 2 of the present invention.

FIG. 3 is a circuit diagram showing one embodiment of a semiconductor device according to means 3 of the present invention.

FIG. 4 is a circuit diagram showing one embodiment of a semiconductor device according to means 4 of the present invention.

FIG. 5 is a circuit diagram showing a conventional technique.

[Explanation of symbols]

 101: Data input terminal 102: Enable terminal 103: Output terminal for delay determination 104: Flip flop 105: Delay measurement circuit 106: Flip flop 107: Flip Flop 108: 2-input AND gate 109: 3-input NAND gate 110-113: Inverter

Claims (4)

[Claims] A ring oscillator capable of controlling oscillation;
A delay measuring circuit composed of an arbitrary combinational circuit, one flip-flop connected before the delay measuring circuit, two flip-flops connected after the delay measuring circuit, and a delay discriminating circuit And a semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein a ring oscillator capable of controlling an oscillation cycle and oscillation, a delay measuring circuit constituted by an arbitrary combinational circuit, and a preceding stage of the delay measuring circuit are connected. A semiconductor device comprising: one flip-flop; two flip-flops connected downstream of the delay measurement circuit; and a delay determination circuit. 3. The semiconductor device according to claim 1, wherein: a ring oscillator capable of controlling an oscillation cycle and oscillation; a frequency divider; a delay measurement circuit comprising an arbitrary combinational circuit; A semiconductor device comprising: one flip-flop connected to a preceding stage; two flip-flops connected to a subsequent stage of the delay measuring circuit; and a delay determining circuit. 4. The semiconductor device according to claim 1, wherein a ring oscillator capable of controlling an oscillation cycle and oscillation, a frequency divider, a delay measurement circuit comprising an arbitrary combinational circuit, and said delay measurement circuit are provided. A selector connected at an arbitrary preceding stage and one flip-flop connected at the preceding stage of the previous selector.
A semiconductor device comprising: a flop; two flip-flops connected to a stage subsequent to the selector; and a delay determination circuit.