JPH05196757A - Delay time measuring circuit - Google Patents

Abstract

PURPOSE:To allow optimum designing without taking an excessive time difference margin within a semiconductor chip by highly accurately measuring difference in delay time within the chip and knowing a fluctuation rate in the semiconductor chip. CONSTITUTION:Two ring oscillator circuits 1, 2 are provided on a semiconductor chip, circuits 5, 6 for dividing respective outputs of the circuits 1, 2 are provided, and an exclusive OR circuit 7 with the outputs connected is provided. An AND gate 9 with the outputs from the divider circuits 5, 6 connected is provided, a one-shot circuit 8 with the output of the gate 9 connected is provided, and an AND gate 10 with the output of the circuit 8 is provided. The output of the AND gate 10 is connected to reset inputs of the two ring oscillator circuits 1, 2 and the two divider circuits 5, 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay time measuring circuit, and more particularly to a delay time measuring circuit in a semiconductor chip of a gate array type semiconductor integrated circuit.

[0002]

2. Description of the Related Art In the conventional delay time measuring circuit shown in FIG. 5, input buffers 501 and 502 and an AND gate 50 are provided.
4, 505, delay circuits 506 and 507, a multiplexer circuit 508, an output buffer 509, an input terminal I3, an output terminal O3, and a select terminal S5 are shown. here,
The number of inverter circuits 510 in the delay circuit 506 is different from the number of inverter circuits 511 in the delay circuit 507.

Conventionally, a delay time measuring device in a semiconductor chip has a delay circuit as shown in FIG. 5, and a select terminal S5 is used to switch the paths of a delay circuit 506 and a delay circuit 507 having different stages. Input terminal I3
And the delay time between the output terminal O3 and the delay circuit 50
6 and the delay circuit 507.
Divided by the difference in the number of stages of the inverter circuits 510 and 511 of 07,
The delay time for one inverter stage was calculated.

[0004]

Such a conventional delay time measuring circuit requires a large number of inverter stages in the delay circuits 506 and 507 in order to maintain the measurement accuracy as shown in FIG. 5, as the speed increases. Become. For example, the inverter 1
Assuming that each stage has 0.5 ns and the in-chip variation rate is 10%, the variation value per inverter stage is 0.05 n.
s.

Delay circuits 506 and 507 are used because of measurement errors.
If the number of stages is set so that the difference in the delay time of 10 ns or more, the difference in the number of inverter stages needs to be 200 or more. For example, if the number of inverter stages of the delay circuit 506 is 300
If the number of stages is set, the delay circuit 507 has 100 stages, for a total of 40
An inverter with 0 stages, that is, 400 gates is required.

As shown in FIG. 6, since the delay circuits 506 and 507 of the circuit to be measured are spread over a wide range on the semiconductor chip 13, the averaged delay amount is measured and the local delay time difference cannot be measured. Therefore, the variation rate of the delay time in the chip is not obtained, and when the circuit design excluding the variation rate is performed, it causes a malfunction of the circuit, and conversely, if the design is made with an excessive margin of delay time, Not the optimum design,
There is a problem that desired performance can be obtained.

An object of the present invention is to solve the above problems and provide a delay time measuring circuit capable of accurately measuring the delay time.

[0008]

A delay time measuring circuit according to the present invention comprises a first and a second ring oscillator circuits, and first and second frequency dividing circuits which respectively receive outputs of the circuits. , An exclusive OR circuit and an AND gate which receive the outputs of the first and second frequency dividing circuits, respectively, and the AND gate
A one-shot circuit having an output of the gate as an input is provided on a semiconductor chip, and reset inputs of the first and second ring oscillator circuits and the first and second frequency dividing circuits are provided from an output of the one-shot circuit. It is characterized by the introduction.

[0009]

1 is a circuit diagram showing a delay time measuring circuit according to an embodiment of the present invention.

Referring to FIG. 1, in the present embodiment, the first and second ring oscillator circuits 1 and 2, the first and second buffer circuits 3 and 4, and the first and second frequency dividing circuits 5 and 5. 6, an exclusive OR circuit 7, a one-shot circuit 8, AND gates 9 and 10, an output buffer 12, and an input buffer 11
And input and output terminals I1 and O1.

Here, the first and second frequency dividing circuits 5 and 6 are each composed of four stages of flip-flops, the one-shot circuit 8 is composed of an inverter, a buffer and a NAND gate, and the first and second ring oscillators. 1 and 2 are 4 respectively
It has inverters and NAND gates.

The outputs of the ring oscillator circuits 1 and 2 are connected to the frequency dividing circuits 5 and 6 via the buffer circuits 3 and 4, respectively, and the outputs thereof are input to the exclusive OR circuit 7 and further, The outputs of the frequency circuits 5 and 6 are input to the AND gate 9, and the output thereof is input to the one-shot circuit 8. This output becomes the input of the AND gate 10. AND
The other input of the gate 10 is a signal obtained from the signal 101 of the input terminal I1 via the input buffer 11.

The output signal 108 of the exclusive OR (EXNOR) circuit 7 is output through the output buffer 12 to the output terminal O.
1 signal.

FIG. 2 is a plan view showing a state in which the circuit of FIG. 1 is laid out on the semiconductor chip 13. In FIG. 2, AND gate 10, circuits 1, 3, circuits 2, 4, frequency dividing circuits 5, 6 and the like are arranged at optimum positions. The input / output circuit element region 15 is around these, and the pads 14 are arranged at the ends.

In the timing chart of FIG. 3, the signal 101 at the input terminal I1 and the output signal 1 of the AND gate 10 in FIG.
02, the output signal 103 of the first frequency dividing circuit 5, the output signal 104 of the second frequency dividing circuit 6, the output signal 106 of the buffer in the one-shot circuit 8, the output signal 10 of the NAND gate 10.
7, each waveform of the output signal 108 of the circuit 7, when counting,
Shown as at reset on.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG.

Now, the number n of gate stages of the ring oscillator circuits 1 and 2 is set to 9, and the frequency dividing circuits 5 and 6 are configured to divide by 16.

The delay time tpd1 of the inverter circuit is set to 0.
If the intra-chip variation is +0.05 ns, the other delay time tbd2 is 0.55 ns. Next, the input terminal I1 is set to high level. Frequency divider 5, 6
Is released and the ring oscillator circuits 1 and 2 oscillate. At this time, the frequency f of the oscillator is f = 1 /
The following equation is obtained from 2n · tpd.

[0019]

The equation (1) is for the ring oscillator circuit 1 and the equation (2) is for the ring oscillator circuit 2.

The frequency division circuit output for the frequency division by 16 is f '= fx1
From / 16 → tbd = 1 / f ′, the following equation is obtained. From the equations (1) and (2), the following equations (3) and (4) are obtained, respectively.

[0022]

That is, from equations (3) and (4), [158n
The pulse of s−144 ns = 14 ns] is output from the exclusive OR circuit 7.

At that time, the frequency dividing circuits 5, 6 output signals 103,
Both 104 have a high potential, the output signal 105 of the AND gate 9 has a high potential, and the one-shot circuit 8 generates a signal 107 of high potential to low potential to high potential, and this signal causes the ring oscillator circuit 1 to temporarily operate. , 2 and the frequency dividing circuits 5, 6 are reset and then released, oscillation occurs again, and the above state is repeated. Furthermore, in this case, only two terminals can be used.

FIG. 4 is a block diagram showing a delay time measuring circuit according to an embodiment of the present invention.

In FIG. 4, four ring oscillator circuits 407 to 410 each composed of four inverters and one NAND gate, and a buffer circuit 41 for each of these outputs.
5 to 418, a multiplexer circuit 423, a frequency dividing circuit 425, and a ring oscillator 411 having the same configuration as described above.
˜414, buffer circuits 419 to 422, multiplexer circuit 424, frequency dividing circuit 426, and input terminal I
2, S1, S2, S3, S4 and input buffers 401-
405, AND gate 406, and AND gate 430
, A one-shot circuit 427 including an inverter, a buffer, and a NAND gate, and an exclusive OR circuit 428.
, An output buffer 429, and an output terminal O2. In this embodiment, the first ing oscillators 407-4 are provided.
10 and the second ring oscillators 411 to 414, one by one, can be selected by the multiplexers 423 and 426 and similarly measured. In this embodiment, the number of inverter stages is small, and the area occupied by the circuit under test on the semiconductor chip is small. Therefore, the local delay time difference can be measured, and the variation rate of the delay time in the semiconductor chip can be obtained.

By using the circuit of this embodiment, the variation rate in the chip can be grasped, and the optimum design can be performed without taking the delay time difference margin in the chip too much.

As described above, in this embodiment, the two ring oscillator circuits, the circuits for dividing the outputs of the ring oscillator circuits, the exclusive OR circuits connecting the outputs of the ring oscillator circuits, and the frequency dividing circuit are provided on the semiconductor chip. An AND gate connected to the output, a one-shot circuit connected to the output, and an AND gate connected to the output are provided, and the output of the AND gate is a reset input of the two ring oscillators and the two frequency dividing circuits. It is characterized by being connected to.

[0029]

As described above, according to the present invention, since the ring oscillator circuit and the frequency dividing circuit are provided, the number of gate stages is small and the area occupied by the entire chip is small. Therefore, the delay time in the chip is small. There is an effect that the difference of can be accurately measured.

The present invention also has an effect that the present circuit can be used with only two terminals.

[Brief description of drawings]

FIG. 1 is a block diagram showing a delay time measuring circuit according to an embodiment of the present invention.

FIG. 2 is a plan view showing a state in which the circuit shown in FIG. 1 is laid out on a semiconductor chip.

3 is a timing diagram of each part of the circuit of FIG.

FIG. 4 is a block diagram showing a delay time measuring circuit according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional delay time measuring circuit.

6 is a plan view showing a state in which the circuit of FIG. 5 is laid out on a semiconductor chip.

[Explanation of symbols]

1,2,407 to 414 Ring oscillator circuit 3,4,415 to 412 Buffer circuit 5,6,425,426 Dividing circuit 7,428 Exclusive OR circuit 8,427 One shot circuit 9,10,406,430, 504, 505 AND
Gate 11, 401-405, 501, 502 Input buffer 12, 429, 509 Output buffer 13 Semiconductor chip 14 Pad 15 Input / output circuit element area 423, 424, 508 Multiplexer circuit 503 Decoder circuit I1-I3, S1-S5 Input terminal O1 ~ O3 output terminal

Claims (1)

[Claims] 1. A first and a second ring oscillator circuit,
First and second frequency dividing circuits having outputs of the circuits as inputs, exclusive OR circuits and AND gates having outputs of the first and second frequency dividing circuits as inputs, and the AN
A one-shot circuit having an output of the D gate as an input is provided on a semiconductor chip, and reset inputs of the first and second ring oscillator circuits and the first and second frequency dividing circuits are output from the one-shot circuit. A delay time measurement circuit characterized by being introduced from.