JP2007257498A - Spread spectrum clock generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a spread spectrum clock generator for reducing jitter generated in a spread spectrum clock in which the frequency changes periodically, and reducing deterioration of a duty ratio and deterioration of the frequency modulation property of the spread spectrum clock. <P>SOLUTION: A delay cell 11 constituting a delay circuit 10 comprises 2-input NAND gates, clock input circuits 21, 22, 23, 24, 25 and 26 that input a clock CLK in the delay circuit 10 comprises 2-input AND gates and NOR gates, and a bypass circuit 4 for achieving a plurality of degrees of modulation comprise 2-input NAND gates. In the first mode, the clock CLK propagated to the first point P1 of the delay circuit 10 is propagated to the nearest delay cell 11. In the second mode, the clock CLK propagated to the first point P1 is inputted in the delay cell 11 of the second point P2 by bypassing the delay circuit 10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a spread spectrum clock generator that generates a spread spectrum clock whose frequency varies periodically from a constant frequency clock.

  2. Description of the Related Art In recent years, with increasing speed and density of electronic devices, electromagnetic noise (EMI (Electro Magnetic Interference) noise) radiated from the electronic devices tends to increase.

  Here, a spread spectrum clock generator (SSCG) is known as means for suppressing electromagnetic wave noise (see, for example, Non-Patent Document 1). Spread spectrum refers to periodically changing the frequency of a basic clock generated by a crystal resonator or the like with a predetermined profile (referred to as a frequency modulation profile). Since the frequency of the electromagnetic noise is dispersed by this, the peak level of the electromagnetic noise can be kept small.

  As a spread spectrum clock generator system, there are an analog system using a PLL (Phase Locked Loop) circuit and a digital system using a delay circuit (delay line).

  FIG. 7 is a diagram showing a circuit configuration of a conventional spread spectrum clock generator using a digital method.

  A spread spectrum clock generator 100 shown in FIG. 7 is a spread spectrum clock generator that generates a spread spectrum clock (referred to as modulation CLK) whose frequency periodically varies from a clock CLK having a constant frequency.

  The spread spectrum clock generator 100 includes a delay circuit 10 in which a plurality of delay cells (unit delay elements) 11 that output an input clock CLK by delaying the input clock CLK by a unit delay amount (dt) are connected in series. . Each of the plurality of delay cells 11 includes two 2-input NAND gates 11_1 and 11_2. The empty pins of the 2-input NAND gates 11_1 and 11_2 are fixed to the “H” level. In this way, by adopting a configuration of two stages of two-input NAND gates in the delay cell 11 constituting the delay circuit 10, the cell size can be reduced, and the rising time and falling time of the clock CLK can be made uniform. can do.

  The spread spectrum clock generator 100 is provided with eight clock input circuits 20_0, 20_1,..., 20_7 for inputting the clock CLK from the eight input ports on the delay circuit 10 to the delay circuit 10.

  Further, the spread spectrum clock generator 100 is provided with a two-input NAND gate 30 for outputting the modulation CLK from the spread spectrum clock generator 100.

  In the spread spectrum clock generator 100, when the clock CLK is input to the delay circuit 10, the clock input circuits 20_0, 20_1,. Specifically, each of the clock input circuits 20_0, 20_1,..., 20_7 includes a two-input NAND gate, and the clock CLK is commonly input to one of the two-input NAND gates. The selection signals SEL0 to SEL7 are input to the other of these two-input NAND gates. These selection signals SEL0 to SEL7 are sequentially set to the ‘H’ level, whereby the clock input circuits 20_0, 20_1,..., 20_7 are sequentially selected.

  FIG. 8 is a diagram showing the entrance of the delay circuit selected along with the cycle of the clock CLK and the delay time increasing and decreasing along with the delay time and the period of the modulation CLK of the spread spectrum clock generator shown in FIG. It is a figure which shows the waveform of CLK.

  FIG. 8 shows the cycle of the clock CLK, the entrance of the delay circuit 10 corresponding to the selection signals SEL0 to SEL7, the delay time until the clock CLK input to the entrance reaches the exit, the modulation CLK The period is shown.

  In the spread spectrum clock generator 100, the entrance of the delay circuit 10 is selected and the clock CLK is input as shown in FIG. 8 in synchronization with the cycle of the clock CLK. Specifically, the clock input circuits 20_0, 20_1, ..., 20_7, 20_7, 20_6, ..., 20_0 are selected in this order, and the clock CLK is input to the delay circuit 10. Here, the number of the delay cells 11 constituting the delay circuit 10 between the clock input circuits 20_0 and 20_1 is one, and the number of the delay cells 11 between the clock input circuits 20_1 and 20_2 is two. The number of delay cells 11 between the clock input circuits 20_2 and 20_3 is three, and the number of delay cells 11 between the clock input circuits 20_3 and 20_4 is four. Further, the number of delay cells 11 between the clock input circuits 20_4 and 20_5 is three, the number of delay cells 11 between the clock input circuits 20_5 and 20_6 is two, and the number of the delay cells 11 between the clock input circuits 20_6 and 20_7. The number is one.

As described above, since the number of delay cells 11 is different corresponding to each selected entrance, when the entrance of the delay circuit 10 is selected in the order shown in FIG. 8, the input is made as shown in FIG. The delay time until the clock CLK reaches the exit changes. As a result, the period of the modulation CLK is increased or decreased, and the waveform of the modulation CLK becomes a waveform whose period is slightly increased or decreased as shown in FIG. In this way, by periodically increasing or decreasing the frequency of the clock CLK, the frequency of the electromagnetic noise can be dispersed and the peak level of the electromagnetic noise can be kept small.
Fujitsu Limited; FUJITSU ELECTRONIC DEVICES NEWS (FIND Vol. 21, No. 4, 2003)

  Here, the degree of increase / decrease in the period of the clock CLK (± 0 to ± 4 dt in FIGS. 8 and 9) is referred to as a modulation degree (modulation depth) as a ratio to the period. When the modulation degree is deep, in general, the effect of noise reduction is large, but on the other hand, the cycle of the shortest clock CLK is shortened, so that a circuit operating with the clock CLK is required to operate at high speed. For this reason, the modulation degree is often selected as an appropriate value for each circuit while taking into account both the noise reduction effect and the normal operation of the circuit.

  In order to realize different modulation degrees in a digital spread spectrum clock generator, a spread spectrum clock generator described below is employed.

  FIG. 10 is a diagram showing a circuit configuration of a conventional spread spectrum clock generator different from FIG.

  The spread spectrum clock generator 200 shown in FIG. 10 is different from the spread spectrum clock generator 100 shown in FIG. 7 in that the clock input circuits 20_6 and 20_7 are reduced. Further, the number of delay cells 11 between the clock input circuits 20_3 and 20_4 is changed from four to two, and the number of delay cells 11 between the clock input circuits 20_4 and 20_5 is changed from three to one. Is different.

  FIG. 11 is a diagram showing the entrance of the delay circuit selected with the cycle of the clock CLK, the delay time that increases / decreases with it, and the period of the modulation CLK of the spread spectrum clock generator shown in FIG.

  In the spread spectrum clock generator 200, when the clock CLK is input to the delay circuit 10, the clock input circuits 20_0, 20_1,..., 20_5, 20_5, 20_4,. By doing so, the spread spectrum clock generator 100 described above has a modulation degree of ± 4 dt as shown in FIGS. 8 and 9, but in the spread spectrum clock generator 200, as shown in FIG. Furthermore, the degree of modulation decreases to ± 3 dt.

  Now, in order to achieve both the deep modulation degree possessed by the spread spectrum clock generator 100 shown in FIG. 7 and the shallow modulation degree possessed by the spread spectrum clock generator 200 shown in FIG. The clock input circuit which is an entrance for inputting the clock CLK to the delay circuit 10 between the time of the above and the time of shallow modulation may be switched and used as shown below.

  FIG. 12 is a diagram showing a circuit configuration of a spread spectrum clock generator in which the clock input circuit is switched according to the deep modulation depth and the shallow modulation depth.

  The spread spectrum clock generator 300 shown in FIG. 12 includes clock input circuits 20_0, 20_1, 20_2, and 20_3 using two-input NAND gates, and clock input circuits 40_1, 40_2, 40_3, and 40_4 using three-input NAND gates. , 40_5, 40_6. Further, inverters 41 and 42 are provided for generating a mode signal MODE_0 for a deep modulation degree (deep) and a mode signal MODE_1 for a shallow modulation degree (shallow).

  In the spread spectrum clock generator 300, the mode signal MODE_0 is set to the “H” level in order to realize a deep modulation degree. Next, the clock input circuits 20_0, 20_1, 20_2, 20_3, 40_3, 40_4, 40_5, and 40_6 are selected in this order. As a result, the spread spectrum clock generator 100 shown in FIG. 7 is realized. On the other hand, in order to realize a shallow modulation degree, the mode signal MODE_1 is set to the ‘H’ level and the clock input circuits 20_0, 20_1, 20_2, 20_3, 40_1, and 40_2 are selected in this order. As a result, the spread spectrum clock generator 200 shown in FIG. 10 described above is realized. In this way, the delay cell 11 can also be used to achieve both a deep modulation degree and a shallow modulation degree.

  However, in the spread spectrum clock generator 300, the clock input circuits 20_0, 20_1, 20_2, and 20_3 using two-input NAND gates and the clock input circuits 40_1, 40_2, 40_3, 40_4, and 40_5 using three-input NAND gates are used. , 40_6. Here, the delay time differs between the 2-input NAND gate and the 3-input NAND gate. Therefore, the symmetry of the clock CLK propagating through the delay circuit 10 is lost, and jitter is generated in the modulated CLK, which is a spread spectrum clock whose frequency is periodically changed, which is finally output from the spread spectrum clock generator 300. Or the duty ratio deteriorates.

  Here, it is conceivable that a bypass circuit is provided in the middle of the delay circuit 10, and the function of the bypass circuit is enabled when the modulation depth is shallow, and the function of the bypass circuit is disabled when the modulation depth is deep. In such a case, the delay cell 11 constituting the delay circuit 10 needs an input port for switching the validity / invalidity of the function of the bypass circuit. For this reason, the delay cell 11 may require a three-input NAND gate. Therefore, the delay cell 11 requires both a 2-input NAND gate and a 3-input NAND gate. Then, the symmetry of the delay circuit 10 is lost, and there is a problem that jitter occurs in the spread spectrum clock whose frequency varies periodically, the duty ratio deteriorates, and the frequency modulation characteristics deteriorate. .

  In view of the above circumstances, the present invention can suppress jitter generated in a spread spectrum clock whose frequency periodically changes, and can suppress deterioration in duty ratio of the spread spectrum clock and deterioration in frequency modulation characteristics. An object is to provide a spread spectrum clock generator.

The spread spectrum clock generator of the present invention that achieves the above object is a spread spectrum clock generator that generates a spread spectrum clock whose frequency periodically varies from a constant frequency clock.
A delay circuit in which a plurality of delay cells that output an input clock by delaying by a unit delay amount are connected in series;
A plurality of clock input circuits for inputting clocks to the delay circuit from a plurality of input ports on the delay circuit;
In response to the mode switching signal, in the first mode, the clock propagated from the upstream side of the clock propagation of the delay circuit to the first point in the middle of the delay circuit is the delay cell immediately downstream of the first point. In the second mode, the clock that has been propagated to the first point is prevented from being transmitted to the delay cell immediately downstream of the first point, and the clock is bypassed in the middle of the delay circuit. A bypass circuit for inputting to the delay cell at the second point downstream of the clock propagation from the first point of the delay circuit,
The delay cell comprises two 2-input NAND gates connected in series,
The clock input circuit has a two-input AND gate having an input terminal for inputting a clock and an input terminal for inputting an input port selection signal for selecting an input port for inputting the clock, and an output terminal of the two-input AND gate Are connected to each other and an input terminal for inputting the mode switching signal, and the output terminal of the two-input NAND gates constituting the delay cell arranged in the corresponding input port It consists of a NOR gate connected to one input terminal of a 2-input NAND gate,
The bypass circuit has an input terminal for inputting a clock input to the delay cell disposed at the first point and an input terminal for inputting the mode switching signal, and an output terminal is disposed at the second point. The two-input NAND gate connected to one input terminal of the two-input NAND gate on the rear stage side of the delayed cell.

  In a conventional spread spectrum clock generator, a two-input NAND gate and a three-input NAND gate may be used for a plurality of clock input circuits that input a clock to the delay circuit. Also in the technique of providing a bypass circuit in the middle of a delay circuit, there are cases where a 2-input NAND gate and a 3-input NAND gate are required for the delay cells constituting the delay circuit. Since the delay time is different between the 2-input NAND gate and the 3-input NAND gate, the symmetry of the clock and the delay circuit is lost, jitter occurs in the spread spectrum clock whose frequency changes periodically, and the duty ratio deteriorates. There is a problem that frequency modulation characteristics deteriorate.

  The spread spectrum clock generator of the present invention includes a delay circuit in which a plurality of delay cells that output an input clock by delaying by a unit delay amount are connected in series, and a plurality of input ports on the delay circuit to the delay circuit. In the first mode, the clock propagated from the upstream side of the delay circuit is directly transmitted to the nearest downstream delay cell, and in the second mode, it is propagated from the upstream side of the delay circuit. And a bypass circuit for bypassing the middle of the delay circuit and inputting it to a delay cell on the downstream side to select a plurality of modulation degrees. Here, a delay cell constituting the delay circuit is composed of two 2-input NAND gates connected in series, and a plurality of clock input circuits for inputting a clock to the delay circuit are composed of a 2-input AND gate and a NOR gate. Further, a bypass circuit for realizing a plurality of modulation degrees is composed of a two-input NAND gate. For this reason, a conventional technique using a two-input NAND gate and a three-input NAND gate for a plurality of clock input circuits, or a two-input NAND gate in a delay cell constituting the delay circuit when a bypass circuit is provided in the middle of the delay circuit, Compared with a technique using a three-input NAND gate, it is possible to suppress the phenomenon that the symmetry of the clock propagating through the delay circuit is lost or the symmetry of the delay circuit is lost. Therefore, it is possible to suppress the jitter generated in the spread spectrum clock whose frequency varies periodically. Further, it is possible to suppress the deterioration of the duty ratio of the spread spectrum clock and the deterioration of frequency modulation characteristics.

  According to the spread spectrum clock generator of the present invention, it is possible to suppress the jitter generated in the spread spectrum clock whose frequency fluctuates periodically, and to suppress the deterioration of the duty ratio of the spread spectrum clock and the deterioration of the frequency modulation characteristics. Can do.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a circuit configuration of a spread spectrum clock generator according to an embodiment of the present invention.

  A spread spectrum clock generator 1 shown in FIG. 1 is a spread spectrum clock generator that generates a spread spectrum clock (modulation CLK) whose frequency periodically varies from a constant frequency clock.

  The spread spectrum clock generator 1 includes a delay circuit 10 in which a plurality of delay cells (unit delay elements) 11 that output an input clock CLK with a unit delay amount (dt) delayed and output are connected in series. .

  The spread spectrum clock generator 1 is provided with six clock input circuits 21, 22, 23, 24, 25, and 26 for inputting the clock CLK from the six input ports on the delay circuit 10 to the delay circuit 10. ing.

  Further, in the spread spectrum clock generator 1, according to the mode switching signal Mode, in the first mode, from the upstream side of the propagation of the clock CLK of the delay circuit 10 to the first point P1 in the middle of the delay circuit 10 The propagated clock CLK is transmitted to the delay cell 11 immediately downstream of the first point P1. In the second mode, the clock CLK propagated to the first point P1 is prevented from being transmitted to the delay cell 11 immediately downstream of the first point, and the clock CLK is bypassed in the middle of the delay circuit 10. In addition, a bypass circuit 4 is provided that inputs the delay circuit 10 to the delay cell 11 at the second point P2 on the downstream side of the propagation of the clock CLK from the first point P1.

  Here, the delay cell 11 includes two 2-input NAND gates 11_1 and 11_2 connected in series or two 2-input NAND gates 11_1 and 11_2 and an inverter 11_3. The empty pins of the 2-input NAND gates 11_1 and 11_2 are fixed to the “H” level.

  The clock input circuit 21 includes a two-input AND gate 21_1 having an input terminal 21_1a for inputting the clock CLK and an input terminal 21_1b for inputting an input port selection signal SEL0 for selecting an input port for inputting the clock CLK. It has been. The clock input circuit 21 has an input terminal 21_2a to which the output terminal 21_1c of the 2-input AND gate 21_1 is connected, and an input terminal 21_2b to which the mode switching signal Mode is input, and the output terminal 21_2c corresponds to the input terminal 21_2c. A NOR gate 21_2 connected to one input terminal 11_1a of the two-input NAND gate 11_1 on the preceding stage among the two two-input NAND gates 11_1 and 11_2 constituting the delay cell 11 arranged at the port is provided. Note that the configuration of the clock input circuits 22, 23, 24, 25, and 26 is the same as that of the clock input circuit 21 and will not be described in detail. However, the clock input circuit 22 includes a 2-input AND gate 22_1. And a NOR gate 22_2, and the clock input circuit 23 includes a 2-input AND gate 23_1 and a NOR gate 23_2. Further, the clock input circuit 24 includes a 2-input AND gate 24_1 and a NOR gate 24_2, and the clock input circuit 25 includes a 2-input AND gate 25_1 and a NOR gate 25_2. The clock input circuit 26 includes a two-input AND gate 26_1 and a NOR gate 26_2.

  Further, the bypass circuit 4 has an input terminal 4a for inputting the clock CLK input to the delay cell 11 arranged at the first point P1, and an input terminal 4b for inputting the mode switching signal Mode, and an output terminal 4c. Is composed of a two-input NAND gate connected to one input terminal 11_2a of the two-input NAND gate 11_2 on the rear stage side of the delay cell 11 arranged at the second point P2.

  In the spread spectrum clock generator 1 configured as described above, the second mode is set to enable the function of the bypass circuit 4 and realize a shallow modulation degree. Specifically, the mode switching signal Mode is set to the “H” level. The thick solid line shown in FIG. 1 indicates the flow of the clock CLK in the second mode. Further, the selection signals SEL0 to SEL5 are sequentially set to the “H” level, and accordingly, when the clock CLK is input to the delay circuit 10, the clock input circuits 21, 22,. The

  The 'H' level mode switching signal Mode is input to one input terminal 4b of the bypass circuit 4 and the inverter 11_3. As a result, the 'L' level is output from the inverter 11_3, and this 'L' level is input to the 2-input NAND gate 11_2 of the delay cell 11 at the first point P1. Therefore, the propagation of the clock CLK to the delay cell 11 downstream of the delay cell 11 at the first point P1 is stopped. On the other hand, an “H” level mode switching signal Mode is input to one input terminal 4b of the bypass circuit 4, and the clock CLK is propagated from the first point P1 to the other input terminal 4a of the bypass circuit 4. The clock CLK from the upstream delay cell 11 is input. For this reason, the clock CLK from the delay cell 11 at the first point P1 is bypassed and input to the delay cell 11 at the second point P2, so that the clock CLK propagates as shown by the thick solid line in FIG. Finally, it is output as a modulation CLK. In this way, a shallow degree of modulation can be realized.

  On the other hand, the first mode is set to disable the function of the bypass circuit 4 and realize a deep modulation degree. Hereinafter, a description will be given with reference to FIG.

  FIG. 2 is a diagram showing a state in which the spread spectrum clock generator shown in FIG. 1 is set to the first mode in order to realize a deep modulation degree. The thick solid line shown in FIG. 2 indicates the flow of the clock CLK in the first mode.

  Here, the mode switching signal Mode is set to the “L” level. Further, the selection signals SEL0 to SEL5 are sequentially set to the “H” level. As a result, the clock input circuits 21, 22,..., 26 are sequentially selected.

  The 'L' level mode switching signal Mode is input to the bypass circuit 4 and the inverter 11_3. Since the ‘L’ level mode switching signal Mode is input to the bypass circuit 4, the ‘H’ level is output from the bypass circuit 4. Further, the 'L' level mode switching signal Mode is also input to the inverter 11_3. Therefore, the inverter 11_3 outputs the “H” level. This 'H' level is input to the 2-input NAND gate 11_2 of the delay cell 11 at the first point P1. Then, the clock CLK propagates to the delay cell 11 on the downstream side of the delay cell 11 at the first point P1. Therefore, the clock CLK propagates as shown by the thick solid line in FIG. 2, and is finally output as the modulated CLK. In this way, a deep modulation degree can be realized.

  FIG. 3 is a diagram showing a delay cell and a clock input circuit as a comparative example.

  FIG. 3 shows a delay cell 11 composed of two 2-input NAND gates 11_1 and 11_2 and a clock input circuit 20_4 for inputting a clock CLK to the delay cell 11.

  The delay cell 11 delays and outputs the clock CLK input from the preceding delay cell by a unit delay amount (dt). In addition, a signal obtained by ANDing the selection signal SEL4 and the clock CLK is input to the delay cell 11 via the clock input circuit 20_4. Here, when the ‘H’ level is input as the selection signal SEL <b> 4, the clock CLK is input to the delay cell 11. Depending on the purpose, it may be desired to modulate the frequency with a plurality of modulation degrees. Usually, in order to realize a plurality of modulation degrees with one delay circuit 10, it is necessary to change the input location of the clock CLK to the delay circuit 10, or to change the counting method of the clock CLK. However, these systems have the disadvantage of increasing the size of a spread spectrum clock generator (digital SSCG) employing a digital system. In view of this, the delay circuit 10 is provided with a bypass path (digital SSCG with a bypass path) without changing the input location of the clock CLK to the delay circuit 10, that is, without increasing the size. Consider realizing the degree of modulation.

  Here, when the delay cell 11 to be bypassed by the delay circuit 10 corresponds to the input cell of the clock CLK, the input terminal becomes insufficient in the 2-input NAND gate. Therefore, the 2-input NAND gate is changed to a 3-input NAND gate.

  FIG. 4 is a diagram showing a delay cell having a three-input NAND gate and a clock input circuit.

  FIG. 4 shows a delay cell 11 composed of a 3-input NAND gate 11_4 and a 2-input NAND gate 11_2, and a clock input circuit 20_4 for inputting the clock CLK to the delay cell 11. The 3-input NAND gate 11_4 receives the bypassed clock CLK, the clock CLK from the preceding delay cell, and the clock CLK from the clock input circuit 20_4. Here, the delay cell 11 shown in FIG. 4 constituting the delay circuit 10 is provided with a 2-input NAND gate 11_2 and a 3-input NAND gate 11_4. Since the delay time is different between the 2-input NAND gate 11_2 and the 3-input NAND gate 11_4, the symmetry of the delay circuit 10 is lost, jitter is generated in the modulation CLK, the duty ratio of the modulation CLK is deteriorated, and the frequency modulation is performed. There arises a problem that the characteristics of the above deteriorate.

  FIG. 5 is a diagram showing a delay cell and a clock input circuit constituting the spread spectrum clock generator shown in FIG. 1, and FIG. 6 is a correspondence between a level and each mode in each node of the delay cell and the clock input circuit shown in FIG. It is a figure which shows a relationship.

  FIG. 5 shows the delay cell 11 and the clock input circuit 25 constituting the spread spectrum clock generator 1 shown in FIG.

  Conventionally, a two-input NAND gate is used for the clock input circuit that inputs the clock CLK to the delay circuit 10, but in this embodiment, instead of the two-input NAND gate, as shown in FIG. A clock input circuit 25 including a two-input AND gate 25_1 and a NOR gate 25_2 is used. The selection signal SEL4 and an external clock CLK are input to the 2-input AND gate 25_1. The mode switching signal Mode is input to the NOR gate 25_2. Furthermore, the clock CLK from the preceding delay cell is input to the two-input NAND gate 11_1 which is the first stage of the delay cell 11. The bypassed clock CLK is input to the second-stage 2-input NAND gate 11_2.

  Here, a node of the first-stage 2-input NAND gate 11_1 to which the clock CLK from the preceding delay cell is input is denoted by a. Further, a node of the NOR gate 25_2 to which an external clock CLK is input is denoted by b. Further, the node of the output of the 2-input NAND gate 11_1 is c, and the node of the second-stage 2-input NAND gate 11_2 to which the bypassed clock CLK is input is d.

  Further, in the 2-input NAND gate 11_1, a node to which the selection signal SEL4 is input is A, a node to which the mode switching signal Mode is input in the NOR gate 25_2 is B, and an output node of the NOR gate 25_2 is Z.

  Here, when the mode switching signal Mode is set to the “H” level, the node Z that is the output of the NOR gate 25_2 goes to the “L” level. Then, the node c is fixed to the “H” level regardless of the state of the node a. Therefore, the bypass clock CLK can be input from the node d. Since the bypass clock CLK can be input from the node d, the first-stage gate of the delay cell 11 may be a 2-input NAND gate, and the symmetry of the delay circuit 10 can be prevented from being lost. Therefore, the problem that jitter occurs in the modulation CLK, the duty ratio of the modulation CLK deteriorates, and the frequency modulation characteristics deteriorate is solved.

  Here, as shown in FIG. 6, when the “L” level is input to both the nodes A and B, the node Z becomes the “H” level, and the clock passing mode in which the clock CLK from the preceding delay cell passes is passed. It becomes. In addition, when the “H” level and the “L” level are input to the nodes A and B, the clock input mode in which the clock CLK in which the logic of the clock CLK input from the outside is inverted is output from the node Z; Become. Further, when the ‘L’ level and the ‘H’ level are input to the nodes A and B, the node Z becomes the ‘L’ level and the bypass mode is set. When the “H” level is input to both the nodes A and B, the node Z becomes the “L” level and is treated as an invalid mode.

It is a figure which shows the circuit structure of the spread spectrum clock generator of one Embodiment of this invention. FIG. 2 is a diagram showing a state in which the spread spectrum clock generator shown in FIG. 1 is set to a first mode in order to realize a deep modulation degree. It is a figure which shows a delay cell and a clock input circuit as a comparative example. It is a figure which shows the delay cell provided with 3 input NAND gate, and a clock input circuit. It is a figure which shows the delay cell and clock input circuit which comprise the spread spectrum clock generator shown in FIG. FIG. 6 is a diagram showing a correspondence relationship between levels and modes in each node of the delay cell and the clock input circuit shown in FIG. 5. It is a figure which shows the circuit structure of the conventional spread spectrum clock generator by a digital system. FIG. 8 is a diagram illustrating an entrance of a delay circuit selected along with a cycle of a clock CLK, a delay time that increases / decreases accordingly, and a period of a modulation CLK of the spread spectrum clock generator illustrated in FIG. 7. It is a figure which shows the waveform of modulation | alteration CLK. It is a figure which shows the circuit structure of the conventional spread spectrum clock generator different from FIG. FIG. 11 is a diagram illustrating an entrance of a delay circuit selected along with a cycle of a clock CLK, a delay time that increases / decreases accordingly, and a period of a modulation CLK of the spread spectrum clock generator illustrated in FIG. 10. It is a figure which shows the circuit structure of the spread spectrum clock generator by which a clock input circuit is switched according to a deep modulation degree and a shallow modulation degree.

Explanation of symbols

1, 100, 200, 300 Spread spectrum clock generator 4 Bypass circuit 4a, 4b, 11_1a, 11_2a, 21_1a, 21_1b, 21_2a, 21_2b Input terminal 4c, 21_1c Output terminal 10 Delay circuit 11 Delay cell 11_1, 11_2, 30 2-input NAND Gate 11_3 Inverter 11_4 3-input NAND gate 21, 22, 23, 24, 25, 26 Clock input circuit 21_1, 22_1, 23_1, 24_1, 25_1, 26_1 2-input AND gate 21_2, 22_2, 23_2, 24_2, 25_2, 26_2 NOR gate

Claims (1)

In a spread spectrum clock generator that generates a spread spectrum clock whose frequency periodically varies from a constant frequency clock,
A delay circuit in which a plurality of delay cells that output an input clock by delaying by a unit delay amount are connected in series;
A plurality of clock input circuits for inputting clocks to the delay circuit from a plurality of input ports on the delay circuit;
In response to the mode switching signal, in the first mode, in the delay circuit, the clock propagated from the upstream side of the clock propagation to the first point in the middle of the delay circuit is the delay cell immediately downstream of the first point. In the second mode, the clock transmitted to the first point is prevented from being transmitted to the delay cell immediately downstream of the first point, and the clock is bypassed in the middle of the delay circuit. A bypass circuit for inputting to a delay cell at a second point on the downstream side of the clock propagation of the delay circuit,
The delay cell comprises two 2-input NAND gates connected in series;
The clock input circuit has a two-input AND gate having an input terminal for inputting a clock and an input terminal for inputting an input port selection signal for selecting an input port for inputting the clock, and an output terminal of the two-input AND gate Are connected to each other and an input terminal for inputting the mode switching signal, and the output terminal of the two-input NAND gates constituting the delay cell arranged in the corresponding input port It consists of a NOR gate connected to one input terminal of a 2-input NAND gate,
The bypass circuit has an input terminal for inputting a clock input to the delay cell arranged at the first point and an input terminal for inputting the mode switching signal, and an output terminal is arranged at the second point. A spread spectrum clock generator comprising a two-input NAND gate connected to one input terminal of a two-input NAND gate on the rear stage side of the delayed cell.

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