JP2000232346A - Pulse width modulation waveform generation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pulse width modulation waveform generation circuit for reducing a circuit scale and also reducing power consumption. SOLUTION: This pulse width modulation waveform generation circuit is provided with a ring oscillator 1a for which 64 pieces of inverter means are cascade-connected, an inverter respectively connected to the output terminals of the inverter means of odd-numbered stages inside the ring oscillator, a multiplexer 2, a change detection circuit 4 and an RS flip-flop 5. The output of the inverter means of even-numbered stages inside the ring oscillator and the output of the inverter are inputted to the multiplexer and one of them is selected corresponding to the logic of digital signals. The RS flip-flop 5 is set at the point of time of outputting edge detection pulses from the change detection circuit 3 and is reset at the point of time of outputting the edge detection pulses from the change detection circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a circuit for generating a pulse width modulation (PWM) signal having a pulse width corresponding to the logic of a digital signal.

[0002]

2. Description of the Related Art A PWM (Pulse Width Modulation) waveform generating circuit is widely used in various electronic circuits such as a DC-DC converter (switching power supply). The use of electric power has a great merit from the viewpoint of the whole system. FIG.
FIG. 3 is a block diagram showing a configuration of a conventional PWM waveform generating circuit, and shows an example of generating a PWM signal having a duty ratio according to the logic of a 6-bit digital signal. The PWM waveform generating circuit of FIG. 26 includes a ring oscillator 1 in which 64 buffers BF are cascaded, a multiplexer (MUX) 2 for selecting any one of the outputs of the buffers BF of each stage in the ring oscillator 1, A change detecting circuit 3 for detecting a logical change position of the output of the ring oscillator 1, a change detecting circuit 4 for detecting a logical change position of the output of the multiplexer 2,
And a flip-flop 5. FIG. 27A is a diagram for explaining the operation principle of the multiplexer 2. An example in which any one of 2 ⁶ = 64 types of input signals A0 to A63 is selected by the logic of the ⁶ -bit selection signals D0 to D5. Is shown. The least significant bit of the selection signals D0 to D5 is D
0 and the most significant bit is D5, the selection signals D0 to D5
Is represented by Expression (1).

[0003] As shown by a thick ^{M = D5 · 2 5 + D4} · 2 4 + D3 · 2 3 + D2 · 2 2 + D1 · 2 + D0 ... (1) FIG. 27 (a), the example input signal A3
When selecting, select signals (D5, D4, D3, D2, D1, D0)
(0,0,0,0,1,1). That is, the numerical value M representing these selection signals in decimal notation is "3". In this specification, the multiplexer performs the selection operation in the same manner as in FIG. 27A without depending on the signal names of the selection signal and the input signal. For example, in FIG. 27B, the least significant bit of the selection signal is T0, the most significant bit is S5, and different types of input signals (C0, C1, B5, B0, A4,..., R0, F11) are input. An example is shown. For example, (S5, S4, S3, S2, S1, S0, T0) = (0,0,
In the case of (0,0,1,0), as shown in FIG. 27B, the third input signal B5 from the left is selected. As shown in detail in FIG. 28A, the change detection circuit 3 of FIG. 26 includes a delay circuit 6 for delaying a signal by a time substantially equal to the signal propagation delay time of the multiplexer 2, and an even number of cascade-connected It has an inverter 7 and an EXOR gate 8, and the output of the change detection circuit 3 is the set terminal S of the RS flip-flop 5.
Is input to Similarly, the change detection circuit 4
As shown in the detailed configuration of (b), the inverter has an even number of inverters 9 connected in cascade and an EXOR gate 10, and the output of the change detection circuit 4 is input to the reset terminal R of the RS flip-flop 5. .

The last stage buffer BF in the ring oscillator 1
Is inverted by the NAND gate G1 and then fed back to the first stage buffer BF. When the active terminal connected to the input terminal of the NAND gate G1 is set to a high level, the stable state is lost, and the ring oscillator 1 performs an oscillating operation.
On the other hand, when the active terminal is set to the low level, the outputs of the buffers BF of the respective stages are all set to the high level, and the oscillation stops. Although this active terminal is not essential, it is often provided for the purpose of outputting a PWM signal only when necessary to reduce power consumption. The number of bits of the digital signal input to the multiplexer 2 and the number of connection stages of the buffer BF in the ring oscillator 1 are not particularly limited. FIG. 29 is a timing chart of each part in the PWM waveform generation circuit of FIG. FIG. 29 shows the waveform of the output A of the ring oscillator 1, the output waveform of the first stage buffer BF, the output waveform of the second stage buffer BF, the output waveform of the third stage buffer BF, and the output of the 33rd stage buffer BF. The waveform, the output waveforms of the change detection circuits 3 and 4, and the output waveform of the RS flip-flop 5 are shown. The operation of the circuit of FIG. 26 will be described below with reference to the timing chart of FIG. The buffer BF of each stage in the ring oscillator 1 inputs the output signal of the buffer BF of the first stage to the buffer BF of the next stage while delaying the output signal by a predetermined time. Further, the output signal of the buffer BF of the last stage is output from the NAND gate G.
After the phase is inverted by 1, the signal is input to the first stage buffer BF.

[0005] The multiplexer 2 outputs digital signals S0 to S0.
Based on the logic of S5, one of the outputs of the buffers BF of each stage in the ring oscillator 1 is selected. The change detection circuit 3 detects a rising edge and a falling edge of the output of the ring oscillator 1, and outputs a narrow pulse when the edge is detected. The change detection circuit 4 detects a rising edge and a falling edge of the output of the multiplexer 2,
When an edge is detected, a narrow pulse is output. For example, if the output A of the ring oscillator 1 changes to a high level at time T1 in FIG. 29, the change detection circuit 3 outputs a positive pulse from time T1 to T2. At this time, the bits S5 to S0 of the digital signal are (1,0,0,0,0,
0), the output of the 33rd-stage buffer BF is selected by the multiplexer 2, and the change detection circuit 4 outputs a positive pulse from time T3 to time T4. As a result, the RS flip-flop 5 is set at time T1 and reset at time T3. That is, the RS flip-flop 5 outputs a PWM signal having a pulse width from time T1 to time T3. Similarly, the change detection circuit 3 outputs a positive pulse from time T5 to T6, and the change detection circuit 4 outputs a positive pulse from time T7 to T8. Therefore, the RS flip-flop 5 is set at time T5 and reset at time T7.

[0006]

By the way, P in FIG.
When the WM waveform generating circuit has a CMOS configuration, each buffer BF in the ring oscillator 1 is configured by two inverters, so that the circuit scale of the ring oscillator 1 becomes large. For example, when 64 stages of buffers BF are cascaded, twice as many as 128 stages of inverters must be connected. When the circuit scale becomes large,
It becomes difficult to reduce the size of the system incorporating the circuit of FIG. 26, and the power consumption increases. The present invention has been made in view of such a point, and an object of the present invention is to provide a pulse width modulation waveform generation circuit having a small circuit size and low power consumption.

[0007]

In order to achieve the above object, ²ⁿ kinds of pulse width modulation signals having different pulse widths are respectively converted according to a digital signal of n bits (n is an integer of 2 or more). In the generated pulse width modulation circuit,
Oscillating signal output means having m (m is an integer of 2 or more) first inverters connected in series, and oscillating signal output means for outputting oscillating signals having different phases from the first inverters, and the n-bit digital signal Selecting means for selecting one of the signals corresponding to the output signals of the m first inverters connected in series based on at least a part of the bits of the first inverter, and a signal selected by the selecting means And a pulse generation means for generating the pulse width modulation signal having a pulse width corresponding to the following.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a pulse width modulation waveform generating circuit (hereinafter, PWM waveform generating circuit) according to the present invention will be described.
This will be specifically described with reference to the drawings. (First Embodiment) FIG. 1 is a block diagram showing a configuration of a first embodiment of a PWM waveform generating circuit according to the present invention.
In FIG. 1, the same components as those of the conventional circuit shown in FIG. 26 are denoted by the same reference numerals. The circuit of FIG. 1 includes a ring oscillator (oscillation signal output means) 1a in which 64 inverters IV1 are cascaded, an inverter IV2 respectively connected to an output terminal of an odd-numbered inverter IV1 in the ring oscillator 1a, A multiplexer (selection means) 2, change detection circuits (first and second edge detection circuits) 3, 4;
S flip-flop (set / reset circuit) 5. The change detection circuits 3 and 4 and the RS flip-flop 5 correspond to the pulse generation means 50. The output of the inverter IV1 of the even-numbered stage in the ring oscillator 1a and the output of the inverter IV2 are input to the multiplexer 2, and one of them is selected according to the logic of the digital signals S0 to S5. . Next, the operation of the circuit of FIG. 1 will be described. The multiplexer 2 selects either the output of the even-numbered-stage inverter IV1 or the output of the inverter IV2 in the ring oscillator 1a based on the logic of the digital signals S0 to S5.

The change detection circuit 3 detects a rising edge and a falling edge of the output A of the ring oscillator 1a and outputs an edge detection pulse. The change detection circuit 4 detects a rising edge and a falling edge of the output B of the multiplexer 2 and outputs an edge detection pulse. The RS flip-flop 5 is set when the edge detection pulse is output from the change detection circuit 3, and is reset when the edge detection pulse is output from the change detection circuit 4. Therefore, from the RS flip-flop 5, the ring oscillator 1
A PWM signal having a pulse width from the time when the output A of a becomes high to the time when the output of the multiplexer 2 becomes high is output. Ring oscillator 1a of FIG.
Has 64 stages of inverters IV1, so for example, CM
When configured with an OS, the size is about half the size of the ring oscillator 1a in FIG. However, the adjacent inverter IV
In this embodiment, since the output logic of each inverter 1 is inverted with respect to the phase of the output A, the output of the odd-numbered stage inverter IV1 whose phase differs from that of the output A by a half cycle or more is inverted in the present embodiment. To enter. Therefore, the 32 inverters IV connected to the odd-numbered inverter IV1
2 is newly needed, and 64 + 32 = 9 in total
It will have six inverters. Therefore, assuming that the formation areas of the inverters are all equal, the ring oscillator 1a in FIG. 1 has a circuit area of 96/128 = 3/4 as compared with the ring oscillator 1 in FIG.

In the case of the PWM waveform generating circuit shown in FIG. 1, the output of the odd-numbered inverter IV1 in the ring oscillator 1a is input to the multiplexer 2 via the inverter IV2. , The signal is delayed. This delay time is equal to the ring oscillator 1a
This does not matter when the oscillation frequency is low, but when the oscillation frequency is high, an error also occurs in the pulse width of the finally generated PWM signal. Therefore, when it is desired to generate a high-precision PWM signal, the size of the inverter IV2 is adjusted to reduce the signal propagation time, or the output of the odd-numbered inverter IV1 in the ring oscillator 1a using a delay element or the like. And the output of the even-numbered-stage inverter IV1 may be adjusted. As described above, in the first embodiment, the ring oscillator 1a is configured by cascade-connecting the plurality of inverters IV1, and the output of the odd-numbered inverter IV1 is
Since the signal is input to the multiplexer 2 via the inverter IV2, the same phase as when the ring oscillator 1a is configured by a plurality of buffers can be obtained. Therefore, similarly to the related art, the PWM signal can be generated by selecting the delay signal according to the logic of the digital signal by the multiplexer 2.

The ring oscillator 1a shown in FIG. 1 includes an inverter IV1 instead of the buffer BF.
When constituted by MOS, the circuit scale can be reduced and the power consumption can be reduced. (Second Embodiment) The second embodiment has a further smaller circuit scale than the first embodiment. FIG. 2 is a block diagram showing a configuration of a second embodiment of the PWM waveform generating circuit according to the present invention, and the same reference numerals are given to the same components as those in FIG. The circuit of FIG. 2 is similar to that of FIG. 5 in that a plurality of cascaded inverters IV1 are provided in the ring oscillator 1a, but the output of the odd-numbered inverter IV1 is directly input to the multiplexer 2. 5 circuit. The output of multiplexer 2 is EX
It is input to a NOR gate (inverting / non-inverting setting circuit) 21. E
The XNOR gate 21 inputs an inverted signal of the exclusive OR of the output of the multiplexer 2 and the least significant bit S0 of the digital signal to the change detection circuit. Next, the operation of the circuit of FIG. 2 will be described. The multiplexer 2 includes digital signals S0 to S5
, One of the outputs of the inverter IV1 at each stage in the ring oscillator 1a is selected and output.

For example, the least significant bit S0 of the digital signal
Is "1", the multiplexer 2 selects one of the outputs of the even-numbered stage inverter IV1. in this case,
A signal having the same logic as the output of the multiplexer 2 is input to the change detection circuit 4 via the EXNOR gate 21. On the other hand, when the least significant bit S0 of the digital signal is "0", the multiplexer 2 selects one of the outputs of the odd-numbered stage inverter IV1. In this case, a signal obtained by inverting the output of the multiplexer 2 is input to the change detection circuit 4 via the EXNOR gate 21. That is, when the least significant bit S0 of the digital signal is “0”, a signal obtained by inverting the output of the inverter IV1 of the odd-numbered stage in the ring oscillator 1a is input to the change detection circuit 4, and as shown in FIG. Oscillator 1
The output of the inverter IV1 of the odd-numbered stage in FIG.
The result is the same as when 2 is connected. Thus, the second
Is an inverter of each stage in the ring oscillator 1a.
The output of IV1 is directly input to the multiplexer 2, and whether to invert the output of the multiplexer 2 is selected according to the logic of the least significant bit S0 of the digital signal. Therefore, the inverter IV2 shown in FIG. 1, the circuit scale can be made smaller and the power consumption can be further reduced.

(Third Embodiment) The third embodiment has a further smaller circuit scale than the second embodiment. FIG. 3 is a block diagram showing a configuration of a third embodiment of the PWM waveform generating circuit according to the present invention, and the same reference numerals are given to the same components as those in FIG. The circuit of FIG.
Compared to the circuit of FIG. 1, the arrangement of the digital signals S0 to S5 input to the control input terminals of the multiplexer 2 is changed, there is no EXNOR gate, and the rise detection circuits 3a, 3a, There is a feature in that 4a is provided. A control input terminal of the multiplexer 2 in FIG. 3 includes, from the lower side, an inverted signal of the most significant bit S5 of the digital signal,
S0, S1, S2, S3, and S4 are input in this order. Third
Focuses on the fact that when a signal is input to the inverter IV1, the phase is inverted. Instead of returning the signal inverted by the inverter IV1 to the original logic, the signal inverted by the inverter IV1 is half a cycle or more. It is characterized in that it is treated as a shifted signal. For example, since the output A of the ring oscillator 1a is input to the first-stage inverter IV1, the output of the first-stage inverter IV1 is a signal obtained by inverting the output A and slightly delaying the output. This signal corresponds to the 32nd delay signal. The output of the second-stage inverter IV1 corresponds to the 0th delay signal, the output of the third-stage inverter IV1 corresponds to the 33rd delay signal, and the output of the fourth-stage inverter IV1 corresponds to the first delay signal. .

The numerical value M in FIG. 3 indicates the phase order of each inverter IV1 in the ring oscillator 1a with reference to the output A of the last inverter IV1 in the ring oscillator 1a. The numerical value N 'indicates the stage number of each inverter IV1 in the ring oscillator 1a. The output of the even-stage inverter (N 'is an even number) has a phase that is delayed by more than half a cycle as compared with the output A of the final stage. In this case, the phase difference M is a value obtained by adding a half cycle time to the signal propagation time determined by the inverter stage number N ′, and M = N ′ / 2 + 32. On the other hand, the output of the odd-stage inverter (N 'being an odd number) has a phase difference within half a cycle as compared with the output A of the last stage. The phase difference M in this case is represented by M = (N′−1) / 2.
Therefore, regardless of whether the stage is even or odd,
By setting the inverted signal of the most significant bit S5 of the selection control signal N (S5 to S0) as the least significant bit and shifting the other bits one bit at a time to the upper bit side, the phase difference order M between the control input N and the output of the multiplexer is obtained. And can be matched. As shown in detail in FIG. 4A, the rise detection circuit 3a of FIG. 3 includes a delay circuit 6 for delaying the output of the ring oscillator 1a by a time substantially equal to the signal propagation delay time of the multiplexer 2, and an odd number of cascades. Connected inverter 7 and AN
And a D gate 31. The rising detection circuit 4a shown in FIG. 3 includes an odd number of cascade-connected inverters 9 and an AND gate.
And a gate 32.

The rising detection circuit 3a includes the ring oscillator 1
The rising edge of the output A is detected, and the rising edge detection circuit 4a detects the rising edge of the output B of the multiplexer 2. FIG. 5 is a timing chart of each part in the circuit of FIG. The timing chart of FIG. 5 shows an example in which the PWM signal is generated using the 33rd delay signal. The output of the rise detection circuit 3a is output between time T1 and T2 in FIG.
It goes high between T6 and T6. Also, the change detection circuit 4a
Is at a high level between times T3 and T4 and between T7 and T8 in FIG. The RS flip-flop 5 operates at time T1
At time T3 and reset at time T3.
5 and reset at time T7. For this reason, the PWM waveform generation circuit of FIG. 5 outputs a PWM signal that goes high between times T1 to T3 and times T5 to T7. Thus, in the third embodiment, the ring oscillator 1a
Of the outputs of the inverters IV1 of the odd-numbered stages among the outputs of the inverters IV1 of the respective stages in FIG.
As in the embodiment, the process of inverting the output of the odd-numbered stage inverter IV1 is not required, so that the circuit scale can be further reduced and the power consumption can be reduced.

(Fourth Embodiment) The fourth embodiment is composed of three components.
This is to generate 64 types of PWM signals using a two-stage inverter. FIG. 6 is a block diagram of a fourth embodiment of the PWM waveform generating circuit according to the present invention. PWM of FIG.
The waveform generating circuit includes a ring oscillator 1a, a 32-input 1-output multiplexer 2a, an EXOR gate 21, a 2-input 1-output
And an output multiplexer 22. The EXOR gate 21 and the multiplexer 22 form a pulse generating means 50b.
Is configured. The ring oscillator 1a includes a cascade-connected 3
It has two inverters IV1 and a NAND gate (logic inversion means) G1 connected between the output terminal of the last-stage inverter IV1 and the input terminal of the first-stage inverter IV1. NA
The ring oscillator 1a is connected to one input terminal of the ND gate G1.
The output terminal of the last-stage inverter IV1 is connected, and the active terminal is connected to the other input terminal. Next, the basic principle of the fourth embodiment will be described. The pulse signal input to the first-stage inverter IV1 of the ring oscillator 1a is delayed by a predetermined time every time the pulse signal passes through the first-stage inverter IV1, and the output A of the last-stage inverter IV1 is applied to the input signal of the first-stage inverter IV1. On the other hand, the signal is shifted in phase by substantially a half cycle.

More specifically, the output A of the ring oscillator 1a
, The output of the odd-numbered inverter IV1 is a signal obtained by delaying the output A by a predetermined time. On the other hand, the output of the even-numbered inverter IV1 is a signal obtained by delaying the inverted signal of the output A by a predetermined time. That is, a signal having a phase different from output A by a half cycle or more is output from even-numbered stage inverter IV1. Also, the falling edge of the output of the inverter IV1 in each stage is shifted in phase by a half cycle from the rising edge of the output of the inverter IV1 in each stage. Therefore,
Taking into account the rise and fall of the output of the inverter IV1 of 32 stages in the ring oscillator 1a, a total of 64
Signals having different types of phases can be obtained. That is,
In the previous three embodiments, only the rising edge of the signal is used, but in the fourth embodiment, the number of stages of the ring oscillator can be halved by using the falling edge. Hereinafter, the rise and fall of the signal are collectively called an edge. The following pulse signals are considered for these 64 types of edges. In the fourth embodiment, one of 64 types of edges having different phases is selected based on the logic of the digital signals S0 to S5, and 64 edges are selected based on the selected edge and the output A of the ring oscillator 1a. PWM signals having different types of pulse widths are generated.

Inverter IV1 of each stage of ring oscillator 1a
Of the input / output signals is determined by the 5-bit digital signals S0 to S input to the multiplexer 2a.
Determined by the logic of 4. For example, if the digital signal is "0000
In the case of "0", the input signal of the first-stage inverter IV1 is selected, and in the case of "11111", the last-stage inverter IV1 is selected.
One input signal is selected. FIG. 7 is a diagram showing the relationship between the input of the inverter IV1 of each stage in the ring oscillator 1a and the order of the rising and falling phases of the signal. In FIG. 7, the stage number “0” indicates the first stage inverter IV1 and the stage number “31” indicates the last stage inverter IV1. The phase order is based on the rise of the signal at the output A of the ring oscillator 1a. When the output A rises, the signal is inverted by the NAND gate G1,
The signal falls at the “0” stage. Then, the signal is inverted by the inverter IV1 in the first stage, and the signal rises in the “1” stage. In this way, the signal is transmitted while repeating inversion,
When the signal rises at the "31" stage, the output A of the last inverter falls, and then the signal rises at the stage number "0". When this signal is transmitted, the falling of the stage number "31" becomes the 63rd phase, and then the output A rises again.
Thereafter, this is repeated.

In the fourth embodiment, PW is performed as follows.
Generate an M waveform. First, one of the outputs in the 32 types of ring oscillators is selected. Hereinafter, this signal is referred to as a selected signal. One of the two rising and falling edges of the selected signal is selected. Hereinafter, this is referred to as a selected edge. The rising edge of the output A is called a reference edge. Considering a PWM waveform that rises at the same time as the reference edge and falls at the same time as the selected edge, the pulse width of this signal is proportional to the phase delay of the selected edge. Therefore, if the vertical relationship between the phase order in FIG. 7 and the integer N (0 to 63) determined by the digital signals S0 to S5 is maintained, a PWM waveform having a pulse width corresponding to N can be generated. Here, N is represented as follows by 6-bit signals S0 to S5. N = S0 + 2 × S1 + 2 a ^{2 × S2 + 2 3 × S3} + 2 4 × S4 + 2 5 × S5 N To the above formula may be as follows. The stage number is associated with an integer N ′ determined by the lower 5 bits. N '= S0 + 2 × S1 + 2 2 × S2 + 2 3 × S3 + 2 4 × S4 further chooses one of rising and falling in accordance with the most significant bit S5. That is, if S5 is 0, the phase delay within half a cycle is selected, and if S5 is 1, the phase delay is longer than a half cycle.

For example, when N = (100100), that is, N = 36, the number determined by the lower 5 bits is (O0100), that is, 4. Therefore, the stage number is 4. Further, since the most significant bit S5 is "1", the rising edge (phase order 36 in FIG. 7) whose phase difference is equal to or more than a half cycle is selected. In this manner, PWM waveforms having different pulse widths can be generated according to the integer N determined by S0 to S5. FIGS. 8A to 8D are timing charts showing an example of generating a PWM waveform based on the above-described mechanism. (A) is (S0, S5) = (O, O), (b) is (S0, S5) =
When (O, 1), (c) is (d) when (SO, S5) = (1,0)
Is when (SO, S5) = (1,1). B is the multiplexer 2
This is the selected signal selected by a. FIG. 8A,
When S0 = 0 as in FIG. 8 (b), the stage number is an even number and the phase is longer than a half cycle. When S5 = 0, the edge whose pulse width is within a half cycle is selected. FIG. 9 shows the waveforms of FIGS. 8A to 8D in a logical table. (I) of FIG. 9 corresponds to (a) of FIG.
8 (b), (iii) corresponds to FIG. 8 (c), and (iv) corresponds to FIG. 8 (d).

The bits S0 and S5 of the digital signal are (0,0)
, The phase difference order with respect to the output A is “0, 2, 4,
The PWM signal is generated based on the "..., 30" th edge. In this case, the result OUT obtained by performing a logical operation between the output A of the ring oscillator 1a and the output B of the multiplexer 2
Is represented by the following logical expression (2). OUT = A · B (2) When the bits S0 and S5 of the digital signal are (0, 1), the order of the phase difference with respect to the output A is based on the “32, 34, 36,. As a result, a PWM signal is generated. In this case, a result OUT obtained by performing a logical operation between the output A of the ring oscillator 1a and the output B of the multiplexer 2 is expressed by the following logical expression (3). OUT = A + / B (3) When the bits S0 and S5 of the digital signal are (1,0), the phase difference order with respect to the output A is "1,3,5, ..., 31".
A PWM signal is generated based on the th edge. In this case, the result OUT obtained by performing a logical operation between the output A of the ring oscillator 1a and the output B of the multiplexer 2 is expressed by the following logical expression (4). OUT = A · / B (4) When the bits S0 and S5 of the digital signal are (1, 1), the phase difference order with respect to the output A is “33, 35, 37,..., 63”.
A PWM signal is generated based on the th edge. In this case, a result OUT obtained by performing a logical operation between the output A of the ring oscillator 1a and the output B of the multiplexer 2 is expressed by the following logical expression (5).

OUT = A + B (5) FIG. 10 shows the logical diagram of FIG. 9 rearranged and rearranged. As can be seen from FIG. 10, the least significant bit S0 of the digital signal and the output signal B of the multiplexer 2 are (0,0)
At this time, the PWM signal OUT has the same logic as the most significant bit S5 of the digital signal. When the signal S0 and the output B are (0, 1), the PWM signal OUT has the same logic as the output signal A of the ring oscillator 1a. Similarly,
When the signal S0 and the output B are (1, 0), the PWM signal OUT
Becomes the same as the logic of the output signal A of the ring oscillator 1a. When the signals S0 and B are (1,1), the PWM signal OUT has the same logic as the most significant bit S5 of the digital signal. When a circuit is formed based on the logic diagram of FIG.
As shown in FIG. The EXOR gate 21 calculates an exclusive OR of the output signal B of the multiplexer 2a and the least significant bit S0 of the digital signal. The multiplexer 22 has an EX
Either the signal S5 or the signal A is selected based on the logic of the OR gate 21. Next, the operation of the circuit of FIG. 6 will be described. In contrast to the output A of the last stage of the ring oscillator 1a, the output of the even-numbered inverter IV1 in the ring oscillator 1a is delayed by more than half a cycle, whereas the output of the odd-numbered inverter IV1 is delayed.
The phase lag of the output of No. 1 is within a half cycle. However, since the least significant bit S0 of the digital signal is input to one input terminal of the EXOR gate 21 in FIG. 6, the EXOR gate 21 is only used when the multiplexer 2a selects the output of the odd-numbered stage inverter IV1. The output of 2a is inverted. As a result, the phase of the output C of the EXOR gate 21 always lags the output A of the last stage of the ring oscillator 1a by a half cycle or more.

FIG. 11 is a timing waveform diagram of the output A of the final stage of the ring oscillator 1a, the output C of the EXOR gate 21, and the output Q of the multiplexer 22. Assuming that the delay time of the NAND gate G1 in FIG. 6 is d, the cycle of the output A of the final stage of the ring oscillator 1a and the cycle T of the output B of the multiplexer 2a are both T = 66d. Further, assuming that the number of stages of the inverter IV1 in the ring oscillator 1a is N ′, the signal propagation delay time Tall of the NAND gate G1 and the ring oscillator 1a is (N ′ + 1) × d. This delay time Tal
There is a phase difference between the output A and the output C corresponding to the half cycle added to l. As shown in FIG. 6, the output C of the EXOR gate 21 is input to the control input terminal of the multiplexer 22, so that the output Q of the multiplexer 22 depends on the logic of the most significant bit S5 of the digital signal as shown in FIG. Changes to Therefore, the time when the output Q is “1”, that is,
The pulse width of the PWM signal is as shown in equation (6). (N ′ + 1) × d + S5 × T / 2 = (N + 1 + S5) · d (6) From equation (6), when N = 0, 1, 2,..., 62, 63, the output Q (P
The duty ratio of the WM signal is 1 / 66,2 / 66,…, 64 / 66,65 /
It becomes 66.

As described above, in the fourth embodiment, a ring oscillator 1a is formed by cascading 32 stages of inverters IV1, and the output of the inverter IV1 of each stage and its inverted output are used to generate 64 types of phases. In order to generate different signals, 64 types of PWM can be used without cascading 64 stages of inverters.
A signal can be generated. Therefore, the circuit scale can be reduced and the power consumption can be reduced as compared with the conventional PWM waveform generation circuit. (Fifth Embodiment) In a fifth embodiment, 64 types of PWM signals are generated using a ring oscillator 1b in which 16 stages of inverters are cascaded. FIG. 12 is a block diagram of a fifth embodiment of the PWM waveform generating circuit according to the present invention. The PWM waveform generation circuit shown in FIG. 12 includes a ring oscillator 1b, a 16-input / 1-output multiplexer 2b,
OR gate 21 and 4-input / 1-output multiplexer 22a
And The EXOR gate 21 and the multiplexer 22a constitute a pulse generation unit 50a. The ring oscillator 1b includes 16 cascade-connected inverters IV1, an output terminal of the last-stage inverter IV1, and the first-stage inverter IV1.
And an input terminal of the NAND gate G1. The signal propagation delay time of the NAND gate G1 is set to approximately half the signal propagation delay time of the inverter IV1 in the ring oscillator 1b.

One input terminal of the NAND gate G1 is connected to the output terminal of the last-stage inverter IV1 in the ring oscillator 1b, and the other input terminal is connected to the active terminal. The PWM waveform generating circuit shown in FIG. 12 is characterized in that 64 types of control signals having different pulse widths are output using the 16-stage inverter IV1. FIG. 13 and FIG.
FIG. 3 is a diagram for explaining the basic principle of the PWM waveform generation circuit of FIG.
The signal propagation delay time of each inverter IV1 in the ring oscillator 1b is "2", and the signal propagation delay time of the NAND gate G1 is "1". FIG. 13 shows the magnitude of the phase difference between the inputs of each inverter IV1 with reference to the rise of the output A of the last inverter IV1 in the ring oscillator 1b, and FIG. 14 shows the rise of the output A 'of the NAND gate G1. It shows the magnitude of the phase difference between the inputs of each inverter IV1 on the basis of the downlink. FIGS. 15 and 16 correspond to FIGS. 13 and 14, respectively, and show not the magnitude of the phase difference but the phase order. Assuming that the time when the output A of the ring oscillator 1b rises is "0", as shown in FIG.
The time when the output of the NAND gate G1 falls is “1”. Next, the time when the output of the first-stage inverter IV1 rises is “3”. Similarly, every time the signal passes through the inverter IV1, the signal is delayed by "2" and the phase is inverted.

On the other hand, assuming that the time at which the output of the NAND gate G1 falls is "0", the time at which the output of the first-stage inverter IV1 rises is "2", as shown in FIG. Similarly, every time the signal passes through the inverter IV1, the signal is delayed by "2" and the phase is inverted. 13 and 14, the final stage inverter of the ring oscillator 1b
By taking into account both the case where the output of the inverter IV1 is used as a reference and the case where the output of the NAND gate G1 is used as a reference, the output of the inverter IV1 at each stage in the ring oscillator 1b is reduced by 6%.
Four types of phase differences can be obtained. The fifth embodiment generates 32 types of PWM signals based on the output A of the last-stage inverter IV1 of the ring oscillator 1b and the output B of any one of the 16-stage inverters in the ring oscillator 1b, And the output A 'of the NAND gate and the ring oscillator 1
any one output B of the 16-stage inverter IV1
, And generates 32 types of PWM signals. FIGS. 15 and 16 show the order of the phases instead of the values of the phase differences based on FIGS. The values in the two figures are one greater in FIG. 15 than in FIG. 16 for the same stage number. In general, the higher the stage number, the larger the value.

Hereinafter, the rising edge of the output A of the inverter IV1 at the last stage of the ring oscillator 1b and the falling edge of the output A 'of the NAND gate G1 are referred to as reference edges. Further, a signal selected from the 16 types of outputs of the inverter IV1 at each stage in the ring oscillator 1b is referred to as a selected signal, and a selected one of rising and falling edges of the selected signal is referred to as a selected edge. Based on 32 types of selected edges and 2 types of reference edges in FIGS. 15 and 16, PWM waveforms of 64 types of pulse widths are generated as follows. The least significant bit S0 is 0
In this case, the fall of the output A 'of the NAND gate is used as a reference, and when S0 = 1, the rise of the output A of the last inverter of the ring oscillator is used as the reference. Medium 4 bits, S
An integer determined by 1 to S4 bits is associated with a stage number. For example, when (S4, S3, S2, S1) = (0,0,1,1) = 3, the stage number 3 is selected. If the most significant bit S5 is 0, the phase order is 31 or less, and if the most significant bit S5 is 1, the phase order is 32 or more. If, for example, S0 = 0 and S5 = 1 in the stage number 3, the falling is selected Phase order 39
(In FIG. 15) is selected. Then, a PWM waveform that rises at the same time as the reference edge and falls at the same time as the selected edge is generated. Then, the pulse width of the generated PWM waveform is S
It depends on an integer N determined from 0 to S5, and the pulse width increases as N increases.

FIGS. 17 and 18 are timing charts showing an example of generating a PWM waveform from a reference signal and a selected signal.
FIG. 17 shows the case where S0 = 1. FIGS. 17 (a) to 17
(D) shows the case of (S1, S5) = (0,0) (0,1) (1,0) (1,1) in order. FIG. 17 shows the case where S0 = 1, and the rising edge of A is selected as the reference edge. FIG. 17 (a), 17
In (b), since S1 = 0, the stage number is odd, and the selected signal B has a phase difference of half cycle or more compared to the reference signal A. If S5 is 0, the falling edge of B is 1, if 1 is selected, the rising edge is selected, and the generated PWM waveform is within a half cycle or more than a half cycle, respectively. 17 (c), 17
17D is the same as FIGS. 17A and 17B except that the phase difference is equal to or less than a half cycle. On the other hand, FIG. 18 shows a case where S0 = 0, and the falling of A ′ is selected as the reference signal. FIGS. 18A to 18D show (S1,
S5) = (0,0) (0,1) (1, O) (1,1). This is the same as FIG. 17 except that the falling edge of A ′ is used as the reference edge. FIG. 19 shows the waveforms of FIGS. 17A to 17D in a logical table. FIG. 19 (i) shows FIG.
7 (a), (ii) in FIG. 17 (b), and (iii) in FIG.
17C corresponds to FIG. 17D, and FIG. 17D corresponds to FIG. 17D.
When the least significant bit S0 of the digital signal is “1” and the bit S
When 1, S5 is (0,0), the phase difference order is “1,5,
A PWM signal is generated based on the “9,..., 29” th edge. In this case, the relationship between the outputs A and B and the PWM signal OUT is represented by the following logical expression (7).

OUT = AB (7) When the least significant bit S0 of the digital signal is "1" and the bits S1 and S5 are (0,1), the phase difference order is "33,3".
A PWM signal is generated based on the “7, 41,..., 61” th signal. In this case, the relationship between the outputs A and B and the PWM signal OUT is represented by the following logical expression (8). OUT = A + / B (8) When the least significant bit S0 of the digital signal is “1” and the bits S1 and S5 are (1,0), the phase difference order is “3,
The PWM signal is generated based on the “7, 11,..., 31” th signal. In this case, the relationship between the outputs A and B and the PWM signal OUT is expressed by the following logical expression (9). OUT = A · / B (9) When the least significant bit S0 of the digital signal is “1” and the bits S1 and S5 are (1,1), the phase difference order is “35,3”.
The PWM signal is generated based on the “9, 43,..., 63” th signal. In this case, the relationship between the outputs A and B and the PWM signal OUT is represented by the following logical expression (10). OUT = A + B (10) Similarly, if the waveforms of FIGS. 18 (a) to 18 (d) are represented by a logic table, they are as shown in FIG. (I) of FIG. 20 corresponds to FIG.
(A), (ii) in FIG. 18 (b), and (iii) in FIG.
(C) and (iv) correspond to FIG. 18 (d), respectively.
When the least significant bit S0 of the digital signal is "0",
If 1,5 is (0,0), the phase order is "0,4,8,
.., A PWM signal is generated based on the 28th signal. In this case, the relationship between the outputs A ′ and B and the PWM signal OUT is expressed by the following logical expression.

OUT = / A ′ · B (11) When the least significant bit S0 of the digital signal is “0” and the bits S1 and S5 are (0, 1), the phase difference order is “32”. , 3
A PWM signal is generated based on the “6, 40,..., 60” th signal. In this case, the outputs A 'and B and the PWM signal OUT
Is expressed by the following logical expression (12). OUT = / A ′ + / B (12) When the least significant bit S0 of the digital signal is “0” and the bits S1 and S5 are (1, 0), the phase difference order is “2”.
The PWM signal is generated based on the “6, 10,..., 30” th signal. In this case, the outputs A 'and B and the PWM signal OUT
Is expressed by the following logical expression (13). OUT = / A ′ · / B (13) When the least significant bit S0 of the digital signal is “0” and the bits S1 and S5 are (1,1), the phase difference order is “34,3”.
The PWM signal is generated based on the “8, 42,..., 62” th signal. In this case, the outputs A 'and B and the PWM signal OUT
Is expressed by the following logical expression (14). OUT = / A '+ B (14) Rearranging and rearranging the logic diagrams of FIGS.
It looks like 1. When the bit S0 of the digital signal is “0”, the bit S5 or the output A ′ of the NAND gate G1 is set according to the logic of the bit S1 and the output B of the multiplexer 2b.
The PWM signal is generated by selecting any one of the inverted signals of. When the bit S0 is “1”,
The PWM signal is generated by selecting either the bit S5 or the output A of the ring oscillator 1b according to the logic of the bit S1 and the output B.

FIG. 12 shows a circuit constructed based on FIG. The multiplexer 2b in FIG. 12 selects one of the input signals of the inverter IV1 at each stage in the ring oscillator 1b according to the logic of the bits S1 to S4 of the digital signal. The EXOR gate 21 is connected to the multiplexer 2b
Of the digital signal and the exclusive OR of the bit S1 of the digital signal. The multiplexer 22a selects one of the bit S5, the output A 'of the NAND gate G1, and the output A of the ring oscillator 1b according to the logic of the bit S0 of the digital signal and the output of the EXOR gate 21 to perform PWM. Generate a signal. FIG. 22 is a timing chart of the pulse width modulation waveform circuit of the fifth embodiment shown in FIG. Hereinafter, the operation of the circuit of FIG. 12 will be described based on the timing chart of FIG. In the circuit of FIG. 12, the signal propagation delay time of each inverter IV1 in the ring oscillator 1b is designed to be twice the signal propagation delay time of the NAND gate G1. The signal propagation delay time can be adjusted by the channel length, channel width, wiring length, and the like of the transistor. Ring oscillator 1
b generates a rectangular wave having a duty ratio of 0.5 and a period of TR. Since the ring oscillator 1b is composed of a 16-stage inverter IV1 and a 1-stage NAND gate G1, its period TR
Is represented by equation (15).

TR = (16 × 2d + d) × 2 = 66d (15) where d is the signal propagation delay time of the NAND gate G1, 2d
Is a signal propagation delay time of each inverter IV1 in the ring oscillator 1b. First stage inverter IV of ring oscillator 1b
1 is the inverted signal / A ′ of the input signal A ′.
The output is delayed by d from the output A of the last stage of b, and the multiplexer 2
The output B of b is delayed from the signal / A 'by S'.2d. S ′ is the digital signal S1 to S1 of the multiplexer 2b.
This is the value of S4 and is represented by equation (16). S '= S1 + S2 × 2 + S3 × 2 2 + S4 × 2 3 ... (16) Moreover, all values N of the digital signal S0~S5 are (1
7) It is expressed by the equation. EXOR21 output X of N = S0 + S1 × 2 + S2 × 2 2 + S3 × 2 3 + S4 × 2 4 + S5 × 2 5 ... (17) FIG. 12 is delayed always more than a half cycle than the output A of the final stage of the ring oscillator 1b. The pulse width TH of the PWM signal Q output from the multiplexer 2b is
From equations (15) to (17), equation (18) is obtained. Also, from the expressions (17) and (18), the duty ratio is as shown in the expression (19).

[0033] Thus, in the fifth embodiment, the inverter IV1 is set to 1
The ring oscillator 1b is formed by cascade connection of six stages, and the output of the last-stage inverter IV1 is input to the first-stage inverter IV1 via the NAND gate G1 having a half of the signal propagation delay time of the inverter IV1. Therefore, by using the output of the ring oscillator 1b as a reference, 32 types of P
A WM signal can be generated, and 32 types of PWM signals can be generated based on the output of the NAND gate G1, and a total of 64 types of PWM signals can be generated. Therefore,
As compared with the first embodiment, the circuit scale can be further reduced, and the power consumption can be further reduced. (Other Embodiments) In the above embodiments, it is assumed that the signal propagation delay time of the output A of the final stage of the ring oscillator and the signal propagation delay time of the output B of the multiplexer are the same. However, since the multiplexer is composed of a plurality of stages of gates, the signal propagation delay time of the output B is expected to be longer than the signal propagation delay time of the output A.

To the extent that the oscillation frequency of the ring oscillator is low,
Although there is no particular problem even if there is a difference in the delay time, it is necessary to adjust the delay time when the oscillation frequency is high. FIG.
FIG. 3 is a block diagram showing an example in which a delay circuit 31 is added to the circuit of the third embodiment shown in FIG. The delay circuit 31 delays the output A of the last stage of the ring oscillator 1 so that the signal propagation delay time of the output A is substantially equal to the signal propagation delay time of the output B. Thereby, even if the oscillation frequency of the ring oscillator 1 is high, there is no possibility of malfunction. In each of the embodiments described above, the multiplexer 2
24, an inverter is connected one by one between adjacent input terminals, but as shown in FIG. 24, an odd number of three or more inverters may be connected between adjacent input terminals. This is to prevent an increase in power consumption in the multiplexer due to dulling of each output signal of each inverting means. When such a method is applied to the circuit of the related art, each buffer is composed of, for example, six stages of inverters. Therefore, the present invention also considers that the circuit scale is reduced. The number of inverters connected between the input terminals may be determined according to the manufacturing process, the oscillation frequency, and the like.

In each of the above embodiments, the case where the inverters IV1 are cascaded in 32 stages and the case where they are cascaded in 16 stages are described. However, the number of stages of the inverter IV1 is not particularly limited. 64 types of PWM signals may be generated using the cascaded ring oscillators 1. In addition, the circuit of the present invention may be configured by a circuit other than those of FIGS. 6 and 12 as long as the circuit can realize the logic of FIGS. Further, instead of providing a ring oscillator, as shown in FIG. 25, a clock signal may be externally input to the first-stage inverter of an inverter delay circuit including a plurality of inverters connected in cascade. In the circuit of FIG. 25, the number of inverter stages and the delay time of each inverter are such that the clock signal input to the first-stage inverter and the clock signal output from the last-stage inverter are out of phase by approximately half a cycle. Is adjusted.

[0036]

According to the present invention, a plurality of inverters are cascaded to form an oscillation signal output means, and a pulse width modulation signal is generated based on the output of each inverter means in the oscillation signal output means. The circuit scale can be reduced, and the power consumption can be reduced. Further, by regarding the output of the odd-numbered inverter means in the ring oscillator as a signal whose phase is delayed by more than half a cycle with respect to the output of the ring oscillator, it is not necessary to invert the output of the odd-numbered inverter means. The circuit size can be further reduced. Furthermore, the configuration of the ring oscillator is simplified by providing a pulse generating means capable of generating any one of pulse width modulation signals of twice or four times the number of connection stages of the inverter means in the ring oscillator. And the circuit scale can be reduced,
Power consumption can also be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a PWM waveform generating circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a second embodiment of a PWM waveform generation circuit according to the present invention.

FIG. 3 is a block diagram showing a configuration of a third embodiment of a PWM waveform generation circuit according to the present invention.

FIG. 4 is a circuit diagram showing an internal configuration of a rise detection circuit.

FIG. 5 is a timing chart of each part in the circuit of FIG. 3;

FIG. 6 is a block diagram of a fourth embodiment of a PWM waveform generation circuit according to the present invention.

FIG. 7 is a diagram illustrating a relationship between an input of an inverter IV1 of each stage in the ring oscillator 1a and a phase order of a signal.

FIG. 8 is a timing chart showing an example in which a logical operation is performed between outputs A and B to generate PWM signals having different pulse widths.

FIG. 9 is a logic diagram corresponding to the waveform of FIG. 8;

FIG. 10 is a logic diagram obtained by rearranging FIG. 9;

FIG. 11 is a timing waveform diagram of the output A of the final stage of the ring oscillator, the output C of the EXOR gate, and the output Q of the multiplexer.

FIG. 12 is a block diagram of a PWM waveform generating circuit according to a fifth embodiment of the present invention.

FIG. 13 shows an inverter IV1 at each stage in the ring oscillator 1b.
FIG. 3 is a diagram showing a phase difference between input signals of FIG.

FIG. 14 shows an inverter IV1 at each stage in the ring oscillator 1b.
FIG. 3 is a diagram showing a phase difference between input signals of FIG.

FIG. 15 is a logic diagram corresponding to FIG. 13;

FIG. 16 is a logic diagram corresponding to FIG. 14;

FIG. 17 shows a logical operation performed between the output A of the ring oscillator and the output B of the multiplexer to obtain PWs having different pulse widths.
FIG. 4 is a timing chart showing an example of generating an M signal.

FIG. 18 is a diagram showing an example in which a logical operation is performed between an output A ′ of a NAND gate and an output B of a multiplexer to generate PWs having different pulse widths.
FIG. 4 is a timing chart showing an example of generating an M signal.

FIG. 19 is a logic diagram corresponding to the waveform in FIG. 17;

FIG. 20 is a logic diagram corresponding to the waveform of FIG. 18;

FIG. 21 is a logical diagram in which FIGS. 19 and 20 are arranged.

FIG. 22 is a timing chart of the pulse width modulation waveform circuit of the fifth embodiment shown in FIG.

FIG. 23 is a block diagram showing an example in which a delay circuit 31 is added to the circuit according to the third embodiment shown in FIG. 3;

FIG. 24 is a block diagram showing an example in which three or more odd-numbered inverters are connected between adjacent input terminals.

FIG. 25 is a diagram showing an example in which an external clock signal is input to the first stage of cascade-connected inverters.

FIG. 26 is a block diagram showing a configuration of a conventional PWM waveform generation circuit.

FIG. 27 illustrates an operation principle of a multiplexer.

FIG. 28 is a circuit diagram showing an internal configuration of a change detection circuit.

FIG. 29 is a timing chart of each part in the PWM waveform generation circuit of FIG. 26;

[Explanation of symbols]

 1,1a, 1b Ring oscillator 2,22,22a Multiplexer 3,4 Change detection circuit 5 RS flip-flop 6 Delay circuit 50,50b Pulse generating means G1 NAND gate IV1 Inverter

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Fumito Hatori 1 Tokoba, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside Toshiba Microelectronics Center Co., Ltd.

Claims (22)

[Claims] 1. A pulse width modulation circuit for generating ²ⁿ kinds of pulse width modulation signals having different pulse widths according to a digital signal of n bits (n is an integer of 2 or more). (M is an integer of 2 or more) first inverter means, oscillating signal output means for outputting oscillating signals having different phases from the first inverter means, and at least one of the n-bit digital signals. Selecting means for selecting any one of the signals corresponding to the output signals of the m first inverter means connected in series based on the bits of the section, and selecting the signal in accordance with the signal selected by the selecting means And a pulse means for generating the pulse width modulation signal having a pulse width. 2. The method according to claim 2, wherein said first inverter means of said oscillation signal means is an odd number of stages of inverters, and said selecting means selects k of said n-bit digital signals.
And a multiplexer that selects one of signals according to output signals of the m first inverters connected in series based on logic of = log ₂ m bits. 2. The pulse width modulation waveform generating circuit according to 1. 3. The oscillating signal output means includes a first one of a final one of the m first inverters connected in series.
3. The pulse width modulated waveform generating circuit according to claim 2, wherein the ring oscillator is a ring oscillator that feeds back the output signal of the inverter means to the input side of the first inverter means. 4. The oscillating signal output means inputs an oscillating signal from the outside to the first inverter means of the first stage among the m first inverter means connected in series, The m signal is set such that the phase difference between the oscillation signal input to the first inverter means and the oscillation signal output from the first inverter means at the final stage is substantially 180 °.
3. The pulse width modulation waveform generating circuit according to claim 2, wherein a value of the signal and a signal propagation time of said first inverter means are set. 5. The pulse generation means according to claim 1, wherein said pulse generation means comprises, based on a logic of said digital signal, one of said pulse width modulation signals of the same number as the number of connection stages of said first inverter means in said ring oscillator. 5. The pulse width modulation waveform generation circuit according to claim 3, wherein the pulse width modulation waveform generation circuit generates one of the waveforms. 6. The ring oscillator includes a plurality of second inverters respectively connected to odd-numbered output signals of the first inverter, and the selector includes an even-numbered stage in the ring oscillator. 6. A pulse width modulation waveform generating circuit according to claim 5, wherein one of each output signal of said first inverter means and each output signal of said plurality of second inverters is selected. . 7. A first edge detection circuit for detecting a rising edge and a falling edge of an output of the ring oscillator and outputting an edge detection pulse, and a rising edge of an output of the selection means. A second edge detection circuit that detects an edge and a falling edge and outputs an edge detection pulse; and a set state when an edge detection pulse is output from the first edge detection circuit; And a set / reset circuit which is reset when an edge detection pulse is output from the edge detection circuit, wherein the pulse width modulation signal is output from the set / reset circuit. 3. A pulse width modulation waveform generating circuit according to claim 1. 8. The ring oscillator according to claim 1, wherein said pulse generation means includes an inversion / non-inversion setting circuit for setting whether or not to invert the output of said selection means, based on a logic of a least significant bit of said digital signal. 6. The pulse width modulation signal having a pulse width corresponding to an output timing of the first inverter means of the last stage and an output timing of the inversion / non-inversion setting circuit. Pulse width modulation waveform generation circuit. 9. The inverting / non-inverting setting circuit, wherein the pulse generating means selects the output signal of the odd-numbered first inverter means in the ring oscillator by the selecting means. Means for inverting the output of said means to generate said pulse width modulation signal, and said inverting non-inverting setting when said selecting means selects an output signal of said first inverter means of an even-numbered stage in said ring oscillator. 9. The pulse width modulation waveform generating circuit according to claim 8, wherein said pulse width modulation signal is generated without inverting the output of said selecting means by a circuit. 10. The selector according to claim 1, wherein the selector outputs an output signal of one of an even-numbered stage and an odd-numbered stage of the first inverter in the ring oscillator based on a logic of a most significant bit of the digital signal. selected from among the output signal of the selected inverter means, based on the logic other than the most significant bit of the digital signal, the output of a specific inverter means
The pulse width modulation waveform generating circuit according to claim 5, wherein a signal is selected. 11. When the most significant bit of the digital signal is "1", the selecting means determines that the signal is delayed by more than a half cycle with respect to the output of the ring oscillator, and selects the even-numbered stage. 11. The pulse width modulation waveform generating circuit according to claim 10, wherein an output signal of said first inverter means is selected. 12. The pulse width modulation signal according to claim 1, wherein the pulse generation means is based on the logic of the digital signal and is one of the pulse width modulation signals having twice the number of connection stages of the first inverter means in the ring oscillator. The pulse width modulation waveform generating circuit according to claim 3, wherein one of them is generated. 13. The ring oscillator according to claim 13, wherein said pulse generation means has an inversion / non-inversion setting circuit for setting whether to invert an output of said selection means based on a logic of a least significant bit of said digital signal; 13. The pulse width modulation signal according to claim 12, wherein the pulse width modulation signal having a pulse width corresponding to the output timing of the first inverter means in the last stage and the output timing of the inversion / non-inversion setting circuit is generated. Pulse width modulation waveform generation circuit. 14. The inverting / non-inverting setting circuit, when the selecting means selects an output signal of the odd-numbered first inverter means in the ring oscillator, Means for inverting the output of said means to generate said pulse width modulation signal, and said inverting non-inverting setting when said selecting means selects an output signal of said first inverter means of an even-numbered stage in said ring oscillator. 14. The pulse width modulation waveform generating circuit according to claim 13, wherein the circuit generates the pulse width modulation signal without inverting the output of the selection unit. 15. The pulse generator, when the least significant bit of the digital signal is "0", outputs the output signal of the last inverter of the last stage in the ring oscillator and the odd-numbered stage. The pulse width modulation signal is generated based on the input signal of the first inverter means, and when the least significant bit of the digital signal is “1”, the first stage of the last stage in the ring oscillator. 13. The pulse width modulation waveform generating circuit according to claim 12, wherein said pulse width modulation signal is generated based on an output signal of said inverter means and an input signal of said even-numbered first inverter means. 16. The selecting means selects an input signal of any one of the first inverter means in the ring oscillator based on a logic of a most significant bit of the digital signal. On the basis of the output of the selecting means and the logic of the least significant bit of the digital signal, one of the output signal of the first inverter means at the last stage in the ring oscillator and the most significant bit of the digital signal is determined. 16. The pulse width modulation waveform generating circuit according to claim 15, wherein said pulse width modulation signal is selected to generate said pulse width modulation signal. 17. The pulse width modulation signal according to claim 1, wherein the pulse generation means is based on the logic of the digital signal and is one of the pulse width modulation signals having four times the number of connection stages of the first inverter means in the ring oscillator. The pulse width modulation waveform generating circuit according to claim 3, wherein one of them is generated. 18. The ring oscillator according to claim 18, wherein said pulse generation means has an inversion / non-inversion setting circuit for setting whether to invert an output of said selection means based on a logic of a least significant bit of said digital signal. 18. The pulse width modulation signal according to claim 17, wherein the pulse width modulation signal having a pulse width corresponding to the output timing of the first inverter means in the last stage and the output timing of the inversion / non-inversion setting circuit is generated. Pulse width modulation waveform generation circuit. 19. The inverting / non-inverting setting circuit, when the selecting means selects the output signal of the odd-numbered first inverter in the ring oscillator. Means for inverting the output of said means to generate said pulse width modulation signal, and said inverting non-inverting setting when said selecting means selects an output signal of said first inverter means of an even-numbered stage in said ring oscillator. 19. The pulse width modulation waveform generation circuit according to claim 18, wherein the circuit generates the pulse width modulation signal without inverting the output of the selection unit. 20. The ring oscillator, comprising:
The output signal of the inverter means is inverted to obtain the first
A logic inversion means for inputting the signal to the inverter means, wherein a signal propagation time of the logic inversion means is set to substantially a half of a signal propagation time per one stage of the plurality of first inverter means. Item 18. A pulse width modulation waveform generating circuit according to item 17. 21. The selecting means, based on logic other than the most significant bit and the least significant bit of the digital signal,
Selecting an input signal of the first inverter means of any of the ring oscillators; the pulse generating means based on an output of the selecting means, a least significant bit of the digital signal, and a logic of a next bit; And selecting one of the output signal of the first inverter means at the last stage in the ring oscillator, the output of the logic inversion means, and the most significant bit of the digital signal to generate the pulse width modulation signal. 21. The pulse width modulation waveform generation circuit according to claim 20, wherein the circuit generates the pulse width modulation waveform. 22. When the least significant bit of the digital signal is "0", the pulse generation means outputs the next bit of the least significant bit of the digital signal, the output of the selection means,
The pulse width modulation signal is generated based on the most significant bit of the digital signal and the output of the logic inversion means,
And when the least significant bit of the digital signal is "1", the next bit of the least significant bit of the digital signal;
The pulse width modulation signal is generated based on an output of the selection means, a most significant bit of the digital signal, and an output signal of the first inverter means at the last stage in the ring oscillator. 21. The pulse width modulation waveform generating circuit according to 20.