JP2003142992A - Clock generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a clock signal with a desired duty ratio without requiring a high frequency signal to an output clock frequency. SOLUTION: Clocks with different duty ratios are generated by a delay circuit part A 11, a reset generating part 3 and a latch circuit part A 12 from an input clock inputted to an input clock terminal 1. The clocks obtained by dividing the frequency of the input clock by half through the use of a half frequency dividing circuit 24 is latched by a plurality of delay elements which are delayed by a plurality of delay elements in a delay circuit part B 25. A pulse width detecting part 28 detects a pulse width for the portion of one period of the input clock signal as the number of delay elements from the output signal of a latch circuit part B 27 which is reset by a reset signal generated in the reset generating part B 26. A clock selecting part B 29 selects the clock with the prescribed duty ratio from the output clocks of the latch circuit part A 12 through the use of a clock selecting part B 29 based on the detection result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit.

[0002]

2. Description of the Related Art In recent years, speeding up has progressed in the field of LSI such as read channels, and the duty ratio of the input clock signal of the AD converter to be used has become a problem, and various clock generation circuits for correcting the duty ratio have been proposed. ing.

A conventional clock generation circuit will be described below. FIG. 11 is a block diagram of an example of a conventional clock generation circuit. 101 is a VCO circuit, 102 is a 1/2 frequency dividing circuit, 103 is a logic gate circuit, 104 is a delay element, and 10
Reference numeral 5 is an OR gate, and 107 is a clock output terminal.

The operation of the clock generating circuit configured as above will be described below. VCO circuit 101
The clock oscillated by is divided into ½ by the dividing circuit 102 to become a clock having a duty ratio of 50%. The clock with a duty ratio of 50% output from the frequency dividing circuit 102 is input to the logic gate circuit 103, but due to the difference in current capability between the N-channel transistor and the P-channel transistor forming the logic gate circuit 103. The output clock after passing through the logic gate circuit 103 deviates from the duty ratio of 50%. Therefore, a clock obtained by delaying the output clock of the logic gate circuit 103 whose duty ratio is shifted through the delay element 104 and an original clock that is not delayed are ORed by the OR gate 1
The clock output terminal 107
Output more. By changing the delay value of the delay element 104, the duty ratio of the clock output from the clock output terminal 107 can be adjusted to 50%.

FIG. 12 is a timing chart of signals at various parts of the conventional clock generation circuit of FIG. Figure 12 shows V
The duty ratio of the output clock of the CO circuit 101 is 30%
Is the case. 1 / output clock of VCO circuit 101
When the frequency is divided by 1/2 by the frequency dividing circuit 102, the duty ratio becomes 50%. Even when the duty ratio after passing through the logic gate circuit 103 becomes 30% as shown in FIG. 12, the delay element 104 causes 20% of the clock cycle.
The logic gate circuit 1 is delayed by the OR gate 105.
By taking the logical sum with 03, the duty ratio of the output clock output from the clock output terminal 107 is 5
It becomes 0%.

Further, a cycle measuring circuit for measuring the length of each N cycle that arrives at intervals of an integer multiple of the N cycle of the input clock signal, and an operation for calculating the half length of the N cycle based on the value. The circuit determines the timing position of the signal to be output with a duty of 50%, and the input signal has a duty of 50%.
An example of a waveform shaping circuit that outputs a waveform with a duty of 50% after being output regardless of whether it is one of the above
No. 1-317662.

Further, the clock signal and the duty correction signal are input, and the output of the duty correction circuit for changing the duty ratio of the clock signal by the correction signal is supplied to the control terminal G of the latch circuit in the subsequent stage via the logic gate. Japanese Patent Application Laid-Open No. 05-25982 discloses an example of a semiconductor logic integrated circuit which prevents a latch malfunction due to a parasitic resistance and a parasitic capacitance of a data input wiring when the duty of a clock signal changes.
No. 4 publication.

[0008]

However, in the configuration of the above-described conventional clock generation circuit, the oscillation frequency of the VCO circuit 101 needs to be twice the frequency actually used, so that the VCO circuit 101 oscillates at a high frequency. The effect of noise on the circuit was a problem.

Further, there is a problem that when the deviation of the duty ratio of the output clock of the logic gate 103 becomes large, the duty ratio cannot be adjusted only by changing the delay value of the delay element 104.

Further, in the above-described conventional clock generation circuit or the waveform shaping circuit described in Japanese Patent Laid-Open No. 11-317662, the adjustment of the duty ratio is limited to one, and therefore the input signal is set to the H level of the input clock. When a conversion frequency is changed when using a serial-parallel AD converter that has a sample hold circuit that samples in the pulse section and holds in the L pulse section, and the clock pulse width affects the performance, the performance deteriorates. There was also a problem.

Further, in the above-described conventional clock generation circuit, the current capabilities of the N-channel transistor and the P-channel transistor which form the logic gate circuit 103 change depending on the voltage condition, the temperature condition and the process condition. Even if the duty ratio is adjusted, the duty ratio may shift under other conditions. In the semiconductor logic integrated circuit described in Japanese Patent Laid-Open No. 05-259824, the duty ratio can be corrected by the duty correction signal input from the outside, but the duty correction signal needs to be changed every time the condition changes. Had a point.

The present invention solves the problems of the conventional clock generation circuit described above, and does not require a signal having a frequency higher than the output clock frequency (the former), and obtains a clock having a desired duty ratio (the latter). An object of the present invention is to provide a clock generation circuit capable of performing the above. More specifically, the latter is to provide a clock generation circuit capable of adjusting the duty ratio even if the deviation of the clock duty ratio is large, and further, to provide a plurality of clocks generated according to the usage conditions such as the clock frequency. An object of the present invention is to provide a clock generation circuit capable of selecting an optimum one from duty ratio clocks, and further, an LSI operation condition such as a voltage condition and a temperature condition and an LSI such as a process condition.
It is an object of the present invention to provide a clock generation circuit that can obtain a clock with a predetermined duty ratio even if the manufacturing conditions change.

[0013]

In order to achieve this object, a clock generation circuit according to claim 1 of the present invention includes a delay circuit section for generating a delayed clock signal obtained by delaying an input clock signal, and an input clock signal. A reset generation unit that generates a reset signal in response to the rising edge of the latch signal, and a latch circuit unit that outputs the output clock signal after being latched to the H level by the delayed clock signal and reset to the L level by the reset signal.

According to this structure, both the rising edge and the falling edge of the output clock signal can be generated from the rising edge of the input clock signal.
The duty ratio of the output clock signal can be adjusted regardless of the deviation of the duty ratio of the input clock signal.

According to a second aspect of the present invention, there is provided a clock generation circuit which delays an input clock signal to generate a plurality of delayed clock signals having different delay amounts, and a delay circuit section which responds to a rising edge of the input clock signal. A reset generation unit that generates a reset signal, and a plurality of latch circuits that are latched to H level by one delay clock signal different from each other among the plurality of delay clock signals and reset to L level by the same reset signal;
And a clock selection unit that selects one of a plurality of clock signals having different duty ratios output from the plurality of latch circuits and outputs the selected clock signal as an output clock signal.

According to this configuration, a plurality of latch circuits generate a plurality of clock signals having various duty ratios, and one of the clock signals can be selected by the clock selector, so that the clock frequency and other conditions can be used. It becomes possible to generate a clock having an appropriate duty ratio.

A clock generation circuit according to a third aspect of the present invention is the clock generation circuit according to the second aspect, further comprising a duty ratio selection register capable of externally setting a stored value, and the clock selection section is a duty ratio selection register. It is characterized in that one of the plurality of clock signals is selected according to the stored value of.

With this configuration, it becomes possible to easily select and output a clock having a duty ratio suitable for the conditions of use.

According to a fourth aspect of the present invention, there is provided a clock generation circuit which detects an input clock signal cycle and a plurality of first delay circuits which delay the input clock signal and have different delay amounts. A first delay circuit section for generating a clock signal and a first delay circuit section for generating a first reset signal in response to a rising edge of the input clock signal
Reset generator and a plurality of first latches that are latched to an H level by one different delayed clock signal of the plurality of first delayed clock signals and reset to an L level by the same first reset signal. Circuit,
Of the plurality of clock signals having different duty ratios output from the plurality of first latch circuits, a clock signal having a predetermined duty ratio is selected as an output clock signal based on the cycle detected by the input clock cycle detector. And a clock selection unit for outputting.

According to this structure, the cycle of the input clock signal is detected, and the clock signal having a predetermined duty ratio is selected based on the cycle, so that the operating condition of the LSI such as the voltage condition and the temperature condition and the like. LS such as process conditions
Even if the manufacturing condition of I changes, a clock with a predetermined duty ratio can be obtained.

A clock generation circuit according to a fifth aspect of the present invention is the clock generation circuit according to the fourth aspect, wherein the input clock cycle detection section divides the input clock signal by 1/2 and divides the input clock signal by 1/2. A 1/2 frequency dividing circuit for generating a signal, a second delay circuit section for delaying the 1/2 frequency divided clock signal and generating a plurality of second delayed clock signals having different delay amounts, A second reset generation unit that generates a second reset signal in response to the rising edge of the divided clock signal and one delay clock signal that is different from the plurality of second delay clock signals Different duty ratios output from the plurality of second latch circuits that latch the frequency clock signal and are reset to the L level by the same second reset signal. At the timing when the leading edge of 1/2 frequency-divided clock signal among a plurality of signals Tsu is made of a period calculation unit for determining the period of the input clock signal from the number of H-level signal that becomes. In this way, the input clock cycle detector can be configured.

Further, according to any of claims 1 to 5, the output clock signal having the same frequency as the input clock signal can be generated. Therefore, even when the input clock signal is input from the VCO circuit or the like, the oscillation frequency is the output clock signal. Since it is only necessary to have the same frequency as that of the signal and it is not necessary to oscillate at a high frequency as in the conventional case, it is possible to suppress the influence of noise on surrounding circuits.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
3 is a configuration diagram of a clock generation circuit in the embodiment of FIG. In FIG. 1, 1 is an input clock terminal, 2 is a delay circuit section that delays an input clock signal input from the input clock terminal 1, 3 is a reset generation section that generates a reset signal from the input clock signal, and 4 is a delay circuit section. The latch circuit unit 5 which is latched to the H level by the delayed clock signal output from 2 and reset to the L level by the reset signal output from the reset generation unit 3 is an output clock terminal.

An outline of the operation of the clock generating circuit according to the first embodiment of the present invention configured as above will be described below. The input clock signal input from the input clock terminal 1 is input to the delay circuit section 2 to generate a delayed clock signal. Further, the input clock signal is input to the reset generator 3 to generate a reset signal.
The delayed clock signal and the reset signal are input to the latch circuit unit 4, a clock having a duty ratio corresponding to the delay value of the delay circuit unit 2 is generated, and output from the output clock terminal 5.

FIG. 2 is a detailed circuit diagram specifically showing each part in FIG. In FIG. 2, reference numeral 6 is a delay element A for delaying the input clock, and 7 is a delay element A for determining the position of the rising edge of the generated clock, 7 is a delay element B for delaying the input clock to generate the reset signal, and 8 is a reset signal. An inverter for inverting the input clock in order to generate a reset signal, 9 is a logical sum gate for generating a reset signal from the output of the delay element B7 and the output of the inverter 8, and 10 is an H clock by the delay clock generated by the delay element A6. It is a D flip-flop that is latched to the level and reset to the L level by the reset signal output from the OR gate 9. That is, the delay circuit section 2 of FIG. 1 is composed of the delay element A6, the reset generation section 3 is composed of the delay element B7, the inverter 8 and the OR gate 9, and the latch circuit section 4 is composed of the D flip-flop 10. ing.

FIG. 3 is a timing chart of each part of the detailed circuit of FIG. The input clock input from the input clock terminal 1 is delayed by the delay element A6, and the delayed clock A
Is generated. Delay clock A is D flip-flop 1
The rising edge of the output clock is generated by being input to the clock terminal of 0 and being latched at the H level by the rising edge of the delay clock A. On the other hand, the input clock input from the input clock terminal 1 is delayed by the delay element B7 to generate the delayed clock B. The delay clock B and the inverted signal of the input clock generated by the inverter 8 are input to the OR gate 9 to generate a reset signal. When the reset signal is input to the reset terminal of the D flip-flop 10 and reset to the L level, the falling edge of the output clock is generated.

As described above, according to the present embodiment, both edges of the output clock can be generated from the rising edge of the input clock, so that the duty ratio output from the VCO circuit or the like (not shown) is not clear. Even when the signal is used as the input clock, it is possible to adjust the duty ratio to a desired value according to the delay value of the delay element A6 regardless of the duty ratio of the input clock.

Further, according to the present embodiment, the input clock and the output clock have the same frequency as shown in FIG. 3, and the input clock is input to the input clock terminal 1 from the VCO circuit (not shown). Then, the oscillation frequency of the VCO circuit only needs to be the same frequency as the required output clock, and it is not necessary to oscillate at a high frequency as in the conventional case, so that the influence of noise on the surrounding circuits can be suppressed. it can.

In the present embodiment, the delay element B7 of the reset generator 3 may be divided into the delay element A6 of the delay circuit section 2 and shared with a part thereof. For example, the delay element A6 has a configuration in which a delay element connected to the input clock terminal 1 and having a delay time equivalent to that of the delay element B7 and another delay element (a plurality of delay elements may be connected) are connected in series.
The output of the delay element (shared portion) having the same delay time as 7 may be input to the OR gate 9.

(Second Embodiment) Next, a second embodiment of the present invention will be described. FIG. 4 is a configuration diagram of a clock generation circuit according to the second embodiment of the present invention. In FIG. 4, reference numeral 1 denotes an input clock terminal, 11 denotes a plurality of delay elements having the same delay value, and the input clock terminal 1
A delay circuit section A for generating a plurality of delay clock signals having mutually different delay amounts from an input clock signal input from 3 is a reset generation circuit section for generating a reset signal from the input clock signal, and 12 is a delay circuit section A11. The latch circuit units A and 13 provided with a plurality of latch circuits that are latched to the H level by one of the output delayed clock signals and reset to the L level by the reset signal have a duty ratio from the outside. A duty ratio control input terminal for setting, 14 is a duty ratio selection register for holding the duty ratio, 15
Is a clock selection unit that selects a clock signal having a predetermined duty ratio from a plurality of clock signals having various duty ratios output from the latch circuit unit A based on the value of the duty ratio selection register 14. Output clock terminal.

An outline of the operation of the clock generating circuit according to the second embodiment of the present invention configured as above will be described below. The input clock signal input from the input clock terminal 1 is input to the delay circuit unit A11 to generate a plurality of delayed clock signals. Further, the input clock signal is input to the reset generator 3 to generate a reset signal. The plurality of delayed clock signals generated by the delay circuit unit A11 and the reset signal generated by the reset generation unit 3 are input to the latch circuit unit A12. The plurality of latch circuits of the latch circuit unit A12 are latched at H level by different delayed clock signals and L level by reset signals.
By being reset to the level, clock signals having various duty ratios are generated. On the other hand, the duty ratio control input terminal 13 sets the duty ratio in the duty ratio selection register 14 according to the usage conditions. Based on the duty ratio set in the duty ratio selection register 14, in the clock selection unit 15, a clock signal having the optimum duty ratio for the use condition among the clock signals having various duty ratios output from the latch circuit unit A12. Is selected and output from the output clock terminal 5.

FIG. 5 is a detailed circuit diagram in the second embodiment of the present invention. In FIG. 5, 16, 17, 18,
Reference numeral 19 is a delay element having the same delay value for delaying an input clock, 20, 21, 22, 23 are D flip-flops for generating clock signals having various duty ratios, 13 is a duty ratio control input terminal, 14 Is a duty ratio selection register, and 15 is a clock selection unit. Reference numeral 7 is a delay element B, 8 is an inverter, and 9 is an OR gate, which has the same configuration as the reset circuit 3 in the first embodiment of FIG.

FIG. 6 is a timing chart of each part of the detailed circuit of FIG. When the input clock input from the input clock terminal 1 passes through the delay element 16, it is delayed like the delayed clock 1A. Further, when passing through the delay element 17, a delay clock 2A having a delay twice as long as the delay clock 1A is generated. A delay clock kA is generated when the delay element 18 passes through k delay elements, and a delay clock nA is generated when the delay element 18 passes through n delay elements. Delay clock 1A for D flip-flop 20, delay clock 2
The A flip-flop 21, the delay clock kA latches the D flip-flop 21 and the delay clock nA latches the D flip-flop 23 to the H level, and all the D flip-flops are reset by the reset signal from the reset generator 3. As a result, a signal of Q1 is output from the D flip-flop 20, a signal of Q2 is output from the D flip-flop 21, a signal of Qk is output from the D flip-flop 22, and a signal of Qn is output from the D flip-flop 23, and clocks having n different duty ratios are output. A signal is generated. The generated n clock signals having different duty ratios are input to the clock selection unit 15, the clocks having the duty ratios set in the duty ratio selection register 14 are selected, and output from the output clock terminal 5. For example, in FIG.
= 9, k = 5 and the value of the duty ratio selection register 14 is 50%, Q generated by the delay clock kA
The clock signal of k is selected by the clock selection unit 15 and output.

As described above, according to this embodiment, a plurality of delay elements 16 to 19 and a latch circuit (D flip-flops 20 to 23) generate clock signals having a plurality of different duty ratios and select them. Since it can be output, it is possible to generate a clock signal having an optimum duty ratio according to the usage conditions such as the clock frequency. For example, A
Even when the optimum input clock duty ratio differs depending on the conversion frequency in the D converter or the like, it is possible to supply the clock signal having the optimum duty ratio according to the usage conditions.

Further, according to the present embodiment, the input clock and the output clock have the same frequency as shown in FIG. 6, and the input clock is the VCO as in the first embodiment.
If a circuit (not shown) inputs to the input clock terminal 1, the oscillation frequency of the VCO circuit may be the same frequency as the required output clock, and it is not necessary to oscillate at a high frequency as in the past. , It is possible to suppress the influence of noise on the surrounding circuits.

In the present embodiment as well, as in the first embodiment, the delay element B7 of the reset generation section 3 can be divided into the delay element 16 of the delay circuit section A11 and shared with a part thereof. .

(Third Embodiment) Next, a third embodiment of the present invention will be described. FIG. 7 is a configuration diagram of a clock generation circuit according to the third embodiment of the present invention. In FIG. 7, 1 is an input clock terminal, 3 is a reset generation section, 11 is a delay circuit section A, 12 is a latch circuit section A, 13
Is a duty ratio control input terminal, 14 is a duty ratio selection register, and 5 is an output clock terminal. These have the same configurations as those in the second embodiment. Reference numeral 24 is a 1/2 divider circuit that divides the input clock signal by 1/2 and generates a 1/2 divided clock, and 25 is a plurality of delays having the same delay as the delay element that constitutes the delay circuit unit A11. The delay circuit sections B and 26, each of which is composed of elements, delays the ½ frequency-divided clock output from the ½ frequency-dividing circuit 24 with a plurality of delay elements to generate a plurality of delayed clock signal groups B.
The reset generation units B and 27 that generate the reset signal B from the divided clock latch the ½ divided clock by the delayed clock signal group B and are reset to the L level by the reset signal of the reset generation unit B26. Is provided in the latch circuit section B, 28 is a pulse width detection section for detecting the length of one cycle of the input clock signal from the output signal of the latch circuit section B27, and 29 is the detection result of the pulse width detection section 28. The clock selecting unit B selects a clock signal having a predetermined duty ratio from a plurality of clock signals having various duty ratios output from the clock selection unit B. The input clock cycle detection unit is composed of a 1/2 frequency divider circuit 24, a delay circuit unit B25, a reset generation unit B26, a latch circuit unit B27, and a pulse width detection unit 28 (cycle calculation unit).

The outline of the operation of the clock generating circuit according to the third embodiment of the present invention configured as above will be described below. The input clock signal input from the clock input terminal 1 is input to the reset generation unit 3 and the delay circuit unit A11, and the reset signal and the delayed clock signal group A are generated, respectively. The reset signal and the delayed clock signal group A are input to the latch circuit unit A12, and a clock signal having a plurality of duty ratios is generated. The above is the same as in the second embodiment.

On the other hand, the input clock signal is also input to the 1/2 frequency dividing circuit 24 to generate the 1/2 frequency dividing clock signal. The ½ frequency-divided clock signal is input to the delay circuit section B25, and a plurality of delayed clock signal groups B obtained by delaying the ½ frequency-divided clock are generated. In addition, the 1/2 frequency-divided clock signal is also input to the reset generation unit B, and the reset signal B
Is generated. The delay clock group B and the reset signal B are input to the latch circuit unit B, and the delay clock group B outputs 1
The 1/2 divided clock signal is latched and reset to the L level by the reset signal B. The output signal of the latch circuit unit B27 is input to the pulse width detection unit 28 and detects the length of one cycle of the input clock signal. Pulse width detector 28
The information on the length of one cycle detected by the clock selection unit 2
A clock signal having a predetermined duty ratio is selected from among a plurality of clock signals having various duty ratios which are input to the latch circuit unit A12 and are output to the output clock terminal 5. The predetermined duty ratio is set in the duty ratio selection register 14 from the duty ratio control input terminal 13. This predetermined duty ratio can be set and changed externally via the duty ratio control input terminal 13.

FIG. 8 is a detailed diagram showing in detail the 1/2 divider circuit 24, the delay circuit section B25, the reset generation section B26, and the latch circuit section B27 in the third embodiment of the present invention. In FIG. 8, 1 is an input clock terminal, 30 is a D flip-flop for dividing the input clock by 1/2, and 31, 32, 33 and 34 have the same delay value for delaying the 1/2 divided clock signal. Delay element, 35, 36,
37 and 38 are D flip-flops for latching the 1/2 divided clock signal, 28 is a D flip-flop 35
Pulse width for detecting the H pulse width of the 1/2 divided clock, that is, the number of delay values of the delay element corresponding to the length of one cycle of the input clock signal based on the output signals of It is a detection unit. 7 is a delay element B, 8 is an inverter,
Reference numeral 9 denotes an OR gate, and the reset generation unit B26 configured by these has the same configuration as the reset generation unit 3,
The reset signal B is generated from the 1/2 frequency-divided clock signal.

FIG. 9 is a timing chart of each part of FIG. The input clock signal input from the input clock terminal 1 is frequency-divided by the D flip-flop 30 and is delayed like the delayed clock 1B when passing through the delay element 31.
Further, when passing through the delay element 32, a delay clock 2B having a delay twice as long as the delay clock 1B is generated. When the delay element 33 passes through the j delay elements, the delay clock jB is generated, and when the delay element 34 passes through the m delay elements, the delay clock mB is generated. D flip-flop 35
Latches the 1/2 frequency-divided clock at the rising edge of the delayed clock 1B, resets it to the L level by the reset signal B, and generates the output signal Q1. Similarly, D
The flip-flop 36, the D flip-flop 37, and the D flip-flop 38 latch the 1/2 divided clock at the rising edges of the delay clock 2B, the delay clock jB, and the delay clock mB, respectively, and are reset to the L level by the reset signal B, Output signals Q2 and Q, respectively
j and Qm are generated. The output signals Q1 to Qm of the latch circuit section B27 are input to the pulse width detection section 28.

In the pulse width detection section 28, the 1/2 frequency-divided clock is input from the 1/2 frequency-divided circuit 24, and the output signals Q1 to Q1 are output at the rising edge positions of the 1/2 frequency-divided clock.
It is detected how many Qm are at the H level.
The detected number corresponds to one cycle of the input clock converted by the delay value of the delay element. The number of delay elements corresponding to the length of one cycle of the input clock detected by the pulse width detection unit 28 is input to the clock selection unit B29 and the latch circuit unit A
A clock signal having a predetermined duty ratio is selected from various clock signals output from 12 and output from the clock output terminal 5. For example, in FIG. 9, j = 10
When a clock signal with a duty ratio of 50% is required, if a clock signal generated from the delayed clock signals that have passed through five delay elements in the delayed clock signal group A is selected, a clock with a predetermined duty ratio is selected. You can get a signal.

In FIG. 10, conditions such as voltage conditions, temperature conditions, process conditions, etc. are changed, and the delay value is 1/100 of that in the case of FIG.
It is a timing chart when it becomes 2. The number of delay elements corresponding to one cycle of the input clock changes from j to m. When j = 10 and m = 20, the number of delay elements corresponding to one cycle of the input clock is 20.
A clock signal with a duty ratio of 50% can be obtained by selecting a clock signal generated from the delayed clock signals that have passed through ten delay elements in the delayed clock signal group A, and even if the condition changes, a predetermined clock signal can be obtained. A clock signal having a duty ratio can be obtained.

As described above, according to this embodiment, 1 /
Divide-by-2 circuit 24, reset generator B26, and delay circuit B
25, the latch circuit section B27 and the pulse width detecting section 28 are provided, the pulse width detecting section 28 can detect the number of delay elements corresponding to one cycle of the input clock signal, and a plurality of clocks generated from the number of delay elements can be detected. Since the duty ratio of the clock can be determined, a clock having an optimum predetermined duty ratio is automatically selected even if the operating condition changes.
It can be selected by 29. As described above, since the clock having the predetermined duty ratio can be automatically generated, the optimum clock can be supplied even when the clock duty ratio is affected by the performance of the AD converter or the like.

Also in this embodiment, as in the second embodiment, the input clock and the output clock have the same frequency as shown in FIG. 6, and the input clock is input from a VCO circuit (not shown). If it is inputted to the clock terminal 1, the oscillation frequency of the VCO circuit may be the same frequency as the required output clock, and it is not necessary to oscillate at a high frequency as in the conventional case, so that noise to surrounding circuits is not generated. The influence can be suppressed.

In the present embodiment as well, the delay element B7 of the reset generator 3 is the same as in the first and second embodiments.
It is also possible to divide the delay element 16 of the delay circuit unit A11 and share it with a part thereof. Further, like the reset generation unit 3 described above, the delay element B7 of the reset generation unit B26 can be divided into the delay element 31 of the delay circuit unit B25 and shared with a part thereof.

[0048]

As described above, according to the present invention, the delay circuit section for generating the delayed clock signal by delaying the input clock signal, and the reset generating section for generating the reset signal in response to the rising edge of the input clock signal. And a latch circuit section that is output to the output clock signal by being latched to the H level by the delayed clock signal and reset to the L level by the reset signal to input the clock signal output from the VCO circuit or the like whose duty ratio is not clear. Even in such a case, it is possible to realize an excellent clock generation circuit capable of adjusting the duty ratio regardless of the duty ratio of the input clock signal.

Further, according to the present invention, a delay circuit unit for delaying an input clock signal to generate a plurality of delayed clock signals having different delay amounts, and a reset circuit for generating a reset signal in response to a rising edge of the input clock signal. Output from the generation unit, a plurality of latch circuits latched to H level by one delay clock signal different from each other among the plurality of delay clock signals and reset to L level by the same reset signal, and output from the plurality of latch circuits. By using a clock selection unit that selects one of a plurality of clock signals with different duty ratios and outputs it as an output clock signal, even if the optimum input clock duty ratio differs depending on the conversion frequency in an AD converter or the like, the usage condition Supply clock signal with optimum duty ratio according to Realizes the superior clock generation circuit can Rukoto.

Further, according to the present invention, the input clock cycle detecting section for detecting the cycle of the input clock signal and the first delay clock signal for delaying the input clock signal to generate a plurality of first delayed clock signals having mutually different delay amounts. A delay circuit section, a first reset generation section that generates a first reset signal in response to a rising edge of the input clock signal, and a plurality of first reset generation sections.
Of the same delay clock signals latched to the H level by one of the delay clock signals different from each other.
Of the plurality of first latch circuits that are reset to the L level by the reset signal and the plurality of clock signals that are output from the plurality of first latch circuits and have different duty ratios. By providing a clock selection unit that selects a clock signal having a predetermined duty ratio based on the cycle and outputs it as an output clock signal, a clock having a predetermined duty ratio can be automatically generated. Even when the clock duty ratio is affected by the performance due to the above, an excellent clock generation circuit that can supply an optimum clock is realized.

Further, in any of the inventions, the output clock signal having the same frequency as the input clock signal can be generated. Therefore, even when the input clock signal is input from the VCO circuit or the like, if its oscillation frequency is the same frequency as the output clock signal. Of course, since it is not necessary to oscillate at a high frequency as in the conventional case, an excellent clock generation circuit capable of suppressing the influence of noise on the surrounding circuits is realized.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock generation circuit according to a first embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of a clock generation circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart according to the first embodiment of the present invention.

FIG. 4 is a block diagram of a clock generation circuit according to a second embodiment of the present invention.

FIG. 5 is a detailed circuit diagram of a clock generation circuit according to a second embodiment of the present invention.

FIG. 6 is a timing chart according to the second embodiment of the present invention.

FIG. 7 is a block diagram of a clock generation circuit according to a third embodiment of the present invention.

FIG. 8 is a partial detailed circuit diagram of a clock generation circuit according to a third embodiment of the present invention.

FIG. 9 is a timing chart in the third embodiment of the invention.

FIG. 10 is a timing chart of another example of the third embodiment of the invention.

FIG. 11 is a block diagram of a conventional clock generation circuit.

FIG. 12 is a timing chart of a conventional example.

[Explanation of symbols]

1 Input clock terminal 2 delay circuit section 3 Reset generator 4 Latch circuit section 5 Output clock terminals 6 Delay element A 7 Delay element B 8 inverter 9 OR gate 10 D flip-flop 11 Delay circuit section A 12 Latch circuit section A 13 Duty ratio control input terminal 14 Duty ratio selection register 15 Clock selection section 16, 17, 18, 19 Delay element 20, 21, 22, 23 D flip-flop 24 1/2 divider circuit 25 Delay circuit section B 26 Reset Generator B 27 Latch circuit section B 28 Pulse width detector 30 D flip flop 31, 32, 33, 34 Delay element 35,36,37,38 D flip-flop

Claims (5)

[Claims] 1. A delay circuit section for generating a delayed clock signal obtained by delaying an input clock signal, a reset generating section for generating a reset signal in response to a rising edge of the input clock signal, and an H signal for the delayed clock signal. A clock generation circuit which is latched at a level and reset to an L level by the reset signal and outputs an output clock signal. 2. A delay circuit section for delaying an input clock signal to generate a plurality of delayed clock signals having different delay amounts, and a reset generation section for generating a reset signal in response to a rising edge of the input clock signal. , A plurality of latch circuits which are latched to an H level by one delay clock signal different from each other among the plurality of delay clock signals and reset to an L level by the same reset signal, and are output from the plurality of latch circuits. A clock generation circuit comprising: a clock selection unit that selects one of a plurality of clock signals having different duty ratios and outputs the selected clock signal as an output clock signal. 3. A duty ratio selection register capable of setting a stored value from the outside is provided, and a clock selection unit selects one of a plurality of clock signals according to the stored value of the duty ratio selection register. The clock generation circuit according to claim 2. 4. An input clock cycle detector for detecting a cycle of an input clock signal, and a first delay circuit section for delaying the input clock signal to generate a plurality of first delayed clock signals having different delay amounts. And a first reset generator that generates a first reset signal in response to a rising edge of the input clock signal, and one delayed clock signal different from the other one of the plurality of first delayed clock signals. A plurality of first latch circuits that are latched at a level and reset to an L level by the same first reset signal, and a plurality of clock signals that are output from the plurality of first latch circuits and have different duty ratios. Among them, a clock signal having a predetermined duty ratio is selected based on the cycle detected by the input clock cycle detector, and the output clock signal is selected. A clock generation circuit having a clock selection unit for outputting as a signal. 5. The input clock cycle detection unit delays the 1/2 frequency-divided clock signal by dividing the input clock signal by 1/2 and generates a 1/2 frequency-divided clock signal. A second delay circuit section for generating a plurality of second delayed clock signals having different delay amounts,
A second reset generation unit that generates a second reset signal in response to a rising edge of the ½ frequency-divided clock signal, and one delay clock signal that is different from the other one of the plurality of second delay clock signals. By 1/2
A plurality of second latch circuits that latch the divided clock signal and are reset to the L level by the same second reset signal, and a plurality of second latch circuits that are output from the plurality of second latch circuits and have different duty ratios. 5. The clock generation circuit according to claim 4, further comprising: a period calculation unit that obtains the period of the input clock signal from the number of signals that become H level at the timing when the 1/2 divided clock signal rises.