JP2006115274A - Slight time difference circuit using two plls and time measurement circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a slight time difference circuit and a time measurement circuit, which are capable of improving time resolution by one digit or more. <P>SOLUTION: The slight time difference circuit includes a first phase synchronizing loop circuit provided with a voltage controlled oscillation circuit which receives a prescribed reference clock signal to generate a first oscillation frequency, and a second phase synchronizing loop circuit provided with a voltage controlled oscillation circuit which receives the same reference clock signals as the first phase synchronizing loop circuit to generate a second oscillation frequency different from the first oscillation frequency, and a slight time is obtained from a delay time difference between output signals of the first phase synchronizing loop circuit and the second phase synchronizing loop circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to high-precision time measurement, and more particularly, to a minute time difference circuit and a time measurement circuit using the same.

  In a digital circuit in a scientific measuring instrument, a distance measuring device such as an automobile or an aircraft, an element analyzer using TOF (Time Of Flight), etc., it is necessary to measure the time of the input signal with high accuracy.

  In general, the simplest method of measuring time in a digital circuit is a method of operating a counter using a clock as shown in FIG. 1, and taking the value of the counter at that time into a register when a signal to be measured arrives. . However, the time resolution (minimum time unit) in this case is determined by the clock cycle, and is 10 ns when a 100 MHz clock is used, for example.

In order to perform time measurement in units of time shorter than the reference clock period, for example, a PLL (described in Japanese Patent Application Laid-Open No. 7-283697 “Voltage Controlled Oscillation Circuit and Signal Detector Using the Same” is used. A circuit has been developed that uses a voltage-controlled oscillation circuit in a Phase Locked Loop (phase-locked loop) circuit to obtain a delay signal that is 1 / N of the oscillation period. FIG. 2 is a circuit diagram of such a circuit. The example shown in this figure is a 16-stage delay circuit, and a voltage-controlled oscillation circuit is constituted by the inverting circuits U1 to U16 and US, and the oscillation frequency can be varied by the control voltage (vgn) obtained from the PLL circuit. ing. Further, this circuit is devised so that oscillation can be generated in an even number of stages where oscillation cannot be generated unless an odd number of phase inverting circuits are used, and the rise of the signal is f1 → f2 → f3 →. . . It changes in the order of f16 → f1, and a rising signal having a time interval of 1/16 of the reference clock can be obtained. In this case, the time resolution can be set to 1 / N of the oscillation period, but the resolution cannot be increased more than the delay time of the two inverting circuits. In a normal CMOS circuit, the delay time of the one-stage inverting circuit is about 0.2 ns, so the delay time of the two-stage inverting circuit (= one-stage delay circuit) is about 0.4 ns.
Japanese Patent No. 2666397

  In order to further improve the time resolution method in the conventional circuit as described above, it is necessary to use a higher-speed integrated circuit process technique and increase the clock frequency. However, there is a limit in reducing the delay time of the gate, and there are problems that the power consumption increases and the manufacturing cost becomes high.

  An object of the present invention is to provide a minute time difference circuit and a time measurement circuit capable of overcoming the problems of the prior art as described above and improving the time resolution by one digit or more.

  The minute time difference circuit according to the present invention includes a first phase-locked loop circuit including a voltage-controlled oscillator circuit that receives a predetermined reference clock signal and generates a first oscillation frequency, and the same reference clock signal as the first phase-locked loop circuit And a second phase-locked loop circuit comprising a voltage-controlled oscillation circuit that generates a second oscillation frequency different from the first oscillation frequency, and the first phase-locked loop circuit and the second phase-locked loop circuit A minute time is obtained from the delay time difference between the output signals.

  A time measuring circuit according to the present invention receives a first phase-locked loop circuit including a voltage-controlled oscillator circuit that generates a first oscillation frequency, and the same reference clock signal as the first phase-locked loop circuit, and receives the first oscillation frequency. And a second phase-locked loop circuit including a voltage-controlled oscillator circuit that generates a second oscillation frequency different from the output phase of each of the first phase-locked loop circuit and the second phase-locked loop circuit. A delay line composed of a plurality of variable delay circuits connected in series so that the delay time is controlled by an output signal of an associated phase-locked loop circuit, The first variable delay circuit in each delay line receives one of two signals to obtain a time difference, and the output of the variable delay circuit that changes simultaneously in each delay line By finding, and determining the time difference between the two signals.

  Another time measuring circuit according to the present invention includes a first voltage controlled oscillation circuit comprising a plurality of N1 stage delay circuits, and a first frequency dividing circuit for receiving the output of the first voltage controlled oscillation circuit and multiplying the frequency by a plurality of M1. A first phase-locked loop circuit comprising a phase frequency detector that receives the output of the first frequency divider and the reference clock and feeds back a phase difference between these signals to the first voltage-controlled oscillation circuit; A second voltage controlled oscillation circuit comprising a plurality of N2 stage delay circuits; a second frequency dividing circuit for receiving the output of the second voltage controlled oscillation circuit and multiplying the frequency by a plurality of M2; and an output of the second frequency dividing circuit. And a reference clock, and a second phase-locked loop circuit including a phase frequency detector that feeds back a phase difference between these signals to the second voltage-controlled oscillation circuit; The output of the peripheral circuit is the clock input signal. A latch circuit and a phase selection circuit that receives the external signal and receives an output signal of each stage of the delay circuit in the first voltage controlled oscillation circuit and performs a fine time measurement. First and second delays comprising a plurality of variable delay circuits connected in series so that an output signal is next input for each of the first phase locked loop circuit and the second phase locked loop circuit The delay time is controlled by the output signal of the related phase-locked loop circuit, and the first variable delay circuit in the first delay line rises to the external signal determined by the latch and phase selection circuit. In response to the output signal of the stage of the delay circuit in the first voltage controlled oscillation circuit at the closest timing, the first variable delay circuit in the second delay line is: The latch and phase selection circuit receives the external signal adjusted in delay so as to pass through the signal received by the first delay line in the first and second delay lines, and receives the first and second delays. It is characterized in that the ultrafine time measurement is performed by checking which delay circuit output in the line the signal arrival time is reversed.

  In a conventional time measuring circuit using a PLL element in an integrated circuit, it has not been possible to obtain time accuracy equal to or less than the delay time of the delay circuit. According to the present invention, even if the delay times of the delay circuits used in the two voltage controlled oscillation circuits are similar to those of the prior art, the time difference is further reduced to an integer N / N of the delay time. can do. As a result, it is possible to generate a signal with a smaller time difference and perform time measurement.

  FIG. 3 is a block diagram showing an example of the configuration of the minute time difference circuit according to the present invention. The minute time difference circuit 1 includes a first phase-locked loop (PLL) circuit 2, a second PLL circuit 3, and a double delay line unit 4.

The first PLL circuit 2 includes a voltage controlled oscillation circuit (VCO) 21, a frequency dividing circuit 22, and a phase frequency detector (PFD) 23. The VCO 21 is composed of an N1 stage delay circuit, and the oscillation output signal is frequency-divided by a frequency dividing circuit 22 to a frequency of 1 / M1 and input to the PFD 23. A reference clock having a period T0 is also input to the PFD 23. The PFD 23 detects a phase difference between these two input signals and feeds back the phase difference voltage signal vgn1 to the VCO 21. By changing vgn1, the output signal of the frequency dividing circuit 22 is frequency-phase synchronized with the reference clock. If the output period of the VCO 21 at this time is T1,

T1 = T0 / M1 (1)

It becomes. Further, the delay time TD1 per stage of the VCO 21 is that the VCO 21 is composed of an N1 stage delay circuit.

TD1 = T1 / N1 (2)

It becomes.

The second PLL circuit 3 has the same configuration as the first PLL circuit 2, and includes a voltage controlled oscillation circuit (VCO) 31, a frequency divider circuit 32, and a phase frequency detector (PFD) 33. The VCO 31 is composed of an N2 stage delay circuit, and its output is frequency-divided by a frequency dividing circuit 32 to a frequency of M1 / 2 and input to the PFD 33. A reference clock having the same cycle T0 as that input to the PFD 23 of the first PLL circuit 2 is also input to the PFD 33. The PFD 33 detects a phase difference between these two input signals and feeds back the phase difference voltage signal vgn2 to the VCO 31. By changing vgn2, the output signal of the frequency dividing circuit 32 is frequency-phase synchronized with the reference clock. If the output period of the VCO 31 at this time is T2,

T2 = T0 / M2 (3)

It becomes. Also, the delay time TD2 per stage of the VCO 31 is that the VCO 31 is composed of an N2 stage delay circuit.

TD2 = T2 / N2 (4)

It becomes.

The time difference ΔT between TD2 and TD1 is obtained from the equations (2) and (4).

ΔT = TD2-TD1
= T2 / N2-T1 / N1

It becomes. Substituting equations (1), (2) and (3) into this,

ΔT = T0 / (M2 · N2) −T1 / N1
= (T1 / M1) / (M2 / N2) -T1 / N1
= (T1 / N1) ((N1 · M1) / (M2 · N2) -1)

It becomes. For simplicity, assuming that N1 = N2 = M2 = N and M1 = N + 1,

ΔT = T1 / (N · N) = TD1 (1 / N) (5)

Thus, a time difference of 1 / N of the oscillation period T1 of the VCO 21 and 1 / N of the delay time TD1 of the delay circuit is obtained.

Similarly, if N1 = N2 = M2 = N and M1 = N + 2,

ΔT = TD1 (2 / N)

Thus, a time difference of 2 / N of TD1 is obtained. In addition, it is possible to realize an arbitrary ΔT by appropriately selecting values of N1, N2, M1, and M2.

  As described above, the conventional circuit can obtain only a delay of TD1, but the minute time difference circuit according to the present invention can obtain a delay of an integer N / N of the value. In particular, if N is selected to be a power of 2, the subsequent digital processing can be made very easy. For example, in equation (5), if N = 16, T1, TD1, and ΔT each have a value that is 16 times different.

  In order to actually use the time difference obtained in this way, the double delay line unit 4 is used. DAx and DBx (x = 1, 2, 3,...) Are the same as the variable delay circuits used in the VCO 21 and VCO 31, and are composed of two inverting elements. At this time, if a circuit that finds the tap x in which the signals s1_x and s2_x change simultaneously (T1x = T2x) is used, the time difference between s1_0 and s2_0 can be known with ΔT accuracy.

  Although a very fine time measurement can be performed using a minute time difference signal obtained by a minute time difference circuit as shown in FIG. 3, if this circuit alone covers a wide time range, the circuit scale becomes too large. Since the time accuracy also deteriorates, it is usually preferable to adopt a circuit configuration combined with a counter and a voltage controlled oscillation circuit as in the conventional example shown in FIGS. FIG. 4 is a block diagram showing an example of the configuration of such a time measuring circuit according to the present invention. This time measuring circuit includes a first PLL circuit 41, a second PLL circuit 42, a double delay line unit 43, a latch and phase selection circuit 44, and a counter circuit 45.

  The first PLL circuit 41 and the second PLL circuit 42 may have the same configuration as that of the first PLL circuit 2 and the second PLL circuit 3 shown in FIG. 3. The frequency circuit 50 and the PFD 51 may be the same as the VCO 21, the frequency divider circuit 22, the PFD 23, the VCO 21, the frequency divider circuit 22, and the PFD 23 shown in FIG. 3.

  In this embodiment, as an example, a 10 MHz clock is used as a reference clock used for the first PLL circuit 41 and the second PLL circuit 42. This frequency is first raised to 170 MHz, 17 times, by the first PLL circuit 41. Using this 170 MHz clock, the counter circuit 45 performs coarse time measurement with a resolution of 5.9 ns (= 1/170 MHz).

  Next, using the delayed signal outputs f1 to f16 obtained from the 16-stage VCO 46 constituting the first PLL circuit 41, the latch and phase selection circuit 44 performs fine time measurement with a resolution of 368 ps (= 5.9 ns / 16). I do.

  On the other hand, in the second PLL circuit 42, since the frequency division is set to 1/16, it oscillates at 160 MHz and the delay time per stage is 391 ps (= 1/160 MHz / 16). Therefore, the double delay line unit 43 performs measurement in units of time of ΔT = 391 ps-368 ps = 23 ps. As described above, the coarse time measurement, the fine time measurement, and the ultrafine time measurement are performed with different resolutions of 5.9 ns / bit, 368 ps / bit, and 23 ps / bit, respectively, by 16 times.

  Next, a latch and phase selection circuit 44 that performs fine time latching and phase selection for extracting a signal to be supplied to the double delay line unit 43 from the output signal of the first VCO 41 will be described. FIG. 5 is a circuit diagram showing an example of the configuration of the latch and phase selection circuit. First, an external signal is latched in the flip-flop by the f1 to f16 signals from the first VCO 46. The output of the first stage flip-flop may become unstable for a short time depending on the timing of the change of the external signal, so it can be stabilized by the second stage flip-flop whose phase is shifted by 180 degrees from the first stage clock. Latch. This output becomes minute time data, and by taking this logical sum, the signal at the closest timing (after 180 degrees from the rise of the external signal) can be selected from f1 to f16 (cout). The external signal is output as hout after the delay is adjusted. In this delay adjustment, the cout signal is adjusted so as to pass the hout signal within the double delay line unit 43. In this delay adjustment, a delay circuit similar to DAx and DBx in FIG. 3 can be used.

  Finally, the output of the flip-flop in the double delay line unit 43 is latched, and an ultrafine time measurement is performed by checking at which tap position the signal arrival time is reversed.

  The numerical values shown in the above embodiments are merely examples for clarifying the explanation, and the present invention is naturally not limited thereto.

It is a figure explaining the example of a time measurement by the conventional counter. It is a figure explaining the time measuring circuit using the conventional PLL. It is a block diagram which shows an example of a structure of the micro time difference circuit by this invention. It is a block diagram which shows an example of a structure of the time measurement circuit by this invention. It is a circuit diagram which shows an example of a structure of a latch and a phase selection circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Minute time difference circuit 2, 41 1st PLL circuit 3, 42 2nd PLL circuit 4, 43 Double delay line part 21, 31, 46, 49 VCO
22, 32, 47, 50 Frequency divider 23, 33, 48, 51 PFD
44 Latch and phase selection circuit 45 Counter circuit

Claims (3)

  A first phase-locked loop circuit including a voltage-controlled oscillator circuit that receives a predetermined reference clock signal and generates a first oscillation frequency; receives the same reference clock signal as the first phase-locked loop circuit; A second phase-locked loop circuit including a voltage-controlled oscillation circuit that generates a second oscillation frequency different from the first phase-locked loop circuit, and a minute time from a delay time difference between output signals of the first phase-locked loop circuit and the second phase-locked loop circuit A minute time difference circuit characterized by obtaining.   A first phase-locked loop circuit including a voltage-controlled oscillator circuit that generates a first oscillation frequency, and a reference clock signal that is the same as that of the first phase-locked loop circuit, and generates a second oscillation frequency that is different from the first oscillation frequency A second phase-locked loop circuit including a voltage-controlled oscillation circuit, wherein the output signal is input in series with respect to each of the first phase-locked loop circuit and the second phase-locked loop circuit. A delay line comprising a plurality of connected variable delay circuits, each variable delay circuit in each delay line being controlled in delay time by the output signal of the associated phase locked loop circuit, the first variable delay in each delay line; The circuit receives one of the two signals to be timed and finds the output of the variable delay circuit changing simultaneously in each delay line, thereby Time measuring circuit, characterized in that to determine the time difference between the signals.   A first voltage controlled oscillation circuit comprising a plurality of N1 stage delay circuits; a first frequency dividing circuit for receiving the output of the first voltage controlled oscillation circuit and multiplying the frequency by a plurality of M1; and an output of the first frequency dividing circuit. And a reference clock, and a first phase-locked loop circuit including a phase frequency detector that feeds back a phase difference between these signals to the first voltage-controlled oscillation circuit, and a second circuit comprising a plurality of N2 stage delay circuits. A voltage-controlled oscillation circuit; a second frequency-dividing circuit that receives the output of the second voltage-controlled oscillation circuit and multiplying the frequency thereof by a plurality of M2; an output of the second frequency-dividing circuit and a reference clock; And a second phase locked loop circuit including a phase frequency detector that feeds back the phase difference to the second voltage controlled oscillation circuit, and an external signal, and an output of the first frequency divider circuit as a clock input signal. Perform rough time measurement And a latch and a phase selection circuit for receiving an output signal of each stage of the delay circuit in the first voltage controlled oscillation circuit and performing a fine time measurement. Each of the circuit and the second phase-locked loop circuit comprises first and second delay lines comprising a plurality of variable delay circuits connected in series such that an output signal is next input, respectively, and related phase lock The delay time is controlled by the output signal of the loop circuit, and the first variable delay circuit in the first delay line is determined by the latch and phase selection circuit, and the first voltage at the timing closest to the rising edge of the external signal. The first variable delay circuit in the second delay line is received by the latch and the phase selection circuit in response to the output signal of the delay circuit stage in the control oscillation circuit. An output of which delay circuit in the first and second delay lines is received by receiving the external signal whose delay is adjusted so as to pass through the signal received by the first delay line in the first and second delay lines. A time measuring circuit which performs ultrafine time measurement by checking whether the arrival time of the signal is reversed in FIG.

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