JPH03109096U

JPH03109096U -

Info

Publication number: JPH03109096U
Application number: JP1532890U
Authority: JP
Priority date: 1990-02-19
Filing date: 1990-02-19
Publication date: 1991-11-08

Description

[Brief explanation of drawings]

第１図は本考案の時間測定回路の一実施例の構
成を示すブロツク図、第２図〜第４図は本実施例
の動作を説明するためのタイミングチヤート（第
３図および第４図は要部の拡大チヤート）であり
、第２図は時間測定の全体動作を、第３図はスタ
ート端数時間ＴＲの検出動作を、第４図はストツ
プ端数ＴＰの検出動作をそれぞれ示し、第５図は
端数測定により分解能を高めた時間測定回路の従
来例の構成を示すブロツク図、第６図は従来例の
動作を説明するためのタイミングチヤートである
。１……カウンタ、２……スタート端数ラツチ、
３……ストツプ端数ラツチ、４……ＲＳフリツプ
フロツプ、５……アンドゲート、６……遅延素子
、７……遅延回路、８……時間算出回路（ＣＰＵ
）、Ｔ１〜Ｔｎ……遅延信号（遅延信号用タツプ
）、ＣＬ……基準クロツク、ＳＲ……スタート信
号、ＳＰ……ストツプ信号、ＴＲ……スタート端
数時間、ＴＰ……ストツプ端数時間、ＴＣ……計
数時間、ＴＳ……測定値。 FIG. 1 is a block diagram showing the configuration of one embodiment of the time measurement circuit of the present invention, and FIGS. 2 to 4 are timing charts for explaining the operation of this embodiment (FIGS. 3 and 4 are Fig. 2 shows the overall operation of time measurement, Fig. 3 shows the detection operation of the start fraction time TR, Fig. 4 shows the detection operation of the stop fraction TP, and Fig. 5 shows the operation of detecting the stop fraction TP. 6 is a block diagram showing the configuration of a conventional example of a time measuring circuit with improved resolution through fractional measurement, and FIG. 6 is a timing chart for explaining the operation of the conventional example. 1...Counter, 2...Start fraction latch,
3... Stop fractional latch, 4... RS flip-flop, 5... AND gate, 6... Delay element, 7... Delay circuit, 8... Time calculation circuit (CPU
), T1 to Tn...delay signal (tap for delay signal), CL...reference clock, SR...start signal, SP...stop signal, TR...start fractional time, TP...stop fractional time, TC... ...Counting time, TS...Measurement value.

Claims

[Claims for Utility Model Registration] A clock counting type time measuring circuit that uses a reference clock with a predetermined frequency and performs measurement with a higher precision than the resolution determined by the frequency of the reference clock, which starts time determination. When the start signal SR that determines the timing is input, the reference clock CL
a counter 1 that starts counting the number of t and determines the end timing of time measurement when a stop signal SP is input, stops the counting and outputs the count value as a count counting time; and a predetermined delay time t. The delay element 6 having n(n
is a natural number of 2 or more) connected in series, the reference clock CL is inputted from one open end of the delay line, and the amount of delay obtained by passing through each delay element 6 is different. n delayed signals T1~
a delay circuit 7 that outputs Tn, and latches the n delay signals T1 to Tn in parallel as digital data according to their voltage levels at the input timing of the start signal SR;
A start fraction latch 2 outputs the latched digital data as a start fraction time, and a voltage level of the n delay signals T1 to Tn is connected in parallel as digital data corresponding to the voltage level at the input timing of the stop signal SP. A time measurement circuit comprising a stop fraction latch 3 for latching and outputting the latched digital data as a stop fraction time.