JPH03235527A - A/d converter - Google Patents

Abstract

PURPOSE:To attain high accurate measurement of an analog quantity and high speed waveform analysis by counting an output of a V/F converter sequentially for a prescribed time at plural counters and outputting the result of a count of a counter whose count is finished as a digital value while other counter makes counting. CONSTITUTION:When an output signal from a V/F converter 10 is counted for a prescribed time by a counter 13, other counter 14 starts count for a prescribed time. The result of count is switchingly outputted as a digital value corresponding to an analog signal in the order from the counter whose count is finished. Thus, desired accuracy of digital conversion is implemented even at a short sampling interval without use of a high speed counter especially and high accurate measurement of an analog quantity and high speed waveform analysis are attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Industrial Application Field of the Present Invention The present invention relates to an A/D converter that converts an analog signal into a digital value corresponding to its magnitude.

<Prior Art> (Fig. 4) Conventionally, A/D converters have used V/F converters because they are relatively simple and inexpensive.

FIG. 4 is a block diagram showing the configuration of this V/F conversion type A/D converter.

In Figure 4, 1 is the voltage of the input analog signal.
A V/F converter that outputs a pulse signal with a frequency F that is proportional to It is configured as follows.

2 is a counting circuit that counts the frequency of the pulse signal from this V/F converter 1, and this pulse signal is passed through an AND circuit 4 by the gate pulse from the gate signal generation circuit 3, and is counted by N bits for a predetermined period of time. It is input to the counter 5, and the count result is latched by the latch circuit 2116 and output as a digital value.

In addition, 7 is a latch pulse generation circuit that outputs a latch pulse that is slightly different from the falling edge of the gate pulse, and 8 is a latch pulse generation circuit that outputs a reset pulse that lags behind the latch pulse but precedes the rising edge of the gate pulse, and controls the counter 5. This is a reset pulse generation circuit for resetting.

Therefore, if the analog voltage (2) changes, the count value latched by the latch circuit 6 will also change in accordance with the change.

Problems to be solved> However, in the A/D converter with the above configuration,
For example, in order to obtain 16-bit resolution, a fairly long gate time of approximately 32 ms (64/2 MHz) is required, and when performing both high-precision measurement of analog images and waveform analysis, it is necessary to use analog images that contain high frequency components. There is a problem in that it is not possible to accurately examine changes in the signal.

Therefore, it is possible to shorten the gate time to, for example, 1/8, or 4 milliseconds, to speed up sampling, and at the same time increase the obtained count value by 8@ to achieve 16-bit accuracy. In this case, the time required to reset the counter 5 must be made so short that it can be ignored with respect to the period of the highest frequency pulse signal output from the V/F converter 1.

That is, since the number of pulses input within this reset time is not included in each count result, the result of adding this count value includes a large error, resulting in a significant decrease in accuracy.

For this reason, it is conceivable to use high-speed elements such as ECL, which can be expected to operate at high speed, but such high-speed elements are expensive, generate a lot of heat, and must deal with new problems such as drift1-. The problem is that it is difficult.

An object of the present invention is to provide an A/D converter that solves this problem.

Means for Solving the Problems> In order to solve the above problems, the A/D converter of the present invention includes: a V/F converter that outputs a signal with a frequency proportional to the magnitude of the analog signal; A plurality of counters capable of counting output signals from the F converter, a counter input switching means for inputting the output signal from the V/F converter to a different counter every time a predetermined time elapses, and counting for a predetermined time is completed. and counter output switching means for sequentially switching and outputting the counting results of the counter as digital values for analog signals.

Effect> Therefore, when the output signal from the V/F converter is counted by one counter for a predetermined time, the other counter starts counting for a predetermined time.

Starting from the counter that has finished counting, the counting results are switched and output as digital values corresponding to analog signals.

Embodiments of the present invention> (Figures 1 and 2) An embodiment of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing the configuration of an A/D converter according to an embodiment.

In FIG. 1, numeral 10 is a V/F converter that outputs a pulse signal with a frequency proportional to the analog voltage ■; for example, a synchronous V/F converter whose output pulse is output in synchronization with the clock signal from the crystal valve mW11. /F converter, the above-mentioned V/F
Similar to converter 1, it outputs pulses with a frequency of 0 Hz to 2 MHz for analog voltages of 0 volts to 10 volts.

Reference numeral 12 denotes an input changeover switch that selectively inputs the pulse signal from the V/F converter 10 to the first counter 13 or the second counter 14 depending on the level of the switching signal. In addition,
The first and second counters 13 and 14 are 12-bit binary counters.

15 is a switching signal generation circuit that divides the clock signal from the crystal oscillator 11 and outputs an input switching signal whose level is inverted every millisecond, for example, and 17 is a switching signal generation circuit that inverts this input switching signal with an inverter 16. This is a write pulse generation circuit that outputs a suppression pulse delayed by a short time d1 from the rising and falling edges of the output switching signal.

Reference numeral 18 denotes an output changeover switch that selectively outputs either the output of the first counter 13 or the output of the second counter 14 according to the level of the output changeover signal. This output changeover switch 18 operates in the opposite direction to the input changeover switch 12, and the first
When the second counter 13 is counting, the second counter 14
When the second counter 14 is counting, the output of the first counter 13 is selected and output.

Reference numeral 19 is a circuit for resetting the counter that has finished counting by delaying the enrichment pulse by a short time d2.

20 is a multiplication circuit that outputs the cumulative value of a predetermined number (32) of consecutively input counting results, and a shift register 21 that sequentially stores the counting results from the output changeover switch in synchronization with the write pulse. and an adder 22 that adds the contents stored in the shift register 21.

Note that the digital value stored in this shift register 21 is a value obtained by counting pulse signals of a maximum of 2 MHz for 1 millisecond, so it has a resolution of "2000", that is, 11 bits, at a size of a.

Next, the operation of this A/D converter will be explained.

When an analog signal is applied to the V/F converter 10, a pulse signal with a frequency proportional to the signal voltage is output to the input changeover switch 12.

Here, when the input switching signal shown in (a) of FIG. 2 rises at 11 o'clock and the input changeover switch 12 is switched to the first counter 13 side, the count value of the first counter 13 is changed to the value shown in (b) of the same figure. It increases from zero as shown in .

When the level of the input switching signal becomes "L" level at 12 o'clock,
The input selector switch 12 is switched to the second counter 14 side, and as shown in FIG.
counting starts from zero. At this time, the output of the first counter 13 is the counting result C1 from T1 o'clock to 12 o'clock.
is retained and output.

While the second counter 14 is counting, the output switching signal is
As shown in (d) of the figure, the count result CI of the first counter 13 is outputted to the shift register 21 because it becomes "H" level, and as shown in (e) of the figure, from 12:00 to d
The counting result is C! due to the dust inclusion pulse delayed by j. will be stored in the shift register 21.

When d2 hours have elapsed since this concussion pulse, the ("
) is output to the first counter 13, so the first counter 13 is reset to zero as shown in (b) of the figure.

At 13:00, 1 millisecond has elapsed since 12:00, the input switching signal becomes "L" level again, the first counter 13 starts counting, and after a delay of "d" from 3:00, the counting result of the second counter 14 is displayed. C2 is stored in the shift register 21, and after a further delay of d2, the second counter 14 is reset to prepare for the next count.

Thereafter, the count values for every millisecond are sequentially stored in the shift register 21 in the same manner.

For example, 32 counting results C1 to C are stored in the shift register 21.
32 is stored, the output of the adder 22 becomes a digital value corresponding to the voltage magnitude of the analog signal for 32 milliseconds from time T to time T.

Note that the output of the V/F converter 10 and the input switching signal are synchronized and the switching time is short, so each counting result is continuous and does not include counting errors. , the addition lI result will have 16-bit precision.

When the next subtraction result C is stored in the shift register 21, the output of the adder 22 becomes a digital value corresponding to the magnitude of the analog voltage for 32 milliseconds from 12 o'clock to 1 o'clock, and so on. A 16-bit accurate digital value corresponding to the analog signal can be obtained every millisecond.

<Other Embodiments of the Present Invention> (Fig. 3) In the above embodiment, continuous counting results are stored in the shift register 21 and added to a predetermined number (32), so that a digital signal with a resolution of 16 bits is generated. However, when performing waveform analysis or the like, all the counting results for the analysis time can be stored in a storage circuit and read out with a resolution as required.

In addition, in the example marked #, the counting results from 11 pips to 1 resolution were added as they were, but as shown in Figure 3, the counting results are each multiplied by 25 (5 "0"s are added to the bottom). Then, Ml! It is also possible to obtain 16-bit resolution by adding 11 consecutive 16-bit counting results of 1 (arbitrary) in the adder 22- and averaging the addition results in the 1/M divider 23. can.

Further, in the above embodiment, two counters are alternately switched, but the output of the V/F converter may be counted by sequentially switching 3@ or more counters.

Effects of the Invention> As described above, the A/D converter of the present invention has a plurality of counters that sequentially count the output of the V/F converter for a predetermined period of time. Since the counting result can be output as a digital value while other counters are counting, it is possible to perform digital conversion with the desired precision even at short sampling intervals without using a particularly high-speed counter. This enables high-accuracy measurement and high-speed waveform analysis.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a timing diagram for explaining the operation of the embodiment,
FIG. 3 is a block diagram showing a part of another embodiment, and FIG. 4 is a block diagram showing the configuration of a conventional device. 10... V/F converter, 12... Input selector switch, 13... First counter, 14
...Second counter, 18...Output selector switch, 20...Reply for the product. Patent applicant: Anritsu Corporation

Claims (1)

[Claims] A V/F converter that outputs a signal with a frequency proportional to the magnitude of an analog signal; a plurality of counters capable of counting output signals from the V/F converter; Counter input switching means for inputting the output signal from the F converter to a different counter every time a predetermined time elapses; and counting results of the counter after counting for the predetermined time;
An A/D converter comprising: a counter output switching means for sequentially switching and outputting a digital value for the analog signal.