JPH0783980A - Jitter/wander analyzer - Google Patents

Abstract

PURPOSE:To provide a jitter/wander analyzer which can accurately, efficiently measure and analyze a jitter, a wander reduced in its frequency. CONSTITUTION:A measuring unit 10 has a measurement signal generator 11, a reference oscillator 12, a frequency converter 13, a multiplier 14, a jitter adding circuit 15, a switching circuit 16, first and second continuous period measuring circuits 17, 18, first and second buffer memories 19, 20, and first and second frequency dividers 21, 22. The circuits 17, 18 continuously measure a period of a signal to be measured. The variations in data of signal periods undergo fast Fourier transform in an arithmetic analyzer 30 to analyze a jitter and analyzes a relative jitter from time interval measured value of the two signals to be measured. On the other hand, frequencies of the signals to be measured are suitably divided by the dividers 21, 22 to analyze its low frequency jitter, and a wander is analyzed by simultaneously calculating MTIE(maximum time interval error) and long frequency deviations at a plurality of observation times.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a jitter analyzer for analyzing the fluctuation (fluctuation) of the pulse width of a signal under measurement, that is, jitter, and an MTIE (MAXIMUM T
Jitter with both functions of wander analysis device that analyzes wander, which is a long-term phase fluctuation due to IME INTERVAL ERROR)
More particularly, the present invention relates to a wander analysis apparatus, in which various quantities in a time / frequency domain of a pulse-shaped signal under measurement, such as a period and a time interval, are continuously measured, and the amplitude and frequency components of jitter and wander by MTIE are measured from the measured quantities. The present invention relates to a jitter / wander analysis device that can analyze a signal with high accuracy and efficiency.

[0002]

2. Description of the Related Art In digital communication networks represented by architectures such as ISDN and SONET / SDH, jitter and wander are considered to be major factors that hinder realization of high quality and large capacity high speed transmission. Jitter is IT
The U / TS (former CCITT) recommendation defines the amplitude amount and frequency component, and similarly, the wander defines the maximum value of MTIE with respect to the observation time.

Generally, in a transmission communication system, a PLL (phase locked loop) having a relatively low gain is used for recovering a received clock. Therefore, the jitter of the high frequency component is suppressed to some extent by the PLL, but the jitter and wander of the low frequency component that cannot be completely removed by the PLL become a problem in actual operation. Furthermore, SONET / SDH, which will be important as a social infrastructure in the future, has a function of inserting and removing a pointer at the beginning of a transmission frame in order to maintain synchronization at a network interface.
In (asynchronous transfer mode), it has a function of transmitting the reference frequency information of the connection source to the connection destination by the time stamp and reproducing the reference frequency of the connection source at the connection destination, but these new synchronization technologies are also new and new. Low frequency jitter (1μ
(Hz to 10 Hz) and wander, and there is concern about lowering the frequency of jitter.

[0004]

[Problems to be Solved by the Invention]
Transmission analyzers are known to be capable of analyzing the jitter of pulsed signals under measurement. This digital transmission analyzer is a test device for measuring transmission error and jitter, and is mainly composed of a transmitting section and a receiving section. Although the receiver has a jitter measuring function, it can be said that it is possible to measure the jitter amplitude and the occurrence frequency when a certain jitter amplitude value is exceeded, and there is no frequency component analyzing function. Because, when performing the frequency component analysis of the jitter with this digital transmission analyzer, the method other than the method of setting the jitter frequency of the output signal at the transmitter and measuring the jitter amplitude at that time at the receiver This is because it is not possible to perform continuous jitter frequency component analysis from low frequency to high frequency. Further, the lower limit of the setting range of the jitter frequency is about 10 Hz to 100 Hz, which is insufficient for low frequency jitter analysis, and cannot be measured for wander.

[0005] Further, conventionally known SONET / SDH analyzers are generally mainly used for function tests, but some models are capable of jitter / wander analysis. Like this digital transmission analyzer, this model consists of a transmitter and a receiver, which sets the jitter frequency and amplitude at the transmitter and measures the jitter amplitude at the receiver. The lower limit of the jitter frequency setting region is as low as 1 Hz. Therefore, the jitter analysis is possible up to 1 Hz, but 1 Hz is still insufficient. There is also a wander measurement (MTIE) function in the observation period from 100 msec (0.1 sec) to 100 sec. However, this observation period is only a part of the range of the ITU / TS recommendation of observation period, and it is extremely insufficient.

At present, the MTIE observation period which is clarified by the ITU / TS recommendation is in the range of 50 msec to 10 ⁹ sec, but in the range of 50 msec to 500 sec and 500 sec to 10 ⁹ sec.
It is divided into two stages in the range of seconds. 50msec to 1 of them
0 range up to ⁷ seconds is important as wander from reality of the observation period (G.811 Recommendation). Therefore, the above 0.1
It is impossible to measure wander with high accuracy during the observation period from second to 100 seconds.

An object of the present invention is to measure and analyze a jitter having a lowered frequency with high accuracy, and to measure and analyze a wander by MTIE recommended by ITU / TS with high accuracy and efficiency. It is to provide a jitter / wander analysis device capable of performing

[0008]

According to the present invention, one edge of a pulsed signal to be measured is provided, and a first continuous cycle measuring circuit for continuously measuring the cycle of the edge, and a pulsed signal. A second continuous cycle measuring circuit for continuously measuring one cycle of the edge of the measurement signal or one edge of a test signal having a predetermined frequency of a reference phase generated inside the device, and continuously measuring the cycle of the edge; A first for storing measurement cycle data output from the first and second continuous cycle measurement circuits
And a second memory, and a measurement amount calculation for calculating various amounts of time / frequency including at least the period and the time interval of the signal under measurement, based on the measurement period data stored in the first and second memories. Means, analyzing means for analyzing various amounts of time / frequency of the calculated measured signal, and selectively dividing the measured signal input to the first and second continuous cycle measuring circuits. First and second frequency dividing means are provided, and it is possible to measure the periods of two signals under measurement simultaneously and continuously by the first and second continuous period measuring circuits. The jitter frequency spectrum of each signal under measurement can be simultaneously obtained from the result of analyzing the amount of change of each measured value calculated by the measured amount calculating means with respect to the elapsed time by fast Fourier transform. Ah .

Further, the measurement amount calculating means calculates a time interval value between both signals from each cycle measurement value, and the analyzing means changes the time interval value calculated by the measurement amount calculating means with respect to the elapsed time. The relative jitter frequency spectrum can be obtained from the result of analysis by performing a fast Fourier transform on the quantity. Further, the first and second frequency dividing means divides the signal under measurement to an appropriate frequency, and the frequency division period is measured by the first and second continuous period measuring circuits, whereby the entire measurement time is measured. And a relatively low jitter frequency spectrum of the signal under measurement can be obtained from the result of analyzing the amount of change of the measured value calculated by the measured amount calculating unit with respect to the elapsed time by fast Fourier transform by the analyzing unit. It was made possible.

Further, the signal to be measured and the test signal having a predetermined frequency of the reference phase are frequency-divided by the first and second frequency dividing means respectively to appropriate frequencies so that their frequencies coincide with each other, and each frequency division is performed. The period of the frequency signal is measured by each of the first and second continuous period measuring circuits, the measurement amount calculating means calculates the time interval value between the two signals from each frequency division period measurement value, and the analyzing means The maximum value and the minimum value are calculated from the time interval value between the two signals calculated by the measurement amount calculating means, and the MTIE and the long-term frequency deviation at a plurality of observation times are calculated from them at the same time. This is to enable efficient analysis of wander, which is a phase fluctuation.

Further, a jitter adding means for adding jitter to the test signal having a predetermined frequency of the reference phase and outputting the jitter added test signal to the outside is provided, and an arbitrary waveform that can be set by the user from the jitter adding means. By outputting a jitter-added test signal of frequency or frequency to an external device under test and inputting an output signal from the device under test as a signal under test, it is possible to analyze the jitter suppression effect or jitter tolerance of the device under test. It is the one.

Further, a terminal for outputting a test signal having a predetermined frequency of the reference phase to the outside is provided, and a pure test signal having no jitter is output from the terminal to an external device under test to be tested. By inputting the output signal from the device as the signal under measurement, the jitter generated only in the device under test can be analyzed.

[0013]

According to the above configuration of the present invention, the jitter frequency of the signal under measurement is analyzed based on the result of the fast Fourier transform of the amount of change of the measured value calculated by the measured amount calculator with respect to the elapsed time, which is analyzed by the analyzer. Since the spectrum can be obtained, continuous jitter frequency component analysis from low frequency to high frequency can be performed with high accuracy. Also,
By dividing the measured signal to an appropriate frequency by the frequency dividing means, low frequency jitter can be sufficiently analyzed, and regarding wander, the wander by MTIE recommended by ITU / TS is emphasized. The measurement can be performed with high accuracy and efficiency over the observation period of 50 msec to 10 ⁷ sec.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of an embodiment of a jitter / wander analysis apparatus according to the present invention. The jitter / wander analysis apparatus according to the present embodiment can continuously and highly accurately measure various quantities in the time / frequency domain of a pulse-shaped signal under measurement, such as a period and a time interval, and at the time of data acquisition. Reveal the time,
The statistical calculation of these various quantities, the frequency distribution, the change with respect to the elapsed time, the MTIE calculation, and the jitter frequency component can also be accurately analyzed, and the measurement unit 10, the calculation analysis unit 30,
The control unit 40, the display unit 50, and the operation unit 60 are roughly classified. The control unit 40, the display unit 50, and the operation unit 60 are a bus 70.
The measurement unit 10 and the calculation analysis unit 30 are connected to each other via the.

The measuring section 10 includes a measurement signal generation circuit 11, a reference oscillator 12, a frequency conversion circuit 13, and a multiplication circuit 14.
A jitter adding circuit 15, a switching circuit 16, and a first
And second continuous cycle measuring circuits 17 and 18, first and second buffer memories 19 and 20, and first and second frequency dividers 21 and 22. The jitter / wander analysis apparatus of the present embodiment analyzes the jitter by using the period measurement value of the continuous period measurement circuit. Since the present analyzer is provided with the two continuous cycle measuring circuits 17 and 18, it is possible to input two signals under measurement and perform a jitter analysis for each signal. As long as the continuous period measuring circuit allows the measured signal, the period is continuously measured without any idle time. Also,
It is also possible to input two signals under measurement and analyze the relative jitter with respect to one input from the measured value of the time interval. In this case, for the time interval measurement value, the time interval between the two continuous cycle measurement circuits 17 and 18 is derived from the elapsed time that is the integration of the cycle measurement values, and the value is analyzed.

On the other hand, since a long measurement time is required to analyze the low frequency jitter, the frequency of the signal under measurement is appropriately divided internally by the frequency dividers 21 and 22 in this analyzer.
Low frequency jitter is analyzed by lengthening the individual measurement value acquisition interval and lengthening the overall measurement time. For example, if the signal to be measured is 2048 KHz and the capacity of the buffer memories 19 and 20 is 1 M words, the frequency division ratio and measurement time are as follows: Frequency division ratio measurement value acquisition interval Total measurement time 1 488 ns 488 ms 2 977 ns 977 ms 41 .95 μs 1.95s 8 3.91 μs 3.91s 16 7.81 μs 7.81s 32 15.63 μs 15.63s, which enables analysis of long-period jitter.

Further, this analyzer can analyze a wander by MTIE recommended by ITU / TS.
In this case, as in the wander measurement example in the Recommendation, both the measured signal and the internal test signal before adding jitter are divided by the frequency divider 2
The frequency is divided into 4 KHz by 1 and 22, and the continuous period of both is measured. The measured cycle value is temporarily stored in the buffer memory 19,
Although stored in 20, the operation analysis unit 30 calls the cycle measurement values from the buffer memories 19 and 20 as sequentially as possible, and adds the count value by the counting clock and the fraction time measurement value to calculate the time interval value. , The maximum value and the minimum value of the time interval measurement value within the observation time set by the user are obtained and stored in the memory (the system memory of the CPU is used because the number of data is relatively small) and all measurements are performed. After the value acquisition is completed, the MTIE for each observation time is calculated and displayed as data and a graph.

At this time, the measurement value acquisition interval time is 250 μm.
Since it is s, the maximum observation time can be set up to 250 s with the buffer memory capacity of 1 M words. Therefore, in order to solve this problem, the writing to the buffer memory is performed after writing the data at the final address. The address counter is rotated so as to return to the head address. Since the measurement value acquisition interval time is relatively slow at 250 μs, the CPU can successively read data without accumulating measurement values, and thus the address can be cycled.

Further, in the present analyzer, a test signal containing jitter can be generated inside the device, and the test signal added with this jitter is subordinate to a device under test, such as a network clock supply device. It is input as a signal, and its dependent synchronous output is input as a signal to be measured to this analyzer, and the jitter and MTIE are analyzed to check the unnecessary jitter output of the device under test, the jitter suppression effect, and the jitter tolerance performance. You can check.

The measurement signal generation circuit 11 is constructed so as to be able to independently receive the two inputs (input 1 and input 2) sent via the first and second frequency dividers 21 and 22, respectively. , A pulse-shaped first signal under test (input under test 1) is supplied as an input 1 to the measurement signal generation circuit 11 via the first frequency divider 21, and is also a pulse signal. Pulse-shaped second measured signal (measured input 2) or the test signal of the reference phase from the frequency conversion circuit 13 before the jitter is added is selected by the switching circuit 16 and supplied as the input 2 to the measured signal generation circuit 11. To be done. The measurement signal generation circuit 11 determines the edge input sequence of the two signals under measurement. As will be described later, the measurement signal generation circuit 11 is configured to be able to simultaneously measure two different signals under measurement with respect to the cycle.

The switching circuit 16 inputs two signals to be measured to analyze the respective jitters or to analyze the relative jitters, and the movable contact c is connected to the first fixed contact a and The input 2 is supplied as the input 2 to the measurement signal generation circuit 11 via the second frequency divider 22. On the other hand, during the wander measurement, the movable contact c is connected to the second fixed contact b, and the reference phase test signal supplied from the reference oscillator 12 via the frequency conversion circuit 13 is used as the second frequency divider 22.
Is supplied as an input 2 to the measurement signal generation circuit 11 via. The switching circuit 16 selects either the external measured signal (measured input 2) or the internal reference phase test signal according to a command (control signal) from the control unit 40, and outputs the second frequency divider 22. Send to. The switching circuit 16 may be a mechanical switch such as a relay or a logical switch using a gate.

When analyzing the jitter of a relatively high frequency, the first frequency divider 21 inputs the measured input 1 to the measurement signal generation circuit 11 without dividing it. On the other hand, when analyzing low-frequency jitter and wander, the measured input 1 is divided and input to the measurement signal generation circuit 11. The second frequency divider 22 divides the test signal of the reference phase before adding the jitter, which is supplied through the switching circuit 16, into 4 KHz and inputs it to the measurement signal generating circuit 11. Of course, like the first frequency divider 21, when the switching circuit 16 is connected to the measured input 2 side, this measured input 2 is divided as necessary and input to the measurement signal generation circuit 11. To do. First above
The second frequency dividers 21 and 22 are configured by programmable frequency dividers so that the frequency division ratio can be switched according to the measurement conditions.

The reference oscillator 12 is the time base of this analyzer and uses an oscillator having an extremely stable frequency, for example, a crystal oscillator in a constant temperature oven. An external reference signal, for example, an external reference frequency signal synchronized with UTC (Coordinated Universal Time) is supplied to the reference oscillator 12 as necessary to synchronize the oscillation frequency. The output signal of the reference oscillator 12 is supplied to the frequency conversion circuit 13, and its frequency is converted into the frequency of the test signal. At the same time, the output signal of the reference oscillator 12 is also sent to the multiplication circuit 14 and its frequency is multiplied to generate the counting clock for the continuous period measuring circuits 17 and 18.
It is supplied to these continuous cycle measuring circuits 17 and 18. The test signal from the frequency conversion circuit 13 has a reference phase at the time of wander measurement, and is supplied as the input 2 to the measurement signal generation circuit 11 via the switching circuit 16 and the second frequency divider 22 as described above. . Further, the test signal from the frequency conversion circuit 13 is output to the outside as a pure test signal without jitter for use in various tests and measurements, and
The test signal to which the jitter is added is also supplied to the jitter adding circuit 15 and is output to the outside for use in various tests and measurements.

The jitter adding circuit 15 artificially generates, for example, jitter generated in various devices or transmission lines, or within a range permitted by ITU / TS, and can be set by a user. A jitter-added test signal obtained by adding the jitter of the waveform and frequency to the test signal of the reference phase from the frequency conversion circuit 13 is output. In this case, the jitter adding circuit 15 generates the jitter adding test signal by using the reference phase test signal from the frequency conversion circuit 13 as the data input and the external clock input. The jitter adding test signal from the jitter adding circuit 15 is input to a device under test such as a jitter removing circuit, or a device under test such as a network clock supply device in an exchange or a transmission device, and their output signals are measured. By inputting as a signal to this analyzer, the jitter suppression effect and jitter tolerance of the device under test can be analyzed.
It is possible to check the output of unnecessary jitter.

In FIG. 2, a test signal (without jitter and addition of jitter) is supplied from this analyzer to a network clock supply device (device under test) in a switch or a transmission device, and an output signal from this device under test is received. An example of the circuit configuration in the case where the jitter suppression effect and the jitter tolerance of the device under test are analyzed and the unnecessary jitter output is checked by inputting the measurement signal to the present analysis device is shown. The frequency of the output clock signal of the network clock supply is generally
1544 KHz (North America, Japan, some Southeast Asian countries)
Or 2048 KHz (countries other than these countries), this is input to the measurement signal generation circuit 11 via the first frequency divider 21 as the measured input 1. The frequency division frequency is determined to be 4 KHz because the wander measurement system diagram at 4 KHz is published as an example in the ITU / TS recommendation document, and it goes without saying that other frequency division frequencies may be used. . When analyzing a jitter having a relatively high frequency, the output clock signal is directly input to the measurement signal generation circuit 11 without being divided.

In the above-mentioned structure, the switching circuit 16 is connected to the measured input 2 side, and the pulse signals as the measured inputs 1 and 2 are the first and second frequency dividers 21 and 22, respectively.
When it is supplied to the measurement signal generation circuit 11 via the, the first and second continuous cycle measurement circuits 17 and 18 rise the pulse signals of the measured inputs 1 and 2 determined by the measurement signal generation circuit 11. Either the edge signal (positive edge) or the falling edge (negative edge) is continuously supplied, and the generation cycle of the edge of the supplied measured edge signal is continuously measured. The measurement result (periodic data) is sent to the first and second buffer memories 19 and 20 through the data lines 17D and 18D, and the write pulse is sent through the write lines 17W and 18W. These buffer memories 1
9 and 20 write measurement data sent through the data lines 17D and 18D and write lines 17W and 18W
It is stored without omission by the write pulse supplied through. The number of data to be stored is preset by the user through the operation unit 60. The calculation analysis unit 30 in the next stage calculates various amounts of time / frequency using the measurement result here.

First and second continuous cycle measuring circuits 17, 18
May have the same configuration, and the period measurement will be performed as shown in FIG. 3 when the positive edge of the measured input 1 is supplied to the first continuous period measurement circuit 17 as a typical example. Be seen. For example, one measured period P1k, which is the time between the positive edge E11 at the time T11 of the input 1 and the positive edge E12 at the next time T12, is calculated from the edge E11, which is the beginning of the period P1k, as shown in FIG. Time t1 to the second counting clock, time t2 from the edge E12 which is the rear end of the period P1k to the second counting clock, and time t
Time N obtained by multiplying the number N of counting clocks included from the end of 1 to the end of time t2 by the period T0 of this clock.
If T0 is obtained, the relationship of P1k + t2 = NT0 + t1 is established, so that it can be calculated as P1k = NT0 + t1-t2.

Here, the second counting clock from the edge is selected because the edge and the first counting clock are extremely close to each other when the first counting clock is selected.
This is because it may not be possible to perform highly accurate time measurement of t1 and t2. If the highly accurate measurement of times t1 and t2 can be performed, the first counting clock immediately after the edge may be selected. Needless to say.

First and second continuous cycle measuring circuits 17, 18
Is the time t1 of the data calculated as described above.
Data (corresponding to time) Np1K T0, Np2K obtained by multiplying the number Np1k, Np2k of count clocks included from the end of the count clock to the end of time t2 by the period T0 of this count clock.
Since T0 is a digital value, it is output as it is.
Difference between fractional times t1 and t2 (t1 -t2)
ΔVp1K and ΔVp2K obtained by converting (referred to as a fractional quantity) into a voltage and then converting this into a digital value with an analog-digital converter (A / D converter) are used for the data lines 17D and 18D.
It is output to the first and second buffer memories 19 and 20 through D. The k of the count values Np1k and Np2k is k = 1 to m.
And m is the number of measurements set by the user. Also,
The integrated value of the measurement results of this continuous cycle becomes the time at the time of data acquisition. Therefore, the time of data acquisition can be measured without omission.

Further, when measuring relative jitter and wander, it is necessary to calculate the time interval value from the difference between the period data acquisition times of the two continuous period measuring circuits 17 and 18, so the measurement start time of both is calculated. Need to match. The measurement signal generation circuit 11 supplies, for example, the positive edge of the signal under measurement of 4 KHz as the input 1 to the first continuous cycle measurement circuit 17, and as the input 2 the positive edge of the test signal of 4 KHz without jitter as the second input. When inputting to the continuous cycle measuring circuit 18, as shown in FIG. 4, after the measurement is started, the second continuous cycle measuring circuit 18 changes the rising edge of the measured signal to the rising edge of the test signal only immediately after the measurement is started. A sequence is assembled in the measurement signal generation circuit 11 so as to measure. That is, the measurement is started from the rising edge of the signal under measurement of the input 1, and the second continuous cycle measuring circuit 18 measures the time P21 from this measurement start time to the first rising edge of the test signal at time T21, and the initial time offset Value (P2
1) Save as and set the measurement start time.

As described above, the first and second buffer memories 19 and 20 store the cycle data measured by the first and second continuous cycle measuring circuits 17 and 18 without omission. The number of data stored in the buffer memories 19 and 20 is preset by the user through the operation unit 60. The data stored in the buffer memories 19 and 20 is used to measure various amounts in the time / frequency domain of the signal under measurement, for example, the period, the time interval, and the statistical calculation, frequency distribution, and progress of these various amounts. It is used by the operation analysis unit 30 in the next stage in order to analyze changes with respect to time, MTIE operation, and jitter frequency components.

In this embodiment, the calculation analysis unit 30 includes the first and second fractional quantity addition units 31 and 32 and the measured amount calculation unit 3.
3 and an analysis calculation unit 34. The first and second fraction quantity adding units 31 and 32 are digital values (ΔVp1k, ΔV) of fraction quantity time voltage that cannot be measured by the counting clock.
p2k) is converted to time domain data, and the cycle data (Np1k T0, Np2k T0) based on the counting clock is added to the converted data based on the above-mentioned calculation formula to obtain the final cycle data (P1k, P2k). ) Is calculated. That is, P1k = Np1k T0 + ΔVp1k P2k = Np2k T0 + ΔVp2k As an example, the fractional quantity time t1−t2 is ΔTns, Np1k
And Np2k as N and ΔVp1k and ΔVp2k as ΔV,
In the A / D converter of the continuous cycle measuring circuits 17 and 18, the number of digital bits of the voltage for the fractional quantity time is 12 bits,
When the period T0 of the counting clock is 10 ns, ΔT =
At −20, −10, 0, +10, +20 ns, the voltages of the sample hold circuits of the continuous cycle measuring circuits 17 and 18 described later are −2048, −1024, 0, +102.
4, +2048 mV, the output of the A / D converter (Δ
V) is 0, 1024, 2048, 3072, 4096 counts, the period P (= P1k = P2) to be obtained.
k) is P = NT0 + ΔT = NT0 + (ΔV-2048) T0 / 1024 = T0 (N + ΔV-2048) / 1024 If T0 = 1000, then P = 1000 (N-2 + ΔV / 1024), and A / D conversion Almost 1 if the instrument has 1-bit precision
It is possible to measure up to 0 ps. 10 ns = 10
To obtain 24 mV, C, R, or the voltage of the integrator of each fractional-time measuring circuit may be set appropriately.

The measured quantity computing unit 33 is composed of the fractional quantity adding units 31, 3
The final period data obtained in 2 is used to calculate the period Pnk of the signal under measurement, the time interval Tk, and the acquisition time of the measurement data. Here, n is an input channel number (the channel to which the measured input 1 is supplied is the input channel 1, the measured input 2 or the channel to which the test signal is supplied is the input channel 2), k = 1 to m, and m is Indicates the number of measurements set by the user. Below, the period Pnk of the signal under measurement and the time interval Tk
A method of calculating is described.

Input channel 1 of the measurement signal generation circuit 11,
Two channels of measured signals (input measured 1,
The period Pnk when the input 2 to be measured or the test signal without jitter is supplied is the first and second fractional quantity adding units 31, 32.
According to the above formula, the period of the signal under measurement (input 1) of the input channel 1 is calculated as P1k, and the period of the signal under measurement (input 2) of the input channel 2 is calculated as P2k. These cycles are shown in FIG. As is clear from FIG. 5, the period of the signal under measurement can be simultaneously measured for the two systems of signals under measurement supplied to both input channels.

Next, the case of measuring the time interval between the signal under measurement supplied to the input channel 1 and the signal under measurement supplied to the input channel 2 will be described. The difference between specific edges of two signals of the same rate is referred to herein as a "time interval". This time interval Tk is obtained by subtracting the time of the positive edge T1k (representative example) of the input 1 from the time of the positive edge T2 (k + 1) of the input 2 (representative example), as is clear from FIG. Can be calculated by That is, Tk = T2 (k + 1) -T1k, where T2 (k + 1) = T2k + P2 (k + 1), T1k = T1 (k-1) +
Since it is P1k, the periods P1k and P2 (k +
The time interval Tk can be calculated from 1) and the positive edge occurrence times T1 (k-1) and T2k.

The time / frequency quantities calculated by the measurement quantity calculator 33 as described above, ie, the period and the time interval in this embodiment, are analyzed by the analysis calculator 34 as needed. The main analysis method is as shown in the block of Fig. 1.
These are statistical calculation, frequency distribution, time change (change with respect to elapsed time), MTIE calculation, and jitter frequency component analysis. These analysis methods will be briefly described below.

The statistical calculation analysis method is based on the mean, variance, sample variance, standard deviation, sample standard deviation, maximum value, minimum value, Allan variance, √Allan variance, normalization, ± offset, constant multiplication and division of the calculated data. It is an analysis. In the frequency distribution analysis method, as shown in FIG. 7, the measured amount, for example, the period Pk (may be a time interval) is plotted on the horizontal axis, and the vertical axis is the number (frequency) at which the period Pk is obtained, and the frequency distribution is displayed. Then, the analysis is performed.

In the time change analysis method, as shown in FIG. 8, the horizontal axis represents the elapsed time tk and the vertical axis represents the measured amount, for example, the period Pk.
Then, the change state of the period Pk with respect to time is displayed,
It is an analysis. Next, MTIE (MAXIMUM TIME
INTERVAL ERROR, maximum time interval error) calculation will be described.

In the wander measurement, the minimum value is subtracted from the maximum value of the time interval value within the observation time set by the user, and this is taken as MTIE. The observation time range set by the user is set to a range of 50 msec to 10 ⁷ sec in the analysis apparatus of this embodiment in consideration of the recommendation of ITU / TS and the reality of the measurement time. In order to briefly explain the MTIE calculation example, in the following description, the observation time is set stepwise in decade units except for 50 msec. Detailed observation time can be set.

The MTIE of the observation time less than or equal to the set observation time can also be calculated in the following manner, and the MTIE of different observation times can be calculated and graphed in one measurement. Example of user setting of observation time: 5 × 10 ^-2 s, 10
^{-1 s, 10 0 s, 10} +1 s, 10 +2 s, 10 +3 s, 10
⁺⁴ s, 10 ⁺⁵ s, 10 ⁺⁶ s, 10 ⁺⁷ s Below is an example of the case where the maximum observation time is set to 10 ⁺⁷ s. a) The shortest observation time after the start of measurement, 5 × 10 ^-2 s
The maximum value Xmax (1) and the minimum value Xmin (1) of the time interval values at the time when the time has elapsed are detected and stored in the memory. The measurement continues as it is. b) The maximum value Xmax (2) and the minimum value Xmin (2) of the time interval after 5 × 10 ⁻² s, that is, 10 ⁻¹ s after the start of measurement, are detected and stored in the memory. . The measurement continues as it is. c) After a further 9 × 10 ^-1 s course, that detects the maximum value Xmax of the time interval at the time of the 10 ⁰ s passed since the start of measurement and (3) the minimum value Xmin (3), stored in the memory. The measurement continues as it is. d) In the same manner, the maximum value Xmax (n) and the minimum value Xmin (n) of the time interval values at each observation time are detected and stored in the memory until the maximum value 10 ⁺⁷ s of the set observation time has elapsed. To do. e) After that, the minimum value Xmin (n) is subtracted from the maximum value Xmax (n) of each observation time to calculate MTIE, and a graph of observation time vs. MTIE as shown in FIG. 9 is displayed.

MTIE = Xmax (n) -Xmin (n) f) Further, the long-term frequency deviation (Δf / f) is calculated from the MTIE thus calculated. Δf / f = MTIE / observation time In the jitter frequency component analysis method, the amount of change in the measured period or time interval with respect to the elapsed time is fast Fourier transformed by the FFT unit (fast Fourier transform unit) to derive the jitter frequency spectrum. It is an analysis. However, since the measured amount data obtained by this device is not measured at fixed time intervals, the interpolator measures the measured amount data and its acquisition time data at a fixed interval using an interpolation method. Convert to measured data.

As an example of the interpolation method in this interpolation section, the first and second fractional quantity addition sections 31 of the operation analysis section 30 will be described.
Each measurement cycle data obtained by _{32 P 1, P 2, P} 3 ·
··············, these period data is obtained by adding the measured values up to that time in each measurement cycle, and P ₁ = t ₁ , P ₁ + P
₂ = t ₂ , P ₁ + P ₂ + P ₃ = t ₃ , ... Are stored in an elapsed time memory (not shown). These t ₁ , t
₂ , t ₃ , ... Indicates the time from the start of measurement,
The measured value P ₁ of the cycle is obtained at time 0, the measured value P _{2 of the} cycle is obtained at time t ₁ , and the measured value P _{3 of the} cycle is obtained at time t _2. Become. From these, the change over time in the period Pk is shown. For example, as shown in FIG. 10A, the measured values Pk are obtained at unequal time intervals.

From these measurement cycle data Pk,
Calculate the periodic data Psk that can be considered to be obtained at intervals by the interpolation unit
To do. For example, in FIG. 10A, an equal time interval from time 0
Sample points S₀ , S₁ , S₂ When the cycle is measured at
Use the linear interpolation method that is the easiest to use for the periodic data that can be regarded.
Ask. The eight measurement period data Pk are (tk, Pk
 ) Coordinates 1 (0, P₁ ), 2 (t₁ , P₂ ), 3 (t₂
 , P₃ ), 4 (t₃ , P_Four ), ... 8 (t₇ , P
₈ ) Can be represented. Sample point S₀ Of course is P₁ Good.
Sample point S₁ Is calculated as follows. That is, in FIG. 10B
3 points (t₁ , P ₂ ), (S₁ , Ps₁), (T₂ , P
₃ ), And a straight line 44 passing through) is P = At + B, A = (P₂ -P₃ ) / (T₁ -T₂ ) B = (t₁ P₃ -T₂ P₂ ) / (T₁ -T₂ ). This A, B and S₁ Substituting and into the equation of the straight line, Ps₁= S₁ (P₂ -P₃ ) / (T₁ -T₂ ) + (T₁ P
₃ -T₂ P₂ ) / (T₁ -T₂ ) And sample point S₁ Period Ps₁Is required. Similarly,
Period Ps₂, Ps₃, Ps_FourAsk for.

The thus obtained periodic data Psk (data indicated by x in FIG. 10A) at equal time intervals is subjected to fast Fourier transform in the FFT section. By displaying the frequency spectrum of this conversion result on a display (not shown) of the display unit 50, for example, the display shown in FIG. 10C is obtained. From this, the frequency component of the fluctuation (jitter) of the period Pk can be known. At this time, the value of the period Pk or its average value can be displayed simultaneously, or the frequency spectrum can be displayed as a ratio to Pk. Further, the percentage of the jitter period can be calculated. In order to improve the accuracy of the periodic data Psk that can be regarded as obtained at equal time intervals, a spline method or other interpolation method can be used.

Next, each section of this apparatus will be described in more detail. It is desirable that the measuring unit 10 continuously acquire data without dropping as much as possible, and can accurately know the time (elapsed time) at the time of data acquisition. First,
A specific example of the measurement signal generation circuit 11, the switching circuit 16, and the first and second frequency dividers 21 and 22 will be described with reference to FIG.

The measurement signal generation circuit 11 includes four D-type flip-flops F1, F2, which are a first, a second, a third, and a fourth.
F3 and F4, two OR gates G2 and G3, one exclusive OR gate G4, and one AND gate G5
And one delay circuit DL, the input 1 from the first frequency divider 21 is supplied to the trigger terminal T of the first D-type flip-flop F1, and the second frequency divider 21. Two
The input 2 from 2 is supplied to the trigger terminal T of the third D-type flip-flop F3.

On the other hand, the external trigger input signal for starting the measurement is supplied to the trigger terminal T of the fourth D-type flip-flop F4, and the high level signal H given to the data terminal D thereof is output terminal Q thereof. Is supplied to the data terminal D of the first D-type flip-flop F1. The output terminal Q of the D-type flip-flop F1 is connected to the first continuous cycle measuring circuit 17 and the trigger terminal T of the second D-type flip-flop F2, respectively, and the high level applied to the data terminal D thereof. The signal H is output from its output terminal Q.

The high level signal H is also applied to the data terminal D of the second D-type flip-flop F2, and its output terminal Q is one of the data terminal D of the third D-type flip-flop F3 and the AND gate G5. Of the exclusive OR gate G4 via the delay circuit DL. This exclusive OR gate G4
To the other input of the third D-type flip-flop F3 is connected to the output terminal Q (logical inversion of Q).
The output of the R gate G4 is connected to the other input of the AND gate G5. The output of the AND gate G5 is connected to the second continuous cycle measuring circuit 18. The delay circuit DL, the exclusive OR gate G4, and the AND gate G5 function as a pulse shaping function unit that shapes the pulse waveform.

The first and second frequency dividers 21 and 22 have the same structure, and the first frequency divider 21 includes one programmable divider PD1 and one latch LT1 and a second frequency divider. The frequency divider 22 is also composed of one programmable divider PD2 and one latch LT2,
As described above, the frequency division ratio can be switched according to the measurement conditions. These programmable dividers PD1 and PD2 have latch LTs at preset data terminals.
The data previously set by the user is input from each of 1 and LT2.

The switching circuit 16 has two AND gates A
G1, AG2, one inverter INV, one O
Although it is a logical switch composed of the R gate OG1, a mechanical switch such as a relay may be used.
The switching circuit 16 is switched by the control unit 40 to a switch (S
W) When the control signal (high level) is input, the reference phase test signal from the frequency conversion circuit 13 is supplied to the second frequency divider 22.
And when the switch (SW) control signal is not input from the control unit 40 (or when a low level switch control signal is input), the measured input 2 is supplied to the second frequency divider 22. .

According to the above configuration, the measurement signal generation circuit 11
The external trigger signal is input to the trigger terminal T of the fourth D-type flip-flop F4 to start the measurement operation, and the switch control signal input from the control unit 40 causes the switching circuit 16 to input the measured input 2 Is supplied or the test signal of the reference phase is supplied, the input 1 and the input 2 are supplied to the measurement signal generation circuit 11 to continuously generate the measured edges, and the first and second continuous signals are generated. Period measurement circuit 1
Since it is obvious that the signal is supplied to Nos. 7 and 18, the waveforms of the respective parts designated by (1) to (13) in FIG. 11 are shown in FIG. , Pulse widths Wx1, Wx2, Wx3, ...
..The positive pulse signal of the first D-type flip-flop F
This is a case where a positive pulse signal having a form obtained by inverting the waveform of the input 1 is inputted to the trigger terminal T of the first D-type flip-flop F3 as the input 2.

To add some explanation, the reset pulse (see waveform (1)) directly resets the second and fourth D-type flip-flops F2 and F4, and the first D-type flip-flop F1 is OR gated. The third D-type flip-flop F3 is reset via the OR gate G3 via G2, and at the same time, the reset pulse also resets the first and second continuous cycle measuring circuits 17 and 18. Also, the rising edge of input 1 causes the first D
The output Q of the D-type flip-flop F1 is inverted, which causes the first D-type flip-flop F1 to operate. However, after the output Q of the first D-type flip-flop F1 is inverted, a first continuous time elapses. The cycle measuring circuit 17 generates a write pulse (see waveform (5)) and the buffer memory 19
To measurement data (cycles between rising edges Pr1, Pr2,
...) is written. This is because the first continuous cycle measuring circuit 17 allows for the time required for internal processing. The time tM1 in FIG. 12 is the time (including the generation of the write pulse (5)) in consideration of the time required for this internal processing.

The same applies to the case of the second continuous cycle measuring circuit 18, in which the third trailing edge of the pulse width Wx1 of the input 1 and the rising edge of the input 2 (see waveform (3)) at the same time are used for the third trailing edge. Output of D-type flip-flop F3
Is inverted, and after a certain time elapses, the second continuous cycle measuring circuit 17 generates a write pulse (see waveform (12)) and the measured data (cycles Pf1, Pf2, ... Between falling edges) is stored in the buffer memory 20.・ ・) Is designed to be written. The time tM2 in FIG. 12 is the time (including the generation of the write pulse (12)) in consideration of the time required for this internal processing.

These writing pulses (5) and (12)
Of the first and third D-type flip-flops F1
, And F3 are reset through OR gates G2 and G3, but the output D of the second D-type flip-flop F2 remains high because no reset pulse is supplied. Here, the output Q of the second D-type flip-flop F2 is delayed by the delay circuit DL by the time t and supplied to one input of the exclusive OR gate G4. A pulse (see waveform (11)) is generated. By the generation of this pulse, the first and second
The measurement start times of the continuous cycle measuring circuits 17 and 18 can be matched. Further, of the periods Pf1, Pf2, ... Between falling edges output from the AND gate G5, the first period Pf1 is equal to the pulse width Wx1 of the input 1. FIG. 13 shows the data contents written in the buffer memories 19 and 20 in this way (when the duty ratio is close to 100%). In FIG. 13, (a) shows the relationship between the measured value and the pulse signal of input 1, and (b) shows the buffer memories 19, 20.
Indicates the contents of. The calculation formula of the pulse width in this case is as follows.

Pulse width Wxn = Wx (n-1) + Pfn + Pr (n-1) Next, one specific example of the first and second continuous cycle measuring circuits 17 and 18 will be described with reference to FIG. Examples of the continuous cycle measuring circuits 17 and 18 include Japanese Patent Application No. 62-2.
The technology shown in No. 5326 can be used as a basic configuration. As described above, the circuit configurations of the first and second continuous cycle measuring circuits 17 and 18 may be substantially the same, and as described with reference to FIG. 3, the fractional times t1 and t2,
Data Np1K T0, Np2K T0 obtained by multiplying the number Np1k, Np2k of counting clocks included from the end of time t1 to the end of time t2 by the period T0 of this counting clock are calculated, and among these calculated data, Np1K T0 , Np2K
If the circuit configuration is such that T0 is output as it is, the difference (t1 −t2) is converted to a voltage for the fractional times t1 and t2, and ΔVp1K and ΔVp2K that are digital values obtained by the A / D converter are output. Well, Fig. 14 is Japanese Patent Application Sho 62
A specific example of the first continuous cycle measuring circuit 17 in which the technique shown in No. 25326 is used as a basic configuration and which is partially modified so that the above operation can be performed will be described. Of course, the second continuous cycle measuring circuit 18 may have the same circuit configuration and is not limited to the circuit configuration of FIG.

The continuous cycle measuring circuit 17 shown in FIG. 14 includes four first to fourth JK flip-flops F11 to F14.
, One D-type flip-flop F15, first and second fractional time-voltage converters TV1 and TV2, and
The fifth five AND gates AG11 to AG15 and the first
~ The fourth four OR gates OG11 to OG14, and the first
And a subtraction amplifier SA1 that performs a subtraction between the output values of the second fractional time-voltage converters TV1 and TV2, and the output values of the first and second fractional time-voltage converters TV1 and TV2 are switched to the subtraction amplifier SA1. Switch SW11 that can be input as input, a 1 / M frequency divider FD1 that divides the clock into 1 / M, two first and second one-shot multivibrators MM1 and MM2, and Np1
A preset type counter PCT11 that counts K T0, a sample hold circuit SAH1 that samples and holds the fractional quantity (t1 −t2) voltage, and an analog-digital converter (A / A / D) that converts the sampled fractional quantity voltage into a digital signal. D converter) AD1. The connection state of these constituent elements is as shown in the figure, and therefore its explanation is omitted. H supplied to the J and K terminals of each of the first to fourth JK flip-flops F11 to F14 and the data terminal D of the D-type flip-flop F15 represents a high level signal.

In the above structure, the measured edge signal of the input 1 is supplied from the measurement signal generation circuit 11 to the input terminal IN1. (In the case of the second continuous cycle measuring circuit 18, the measured signal of the input 2 is supplied from the measurement signal generating circuit 11 to the input terminal IN1.) The following description of the operation is the first continuous cycle measurement. In the case of the circuit 17, the second
It goes without saying that the same operation is performed in the case of the continuous cycle measuring circuit 18 of.

The measured edge signal of the input 1 supplied to the input terminal IN1 is input to the trigger (clock) input terminal T of the first JK flip-flop F11, and the level thereof is inverted by the first edge signal of the JK flip-flop. The output Q of F11 is supplied to the first fractional time-voltage converter TV1. The first fractional time-voltage converter TV1 calculates the time t1 (see FIG. 3) from this edge (for example, E11 in FIG. 3) to the second counting clock and determines it as the voltage signal Δ.
Convert to V1. Further, the output Q of the JK flip-flop F11 (the logically inverted output of Q) is connected to the second fractional time-voltage converter TV2, and the measured edge signal (second edge signal) to be input next is used. When the level-inverted output Q is supplied to the second fractional time-voltage converter TV2, the second fractional time-voltage converter TV2 outputs the second count from this edge (for example, E12 in FIG. 3). The time t2 before the clock (see FIG. 3) is calculated and converted to the voltage signal .DELTA.V2. Similarly, the first fractional time-voltage converter TV1 generates the voltage signal .DELTA.V2n-1 corresponding to the time from the third, fifth, ... Odd-numbered edge to the second counting clock. , Second fractional time-to-voltage converter TV
2 generates a voltage signal ΔV2n corresponding to the time from the fourth, sixth, ... Even-numbered edge to the second counting clock.

These voltage signals ΔV2n-1 and ΔV2n are supplied to the subtraction amplifier SA1 via the changeover switch SW11. This change-over switch SW11 is composed of two change-over switches that operate in conjunction with each other, the movable contact 1c of the first change-over switch is connected to the + side input of the subtraction amplifier SA1, and one fixed contact 1a thereof has a first fractional time-voltage. On the output side of the converter TV1, the other fixed contact 1b is connected to the output side of the second fractional time-voltage converter TV2, respectively, and the movable contact 2 of the second changeover switch.
c is connected to the-side input of the subtraction amplifier SA1, one fixed contact 2a of which is connected to the second fractional time-voltage converter TV2.
On the output side, the other fixed contact 2b is connected to the output side of the first fractional time-voltage converter TV1.

Since the arithmetic operation in the subtraction amplifier SA1 is to obtain the voltage of the fractional quantity (t1 -t2) as described above, the voltage on the termination side is subtracted from the voltage on the termination side.
Therefore, at the time of initial setting, the movable contact of the changeover switch SW11 is at the position shown in the figure, and first (ΔV1-ΔV2)
Is subtracted. Note that the calculation in the subtraction amplifier SA1 is always a calculation for subtracting the voltage on the terminal side from the voltage on the terminal side, but in the next subtraction, the voltage (ΔV2) on the terminal side immediately before can be used as the voltage on the terminal side. The switch SW11 is switched to subtract the second output (ΔV3) of the first fractional time-voltage converter TV1 from the output (ΔV2) of the second fractional time-voltage converter TV2 (ΔV2-ΔV3). . For the next subtraction, the switch SW11 is switched again to change the first fraction time-from the second output (ΔV3) of the voltage converter TV1 to the second fraction time-
The second output (ΔV4) of the voltage converter TV2 is subtracted (ΔV3−ΔV4), and thereafter the switch SW11 is alternately switched to perform the subtraction.

The fractional quantity voltage (ΔV calculated in this way
n −ΔVn + 1) is sampled by the sample hold circuit SAH1 and further converted into a digital value by the A / D converter AD1 to obtain a digital value ΔVp1K of the fractional quantity voltage as a first value.
Output to the buffer memory 19 of. Data Np1K T0 obtained by multiplying the number Np1k of counting clocks included from the end of time tn to the end of time t (n + 1) by the period T0 of this counting clock is stored in the first buffer memory by the preset counter PCT11. It is output to 19.

On the other hand, the write pulse generated from the second one-shot multivibrator MM2 is supplied to the first buffer memory 19 to start writing the input measurement data. Therefore, the period of the signal under measurement can be continuously measured from the period data in the arithmetic analysis unit 30 as described above. Next, FIG. 15 shows a specific example of the first and second buffer memories 19 and 20. Since the data from the measuring unit 10 is continuously stored without a leak when a write pulse is input, each buffer memory 19 and 20 is a double buffer, and two sets of address counters (ACT1 and ACT2) of the same scale are provided. ) And RAM (RAM1, RAM2) are used, and they alternately perform write operations. Further, while the write operation is being performed on the one address counter and the RAM, the other address counter and the RAM are read. If necessary, speed up reading rather than writing, and after reading,
Next, it may be possible to perform a necessary calculation before the writing to the buffer memory. Although a specific example of the first buffer memory 19 is shown in FIG. 15, the second buffer memory 20 may have a similar circuit configuration, and the write data from the first and second continuous cycle measuring circuits 17 and 18 ( Period data) Np1K T0, Np2K T
0 and ΔVp1K, ΔVp2K are the continuous cycle measuring circuit 1
When the write pulses are supplied from 7 and 18, they are separately stored in the RAMs of the buffer memories 19 and 20.
In FIG. 15, AG21 to AG24 are AND gates, OG21 to OG24 are OR gates, and F21 and F21.
Reference numerals 22 denote D-type flip-flops, respectively.

As described above, these buffer memories 1
9 and 20 are configured in a cyclic manner in which the memory address returns to the initial value when it reaches the final value of the address counter, and the operation analysis unit reads the measured value from the buffer memories 19 and 10 in parallel with the acquisition of the measured value, and the user The maximum value and the minimum value of the time interval value within the observation time set by are calculated sequentially.

Next, the frequency conversion circuit 13 and the multiplication circuit 1
16 shows a specific example of No. 4 of FIG. As a specific example, these are circuit diagrams under the following general conditions. Reference oscillator output frequency: 10 MHz External reference input frequency: 10 MHz Count clock frequency: 100 MHz Reference phase output frequency: 2048 KHz The multiplication circuit 14 uses the output frequency of the reference oscillator 12 as a PLL.
(Phase-locked loop) is used to convert the count clock frequency. The counting clock frequency is set to about 100 MHz so that it can be configured by a commercially available general-purpose digital IC (TTL, C-MOS, ECL, etc.), and the voltage controlled oscillator (VCO) that constitutes the PLL uses a crystal oscillator with low phase noise ( VCXO) is used.

The PLL constituting the multiplication circuit 14 includes, as usual, a phase comparator 101 to which the output frequency signal of the reference oscillator 12 is input, and a loop filter 102 for filtering the output signal from the phase comparator 101. , The VCXO 103 whose oscillation frequency is controlled by the voltage of the signal filtered by the loop filter 102, and this VCX
A frequency divider 104 that divides the frequency of the oscillation output from O103 into 1/10. The frequency division output of the frequency divider 104 is input to the phase comparator 101, and the phase of the output signal from the reference oscillator 12 is input. Compared to. 1/10 with frequency divider 104
The output frequency of the reference oscillator 12 is divided by 10 MHz.
This is because the oscillation frequency of the VCXO 103 is set to 100 MHz with z.

In this example, the output signal from the reference oscillator 12 is input to the multiplication circuit 14 and the frequency conversion circuit 13 via the changeover switch 105. The switch 105 switches between an output signal from the reference oscillator 12 and an external reference frequency signal (for example, one synchronized with UTC), and when an external reference signal having the same frequency as the oscillation frequency of the reference oscillator 12 is obtained, Instead, this external reference frequency signal can be used. Therefore, in this case, the reference oscillator 12 may not be provided.

Although the circuit scale becomes slightly larger,
The multiplier circuit 14 may be configured by an overdrive circuit and a tuning filter without using L. However,
Select a tuning filter that is resistant to temperature changes and has a high Q. The frequency conversion circuit 13 converts the output frequency of the reference oscillator into a reference phase signal necessary for wander measurement by the PLL. Since the phase is the reference phase, the voltage controlled oscillator (VCO) of the PLL that constitutes the frequency conversion circuit 13 also uses a VCXO using a crystal oscillator with low phase noise. Frequency conversion circuit 13
The PLL constituting the frequency divider 111 divides the output frequency from the reference oscillator 12 or the external reference frequency signal (10 MHz).
At 1/2500 and input a 4KHz signal to the phase comparator 112, and from the VCXO 114 to 2048K.
The frequency signal of Hz is oscillated, and this is divided by the frequency divider 115 to 1
The frequency of the 4 kHz signal divided into / 512
Since the configuration and the operation are the same as those of the PLL of the multiplication circuit 14 except for the input to the above, the description thereof will be omitted. The output signal of the phase comparator 112 is the loop filter 11
It is filtered by 3 and input to the VCXO 114.

The reference phase frequency signal (test signal) from the frequency conversion circuit 13 is supplied to the switching circuit 16 and the jitter adding circuit 15 as described above. Further, it is taken out from the terminal (not shown) as a test signal output without jitter. In this example, a 2048 KHz test signal is shown, but the test signals are mainly 1544 KHz and 204
Since 8 KHz is used, the set value may be changed to set it to 1544 KHz. It is not necessary for the user to generate both frequency signals, as the user need only have one of the test frequency signals required by the country. Therefore, in practice, if the frequency conversion circuit 13 is mounted on the option board, the user can easily change the test frequency by replacing the board.

Next, a concrete example of the jitter adding circuit 15 is shown in FIG. The jitter adding circuit 15 is used for, for example, jitter generated in various devices or transmission lines, or ITU / TS.
This is to artificially generate the jitter within the range allowed by 1. The jitter of an arbitrary waveform or frequency that can be set by the user is added to the reference phase test signal from the frequency conversion circuit 13 and output to the outside. The jitter adding circuit 15 doubles the retiming flip-flop RF1 for retiming the test signal PA (digital signal) of the reference phase to which jitter is added and the retiming flip-flop RF1 for producing the clock signal PB from the test signal of the reference phase. Multiplier MP10 and inverter INV10 for inverting the output signal of this multiplier MP10
A delay circuit DL11 for delaying the inverted output of the inverter INV10, a 2 ⁿ multiplier MP11 for multiplying the delayed clock signal by 2 ⁿ , an n-bit binary counter BCT1, and an m-bit address counter ADT1
RAM, microcomputer MC1, AND gates AG31 and AG32, exclusive OR gate EG1,
AND gate A composed of EG2, ... EGn
G32 and exclusive OR gates EG1, EG2, ... EG
A match detection circuit is formed by n.

The jitter adding circuit 15 is the frequency converting circuit 1.
The test signal of the reference phase from 3 is input to the data terminal D of the retiming flip-flop RF1 as a digital signal PA to which jitter is added, while the test signal of the reference phase is given to the multiplier MP10 and doubled. Further, it is inverted by the inverter INV10 to generate the external clock signal PB, and from this clock signal PB, under control of the microcomputer MC1, a 2 ⁿ multiplier MP11, an n-bit binary counter BCT1, an m-bit address counter ADT1. , RAM, AND gates AG31 and AG3
2. The exclusive OR gates EG1, EG2, ... EGn are used to generate a trigger signal for retiming the digital signal PA, and the trigger signal is given from the ANDAG 31 to the trigger terminal T of the retiming flip-flop RF1. The digital signal PJ (test signal) to which the jitter is added is output from the output terminal Q.

The jitter adding test signal PJ from the jitter adding circuit 15 is input to a device under test such as a jitter removing circuit or a device under test such as a network clock supply device in an exchange or a transmission device, and outputs them. By inputting the signal to this analyzer as the signal under measurement,
It is possible to analyze the jitter suppression effect and the jitter tolerance of the device under test and check the output of unnecessary jitter.

A detailed explanation of the operation of the jitter adding circuit 15 is described in Japanese Patent Application No. 3-188723 "Jitter adding device" filed by the applicant of the present invention. Therefore, the constants m and n in FIG. FIG. 18 shows waveforms (1) to (10) of the respective parts in the case where each is set to 3, and the description thereof will be omitted. Further, it is needless to say that the above embodiment is merely an example of the present invention, and therefore the configuration, circuit connection, elements to be used, etc. can be variously changed and modified as necessary.

[0073]

As described above, according to the present invention, the rising edge or the falling edge of the pulse-shaped signal under measurement is input to the two-system continuous cycle measuring circuit to continuously measure the cycle. Further, since the analyzing means has a means for analyzing the change amount of each calculated measured value with respect to the elapsed time by performing a fast Fourier transform, the jitter frequency of two measured signals can be obtained from the result of the fast Fourier transform. There is an effect that the spectrum can be obtained simultaneously and with high accuracy.

Further, the measurement amount calculating means calculates the time interval value between both signals from each cycle measurement value, and the analyzing means analyzes the change amount of the time interval value with respect to the elapsed time by performing a fast Fourier transform. This has the effect that the relative jitter frequency spectrum can be obtained with high accuracy. Further, since the frequency of the signal to be measured is divided by the dividing means to an appropriate frequency and the divided period is measured by the continuous period measuring circuit, the whole measuring time can be lengthened. There is an effect that a relatively low jitter frequency spectrum of the signal under measurement can be obtained with high accuracy by analyzing the amount of change in the measured value with respect to the elapsed time by performing a fast Fourier transform.

Further, the frequency dividing means divides the signal under measurement and the test signal having a predetermined frequency of the reference phase up to an appropriate frequency at which the frequencies match, and the period of each divided signal is continuously measured. Each of them is measured by the circuit, and the measured amount calculation means calculates the time interval value between both signals from the measured value of each frequency division period, and the analysis means calculates the maximum value and the minimum value from the time interval value between these signals. And the MTIE and the long-term frequency deviation at a plurality of observation times at the same time, the wander that is the long-term phase fluctuation can be efficiently analyzed.

Further, by adding a jitter to the test signal of a predetermined frequency of the reference phase and providing the jitter adding means for outputting the jitter adding test signal to the outside, an arbitrary value which can be set by the user from the jitter adding means is provided. Since the jitter-added test signal of the waveform or frequency can be output to the external device under test, by inputting the output signal from the device under test as the signal under measurement, the jitter suppression effect or jitter of the device under test can be reduced. There is an effect that the yield strength can be analyzed with high accuracy.

Further, a terminal for outputting a test signal having a predetermined frequency of the reference phase to the outside is provided, and a pure test signal without jitter is output from this terminal to an external device under test to output from the device under test. By inputting the output signal of 1 as the signal under measurement, it is possible to analyze the jitter generated only in the device under test with high accuracy. Therefore, according to the present invention, continuous jitter frequency component analysis from low frequency to high frequency can be performed with high accuracy, low frequency jitter analysis can be sufficiently performed, and ITU / TS can be used for wander. It is possible to measure with high accuracy and efficiency over the observation period from 50 msec to 10 ⁷ sec, which is regarded as important for MTIE wander recommended by the above.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of a jitter / wander analysis device according to the present invention.

FIG. 2 is a configuration diagram showing an example of a case where the jitter / wander analysis device of FIG. 1 measures and analyzes the jitter / wander of an external device under test.

FIG. 3 is a waveform diagram for explaining a continuous cycle measuring operation in the continuous cycle measuring circuit of the jitter / wander analysis device of FIG.

FIG. 4 is a time chart for explaining a method of adjusting the measurement start times of two continuous cycle measuring circuits in the jitter / wander analysis device of FIG.

5 is a time chart for explaining the operation when measuring the period of an input pulse in the jitter / wander analysis device of FIG. 1. FIG.

6 is a time chart for explaining an operation when measuring a time interval between two input pulses in the jitter / wander analysis device of FIG. 1. FIG.

FIG. 7 is a diagram showing an example of analyzing data calculated by frequency distribution display.

FIG. 8 is a diagram showing an example of analyzing data calculated by a time change display.

FIG. 9 is a diagram for explaining an operation of calculating MTIE.

10A is a diagram showing a pulse width over time, FIG. 10B is a diagram for explaining linear interpolation, and FIG. 10C is a diagram showing an example of a frequency spectrum of pulse width jitter.

11 is a circuit diagram showing a specific example of a measurement signal generation circuit, a frequency divider, and a switching circuit used in the jitter / wander analysis device of FIG.

12 is a time chart showing signal waveforms at various parts of the measurement signal generation circuit of FIG.

FIG. 13 is a diagram showing a relationship between measured values in a continuous cycle measuring circuit and contents stored in a buffer memory when the duty ratio of an input pulse is close to 100%.

14 is a circuit diagram showing a specific example of a continuous cycle measuring circuit used in the jitter / wander analysis device of FIG.

15 is a circuit diagram showing a specific example of a buffer memory used in the jitter / wander analysis device of FIG.

16 is a circuit diagram showing a specific example of a frequency conversion circuit and a multiplication circuit used in the jitter / wander analysis device of FIG.

17 is a circuit diagram showing a specific example of a jitter adding circuit used in the jitter / wander analysis device of FIG. 1. FIG.

FIG. 18 is a time chart showing a signal waveform in each part of the jitter adding circuit of FIG.

[Explanation of symbols]

 Reference Signs List 10 measurement unit 11 measurement signal generation circuit 12 reference oscillator 13 frequency conversion circuit 14 multiplication circuit 15 jitter addition circuit 16 switching circuit 17, 18 continuous cycle measurement circuit 19, 20 buffer memory 21, 22 frequency divider 30 arithmetic analysis unit 31, 32 Fractional quantity addition unit 33 Measured amount calculation unit 34 Analysis calculation unit 40 Control unit 50 Display unit 60 Operation unit 70 Bus

Claims (8)

[Claims] 1. A first continuous cycle measuring circuit, which is provided with one edge of a pulsed signal under measurement and continuously measures the period of the edge, and one edge or device of the pulsed signal under measurement. A second one of which is provided with one edge of a test signal of a predetermined frequency having an internally generated reference phase and which continuously measures the period of the edge;
Continuous cycle measuring circuit, first and second memories for storing measurement cycle data output from the first and second continuous cycle measuring circuits, and stored in the first and second memories. Measuring amount calculating means for calculating various amounts of time / frequency including at least the period and time interval of the measured signal based on the measured period data, and analysis of various calculated time / frequency amounts of the measured signal. And first and second frequency dividing means for selectively frequency-dividing the signal under measurement input to the first and second continuous cycle measuring circuits, respectively. Jitter / Wander analyzer. 2. An analysis means for analyzing various amounts of time / frequency of the signal under measurement is a result obtained by performing a fast Fourier transform on a variation amount of the measurement value calculated by the measurement amount calculation means with respect to an elapsed time and analyzing the result. 2. The jitter / wander analysis apparatus according to claim 1, further comprising means for obtaining a jitter frequency spectrum of the signal under measurement from. 3. The first and second continuous cycle measuring circuits simultaneously and continuously measure the cycles of two signals under measurement, and the analyzing means calculates each of the cycles calculated by the measurement amount calculating means. 2. The jitter / wander analysis device according to claim 1, wherein the jitter frequency spectrum of each signal under measurement is simultaneously obtained from the result of analysis of the change amount of the measured value with respect to the elapsed time by fast Fourier transform. 4. The first and second continuous cycle measuring circuits simultaneously and continuously measure the cycles of two signals under measurement, and the measured amount calculating means calculates the interval between the two signals from each cycle measurement value. Calculating a time interval value, and obtaining a relative jitter frequency spectrum from the result of analysis by the fast Fourier transform of the amount of change of the time interval value calculated by the measurement amount operation unit with respect to the elapsed time by the analysis unit. The jitter / wander analysis device according to claim 1. 5. The frequency division of the signal to be measured by the first and second frequency dividing means to an appropriate frequency, and the frequency division period is measured by the first and second continuous period measuring circuits. The measurement time is increased, and the analysis unit analyzes the amount of change in the measured value calculated by the measurement amount calculation unit with respect to the elapsed time by performing a fast Fourier transform to analyze a relatively low jitter frequency spectrum of the signal under measurement. The jitter / wander analysis device according to claim 1, which is obtained. 6. The first and second frequency dividing means divides the signal under measurement and the test signal having a predetermined frequency of the reference phase, respectively, to an appropriate frequency at which the frequencies match, and divides the respective frequencies. The period of the frequency signal is measured by each of the first and second continuous period measuring circuits, the measurement amount calculating means calculates the time interval value between the two signals from each frequency division period measurement value, and the analyzing means The maximum value and the minimum value are calculated from the time interval value between the two signals calculated by the measurement amount calculation means, and the MTIE and the long-term frequency deviation at a plurality of observation times are simultaneously calculated from them.
2. The jitter / wander analysis device according to claim 1, wherein a wander that is a long-term phase fluctuation can be efficiently analyzed. 7. A jitter adding means for adding jitter to a test signal of a predetermined frequency of the reference phase and outputting the jitter added test signal to the outside, and any jitter that can be set by a user from the jitter adding means. By outputting the jitter-added test signal of waveform or frequency to the external device under test and inputting the output signal from the device under test as the signal under measurement, the jitter suppression effect and the jitter tolerance of the device under test can be analyzed. The jitter / wander analysis device according to claim 1, wherein 8. A terminal for outputting a test signal having a predetermined frequency of the reference phase to the outside, and a pure test signal having no jitter is output from the terminal to an external device under test to be tested. The jitter / wander analysis device according to claim 1, wherein the jitter generated in only the device under test can be analyzed by inputting an output signal from the device as a signal under measurement.