JPS5917914B2 - Jitter measurement device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a jitter measuring device that measures temporal fluctuations in the edges of digital signals, so-called jitter, occurring in a transmission path.

When a digital signal is transmitted, its rising and falling edges, that is, the edges of the signal, fluctuate back and forth in time due to jitter in the transmission path.

In order to measure this fluctuation, that is, the amount of jitter, the transmitted signal and a reference clock signal are required. In other words, the amount of jitter is measured by comparing the transmitted signal with a reference clock signal that is not subjected to jitter, and determining the amount of jitter from the deviation of the edge of each transmitted signal with respect to the reference clock signal. When such a reference clock signal cannot be obtained, a special signal is transmitted as a digital signal that repeats a high level "1" and a low level "0" for each single point length, that is, for each pit, and
The amount of jitter was measured by measuring the interval between "l" and "o". When transmitting normal zeta, the length of the high level and low level changes depending on the data, so it is not possible to measure changes in the position of the edge. For this reason, it was necessary to send the above-mentioned special data for measurement. A voltage-controlled oscillator that generates a signal that repeats high and low levels with its clock or D single point length according to received normal data, is connected to a phase-locked loop;
It is also conceivable to create a clock synchronized with the clock of the incoming digital signal by applying phase synchronization using a so-called PLL, and to measure the jitter of the incoming digital signal using this as a reference. However, in this case, if the digital signal has a relatively long high level or low level state, the time constant of the phase-locked loop must be lengthened, so that the high level and low level can be repeated quickly. If this happens, the PLL will not be able to follow it, making it impractical.The purpose of this invention is to measure jitter in a transmitted digital signal even if there is no reference clock for that signal, and without creating that reference clock. The present invention provides a jitter measurement device that can perform Hereinafter, a jitter measuring device according to the present invention will be explained with reference to the drawings.

The digital signal to be measured is sent from the terminal 11 to the gate 12 in Figure 1.
and the set terminal of flip-flop 13. When a starting pulse as shown in FIG. 2A is applied from the terminal 14 to the set terminal of the flip-flop 15, the Q output of the flip-flop 15 becomes high level as shown in FIG.
becomes operational. Therefore, due to the rising edge of the digital signal under test shown in FIG. 2C from the terminal 11 immediately after the activation pulse is generated, the output of the flip-flop 13 becomes high level as shown in FIG. 2D. The rise and fall b of the digital signal to be measured are △Tl, △T2, △T3, due to jitter.
...is fluctuating. The output of flip-flop 13 opens gates 12, 16 and 17.

The digital signal to be measured from the terminal 11 passes through the opened gate 12 and is applied to the gate 16.
The output of the inverter 18 is inverted and applied to the gate 17. That is, the signal passing through the gate 12 becomes as shown in FIG. 2E, and the output of the inverter 18 becomes as shown in FIG. 2F. On the other hand, the clock oscillator 19 supplies the clock shown in FIG. 2G to the gates 16 and 17.

Therefore, from the gate 16, the clock pulse passes through the high level section of the digital signal under test as shown in FIG.
It is supplied to the counter 21. Similarly, during the low level period of the digital signal under test, a clock pulse passes through the gate 17 and is supplied to the counter 22, as shown in FIG.
The output signal of the gate 12 shown in FIG.
3, and each time the signal falls, the counter 21
The count value is latched in the latch circuit 23.

The output of the inverter 18 is also given to the latch circuit 24,
Each time the signal falls, the count value of the counter 22 is latched in the latch circuit 24. Furthermore, the output of gate 12 is also provided to toggle flip-flop 25, which allows 1/2
The signal shown in FIG. 2H is obtained. At the time when the output of the flip-flop 25 changes, that is, at the rising and falling edges, the adder circuit 26 is driven and the count values held in the latch circuits 23 and 24 are added. The output of the flip-flop 25 is also supplied to the address counter 27, and the address counter 27 increments its count every time the state of its input is reversed.The count value of the address counter 27 is given as an address to the memory 28, and the address counter 27 is The adder circuit 26 is added to the memory 28 specified by the contents of
The added value of is stored. The output of the gate 12 is also applied to a counter 29 for counting measurement time, and when the counter 29 counts a certain number, it generates a termination pulse as shown in FIG.

This termination pulse resets the flip-flops 13 and 15, and the output of the flip-flop 13 becomes as shown in FIG.
As shown in FIG. 2, the level becomes low, and therefore the gate 12 is closed. Further, the output of the flip-flop 15 also becomes a low level as shown in FIG. 2B. Furthermore, the termination pulse of FIG. 2 is also supplied to the data processing device 31. The data processing device 31 reads the data stored in the memory 28 and starts its processing.The memory 28 stores the added value of the adding circuit 26 every time the state of the signal shown in FIG. 2H changes. Therefore, in the example from the generation of the starting pulse in Figure 2A, the length tl from the first rising edge of the input data to the next rising edge is stored at the first location, and the length tl from the first rising edge to the second rising edge of the input data is stored at the second location. The length T2 to the rising edge is stored in the third address, and the length T3 from the first rising edge to the third rising edge is stored in the third address. Thereafter, in the same way, the count value of the clock from the first rising edge to each rising edge, that is, the value corresponding to the length, is stored in the memory 28, and the length T from the first rising edge to the last rising edge is stored in the memory 28.
nil. It is stored at address n. In this way, the length Tn from the first rising edge to the last rising edge of the digital signal under test from the start pulse to the end pulse is measured.The nominal transmission rate of the digital signal under test, that is, per unit time. The amount of information is known in advance, and therefore, from the above Tn and the nominal transmission speed, the number Nn including periods corresponding to the single point length of the digital signal under test is calculated within the period Tn. The number Nn of single point lengths actually included in the measurement time Tn must be an integer. Therefore, for example, if the nominal transmission rate is 1 Mbit/s and the measurement time Tn is 119.9
In the case of μs, Nn=120. This number of single point lengths N
By dividing the measurement time Tn by n, the length τs corresponding to the single point length of the digital signal is determined. Jitter occurs randomly and averages out to O. Therefore, if the measurement time Tn is made long enough, this Tn will hardly be affected by jitter, and τS can be determined correctly.
The length τs corresponding to this single point length and the length T from the first rise to the next rise sequentially, t2, t3,...
Calculate the amount of jitter from... For example, the length T,
The amount of information in t2, t3, . . . , that is, the number of lengths (integers) corresponding to the single point length, is calculated using the nominal transmission speed and Nl, N2, N3, . . . seek.

Next, multiply N, and τs to obtain a value N,τ without this jitter.
The jitter amount ΔT2 is determined from the difference between s and T. Similarly, the difference between the length T2 until the next rising edge and N2τs is the jitter amount ΔT4 at the next rising edge. Thereafter, the jitter amount N3τS, . . . Nnτs−Tn is determined in the same manner. As mentioned earlier, jitters occur randomly, and on average,
It is thought that.

If this is not the case, the frequency or speed of the digital signal under test will become progressively faster or slower. If the speed is constant, the average jitter will be O over a long period of time, and τs will be calculated in a state where the average jitter is 0, so that accurate τs can be found. Regarding the incoming digital signal, its Tl, t2,
By sequentially storing t3, . Moreover, there is no need to send special data for measurement to the transmission path to be measured.

In the above description, the amount of jitter at successive rising points is measured using the first rising point of the digital signal under test as a reference within a certain period of time, but it is also possible to measure the jitter at the rising points. In that case, by inverting the digital signal under test shown in FIG. 2C and supplying it to the terminal 11, it is possible to measure the jitter at the falling point of the digital signal shown in FIG. 2C. To find the length τs corresponding to the single point length, you can divide Tn by Nn as shown above, but to make it even more accurate, each count value T,, t2, t3...
The total value of... ΣTi, Nl, N2, N3...
Addition of 1 = 1 value, . The value divided by YNi is τs
Then, 1=1 becomes a more accurate value.

As is clear from the explanation of FIG. 2, τs used in the above is twice the actual single point length.

Therefore, jitter measurement may be performed by finding one-half of τs. Also, for each rising or falling edge, measure the length of the adjacent interval sequentially, and add the first and second lengths,
The sum of the first to third values is Tl and t2, respectively.
, t3, and thereafter T, to Tn may be measured in the same manner.
However, in this case, an error of ±1 occurs in the measured value of each adjacent interval, and this error is added, so that the processing shown in FIG. 2 has higher accuracy. As the zeta processing device 31, it is possible to carry out the processing using a so-called programmer.

It is also possible to create a frequency distribution of jitter for each rise or rise obtained in this way, and it is also easy to calculate the amount of jitter as an angle and express it as a frequency distribution.
If the amount of jitter expressed as this angle is output at a fixed period and converted into a digital analog signal, the analog signal will represent the amount of fluctuation in the amount of jitter over time, and this can be analyzed using an existing frequency analyzer. It is also possible to easily measure the frequency components of the ivy. As described above, according to the jitter measuring device of the present invention, there is no need to create a reference clock frequency in particular, but it can be obtained by calculation, and therefore, it is difficult to use a clock frequency that is long-distance, such as a transmission line. Jitter can also be measured, and the measurement data is “1”.
, "2" need not be repeated.

jitter can be measured during actual zeta transmission,
Therefore, more realistic jitter measurements can be made. It is now possible to easily measure the distribution of jitter and obtain the frequency components of jitter, and it is also possible to analyze the causes of jitter, which makes it easy to allocate margins when designing a transmission system. It is possible to do it accurately.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing →1j of the jitter measuring device according to the present invention, and FIG. 2 is a waveform diagram for explaining the same. 11: Digital signal input terminal to be measured, 13, 15, 25
: Flip-flop, 14: Start signal input terminal, 21,
22: Counter, 23, 24: Latch circuit, 26: Adder circuit, 27: Address circuit, 28: Memory 18, 29: Counter for determining measurement time, 19: Clock generator, 31:
data processor.

Claims (1)

[Claims] 1 Time tn from the beginning to the end of one of the rising and falling edges of the digital signal under test in a predetermined period
and determining the number Nn of single point lengths included within the predetermined period of the digital signal under test from the pre-known nominal transmission speed of the digital signal under test and the measurement time tn. means for determining the length τs of the single point length of the digital signal to be measured from at least the measurement time tn and the number Nn of single point lengths; and edges sequentially corresponding to one of the rising and falling edges from the first edge. means for measuring each length t_1, t_2, t_3, ... up to t_1, t_2, t_
3. A jitter measuring device comprising: . . . and means for calculating the amount of jitter at each edge from the length τs of the single point length.