JP2002118449A - Variable delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a desired delay amount. SOLUTION: A variable delay circuit comprises a delay compensator having a plurality of reference delay units including a different number of a first variable delay elements having a changing delay amount, based on a control signal to generate a plurality of control signals to be given to the first variable delay elements in response to the number of the first variable delay elements, and a delay unit having a plurality of second variable delay elements each having same characteristics as that of the first variable delay elements to generate a desired delay amount under the control of a plurality of the control signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a variable delay circuit for generating a delay amount. In particular, the present invention relates to a variable delay circuit that has a plurality of variable delay elements and generates a desired delay amount.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing a conventional variable delay circuit 100. The variable delay circuit 100 includes a minute variable delay unit 12 and a variable delay unit 14. The minute variable delay unit 12 has minute variable delay elements (12a to 12n). The variable delay unit 14 has delay units (14a to 14n). The minute variable delay elements (12a to 12n) generate a delay amount smaller than the delay amounts generated by the delay units (14a to 14n). Each of the delay units (14a to 14n) has a different number of gate circuits 11, and generates a delay amount according to the number of gate circuits 11.

In accordance with a desired delay amount, delay data for specifying any combination of the minute variable delay elements (12a to 12n) and the delay units (14a to 14n) is supplied. An input signal is input and delayed by a delay element selected by the delay data to output a delayed signal.

FIG. 2A is a circuit diagram showing a driving impedance control type minute variable delay element 12. As shown in FIG. When the control signal has the logical value “0”, the driving impedance is set low. When the control signal has the logical value “1”, the driving impedance is set high. Therefore, when the control signal has the logical value "1", the input signal is output with a slight delay compared to when the control signal has the logical value "0".

FIG. 2B is a circuit diagram showing the variable load capacitance type minute variable delay element 12. As shown in FIG. When the control signal has the logical value “0”, the load capacitance is not set, and when the control signal has the logical value “1”, the load capacitance is set. Therefore, when the control signal has the logical value "1", the input signal is output with a slight delay compared to when the control signal has the logical value "0". The variable delay circuit 100 shown in FIG.
The micro variable delay element 12 shown in (b) is provided, and a delay amount of about 10 ps to 100 ps is generated for one micro variable delay element 12.

FIG. 3 shows delay data designating a combination of design delay elements for generating a desired delay amount in the conventional variable delay circuit 100 described with reference to FIG. 1, and a delay set by the delay data. 9 is a graph showing a relationship between delay amounts actually generated by combinations of elements. The line a is a straight line indicating ideal delay characteristics. On the other hand, the line b generates a delay amount larger than the ideal delay amount. Line c generates a delay amount smaller than the ideal delay amount.

The lines b and c have discontinuous portions. This is because a plurality of different types of variable delay elements exist in the variable delay circuit 100,
This is because the effects of variations in element characteristics and changes in the ambient temperature do not always coincide with each other.

[0008]

The amount of delay generated in the variable delay circuit 100 is caused by variations in the element characteristics of the delay element, fluctuations in the self-heating amount of the delay element, fluctuations in the ambient temperature, and fluctuations in the power supply voltage. For example, an error may occur between the amount of delay actually generated by the delay element and the amount of delay in design.

Accordingly, an object of the present invention is to provide a variable delay circuit which can solve the above-mentioned problems.
This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous embodiments of the present invention.

[0010]

According to a first aspect of the present invention, there is provided a variable delay circuit for generating a desired delay amount, wherein the variable delay circuit changes a delay amount based on a control signal. A plurality of reference delay units having different numbers of first variable delay elements to be included in each of the plurality of reference delay elements according to the number of first variable delay elements included in each of the plurality of reference delay units. A delay compensator for respectively generating a plurality of control signals to be supplied to the first variable delay element to be controlled, and a plurality of second variable delay elements having the same characteristics as the first variable delay element are controlled by the plurality of control signals. And a delay unit for generating a desired delay amount.

The reference delay section has a first reference delay section having M (M is a natural number) variable delay elements, and N (N is different from the number of first variable delay elements in the first reference delay section). A second reference delay unit having a (natural number) first variable delay element, wherein the delay compensation unit generates a control signal to be supplied to the first variable delay element of the first reference delay unit. And a second delay compensator for generating a control signal to be provided to the first variable delay element included in the second reference delay unit.

The reference delay section may have a different number of first variable delay elements, and may have a ring oscillator that generates an oscillation clock having a predetermined cycle in accordance with the number of first variable delay elements.

The delay compensator compares the control signal based on the comparison with a phase comparator which compares the phase of the reference clock having a predetermined period with the phase of the delay clock obtained by delaying the reference clock by the first variable delay element. And a control signal generator for generating the control signal.

The control signal generating section may generate the control signal so that the phase of the reference clock coincides with the phase of the delayed clock.

[0015] The apparatus may further include a selector for supplying any one of the plurality of control signals supplied from the delay compensating section to the second variable delay element.

The first variable delay element may include a capacitor having a predetermined capacity and a time constant control unit for changing a time constant of the capacitor, and may change the delay amount according to the time constant.

The time constant control section may have a transistor and change the time constant of the capacitor by changing the gate voltage applied to the transistor.

According to a second aspect of the present invention, there is provided a variable delay circuit for generating a desired amount of delay in a signal to be output to an output terminal, wherein a capacitor having a predetermined capacitance is provided between the capacitor and the output terminal. A variable delay element that has a time constant control unit that changes the time constant of a capacitor, and that changes a delay amount according to the time constant, and selects a variable delay element based on a desired delay amount. And a delay unit for generating a desired delay amount.

The time constant control section may have a transistor and change the time constant of the capacitor by changing the gate voltage applied to the transistor.

According to a third aspect of the present invention, there is provided a semiconductor test apparatus for testing a semiconductor device, comprising: a pattern generator for generating a test pattern to be input to the semiconductor device; and a delay amount changing based on a control signal. A plurality of reference delay units each having a different number of first variable delay elements, and a delay compensation unit that generates a plurality of control signals to be applied to the first variable delay elements according to the number of the first variable delay elements. A plurality of second variable delay elements having the same characteristics as the first variable delay element are controlled by a plurality of control signals to generate a delay clock having a delay amount according to an operation characteristic of the semiconductor device. And a shaping test pattern generator for shaping the test pattern based on the delay clock to generate a shaping test pattern; and A device contact unit for inputting the body device, characterized in that it comprises a determining comparator acceptability of the semiconductor device based on an output signal output from the semiconductor devices entered shaping the test pattern.

The reference delay section may have a different number of first variable delay elements, and may have a ring oscillator for generating an oscillation clock of a predetermined cycle according to the number of first variable delay elements.

A selector may be provided for supplying any one of the plurality of control signals supplied from the delay compensator to the second variable delay element.

The first variable delay element may include a capacitor having a predetermined capacity and a time constant control unit for changing a time constant of the capacitor, and may change the delay amount according to the time constant.

According to a fourth aspect of the present invention, there is provided a semiconductor device having a semiconductor test section for testing a semiconductor device, the semiconductor device having a different number of first variable delay elements whose delay amount changes based on a control signal. A plurality of reference delay units, a delay compensator for respectively generating a plurality of control signals to be supplied to the first variable delay element according to the number of the first variable delay elements, and a characteristic identical to that of the first variable delay element Controlling a plurality of second variable delay elements having
A semiconductor test section having a delay section for generating timing used for testing a device under test based on operating characteristics of the semiconductor device, and a device under test to be tested by the semiconductor test section. .

The reference delay section may have a different number of first variable delay elements, and may have a ring oscillator for generating an oscillation clock having a predetermined cycle according to the number of first variable delay elements.

[0026] A selector may be further provided for supplying any one of the plurality of control signals supplied from the delay compensator to the second variable delay element.

The first variable delay element may include a capacitor having a predetermined capacity and a time constant control unit for changing a time constant of the capacitor, and may change the delay amount according to the time constant.

According to a fifth aspect of the present invention, there is provided a delayed signal generating method for generating a delayed signal obtained by delaying an input signal by a desired time, wherein the first variable delay means changes a delay amount based on a control signal. A step of generating a plurality of clocks by a plurality of reference delay units having different numbers of variable delay elements, a step of comparing the phases of the plurality of clocks and the reference clock, and a step of generating a plurality of clocks based on the compared phases. Correcting a control signal corresponding to each of the following, controlling each delay amount of the first variable delay element based on the corrected control signal, receiving a control signal, and controlling based on the control signal, A plurality of second variable delay elements having the same characteristics as the first variable delay element are controlled based on the corrected control signal to delay the input signal by a desired time. Characterized in that it comprises the steps of generating a signal.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described through embodiments of the present invention. However, the following embodiments do not limit the claimed invention and have the features described in the embodiments. Not all combinations are essential to the solution of the invention.

FIG. 4 is a block diagram showing one embodiment of the semiconductor test apparatus. The semiconductor test apparatus includes a pattern generator 90, a shaped pattern generator 92, a device contact unit 94, and a comparator 95. Shaping pattern generator 92
Has a variable delay circuit 100.

The device under test 93 is connected to the device contact portion 9.
At 4, electrical contact is made with the semiconductor test equipment. The pattern generator 90 includes pattern data as a test pattern to be input to the device under test 93 and the device under test 9.
3 receives pattern data and generates expected value data to be output. The pattern generator 90 outputs the pattern data to the shaping pattern generator 92 and outputs the expected value data to the comparator 95. Further, the pattern generator 90 outputs to the variable delay circuit 100 a timing set signal designating generation of a delay clock having a predetermined delay amount according to the operation characteristics of the device under test 93.

Variable delay circuit 100 generates a delayed clock having a delay amount specified by a timing set signal. The shaping pattern generator 92 shapes the pattern data based on the delay clock supplied from the variable delay circuit 100, and outputs shaping pattern data corresponding to the operation characteristics of the device under test 93 to the device contact unit 94. The device under test 93 outputs an output value corresponding to the shaping pattern data to the comparator 95 via the device contact unit 94.
The device under test 93 may be packaged,
Further, it may be provided on a wafer. The comparator 95 is
The output value and the expected value data supplied from the pattern generator 90 are compared to determine the quality of the device under test 93.

FIG. 5 shows a semiconductor device 96 having a semiconductor test section 97 for testing a semiconductor device. The semiconductor device 96 includes a semiconductor test section 97 and a device under test 98.

The semiconductor test section 97 includes the pattern generator 9
0, a shaping pattern generator 92 and a comparator 95. The shaping pattern generator 92 has a variable delay circuit 100.

The pattern generator 90 generates pattern data which is a test pattern to be input to the unit under test 98 and expected value data which the device under test 98 should input and output the pattern data. The pattern generator 90 outputs the pattern data to the shaping pattern generator 92 and outputs the expected value data to the comparator 95. Further, the pattern generator 90 outputs to the variable delay circuit 100 a timing set signal designating generation of a delay clock having a predetermined delay amount according to the operation characteristics of the device under test 98.

The variable delay circuit 100 generates a delay clock having a delay amount specified by the timing set signal. The shaping pattern generator 92 shapes the pattern data based on the delay clock supplied from the variable delay circuit 100, and outputs shaping pattern data corresponding to the operation characteristics of the device under test 98 to the device under test 98. .
The device under test 98 outputs an output value corresponding to the shaping pattern data to the comparator 95. The comparator 95 compares the output value with expected value data supplied from the pattern generator 90,
The quality of the device under test 98 is determined by comparison.

FIG. 6 is a block diagram showing one embodiment of the variable delay circuit 100. The variable delay circuit 100
A first delay compensator 80a, a second delay compensator 80b, a selector 88, and a delay unit 10 are provided. First delay compensator 80a
Has a first ring oscillator 82a, a phase comparator 84a, and a control signal generator 86a. Second delay compensator 80b
Has a second ring oscillator 82b, a phase comparator 84b, and a control signal generator 86b.

The first ring oscillator 82a has M (M is a natural number) voltage-controlled variable delay elements 28 whose delay amount changes based on a control signal. Second ring oscillator 82b
Has N (N is a natural number) voltage-controlled variable delay elements 28 different from the number of voltage-controlled variable delay elements 28 included in the first ring oscillator 82a. The delay unit 10 includes a plurality of selectors 13 and a plurality of voltage-controlled variable delay elements 28 having the same characteristics as the voltage-controlled variable delay elements 28 included in the first ring oscillator 82a and the second ring oscillator 82b. For example, it is preferable that the variable delay circuits 100 are generated in the same semiconductor device.

In the first delay compensator 80a, the first ring oscillator 82a generates a first oscillation clock having a first cycle and outputs the first oscillation clock to the phase comparator 84. The cycle of the first oscillation clock is set based on a first control signal for controlling a delay amount. The phase comparator 84 compares the phase of the first oscillation clock with the phase of a reference clock having a predetermined period, and outputs a comparison result. For example, the phase comparator 84 may output the phase difference between the first oscillation clock and the reference clock, which is the comparison result, as a voltage value. Control signal generator 86a
Generates the first control signal based on the comparison result supplied from the phase comparator 84a, and generates the first ring oscillator 82a
And selector 88.

The control signal generator 86a may generate the first control signal such that the phase of the first oscillation clock matches the phase of the reference clock. Therefore, for example, when the cycle of the reference clock is T, the control signal generator 86a
Each voltage-controlled variable delay element 28 included in the first ring oscillator 82a generates a first control signal so as to generate a T / M delay amount. In another embodiment, the control signal generator 86a generates the first control signal such that the phase of the clock obtained by dividing the reference clock and the phase of the first oscillation clock match. You may.

In the second delay compensator 80b, the second ring oscillator 82b has N (N is a natural number) voltage-controlled variable delay elements 28. For example, when the period of the reference clock is T, a control signal is generated. The unit 86b is configured such that each voltage-controlled variable delay element 28 of the second ring oscillator 82b has a T
A second control signal is generated so as to generate a delay amount of / N. Second ring oscillator 8 included in second delay compensator 80b
2b, the functions and operations of the phase comparator 84b and the control signal generator 86b are the same as the functions and operations of the first ring oscillator 82a, the phase comparator 84a and the control signal generator 86a of the first delay compensator 80a. Is omitted.

The selector 88 applies either the first control signal or the second control signal to each of the voltage-controlled variable delay elements 28 included in the delay unit 10 based on delay data designating a combination of delay elements. Supply. Delay unit 1
0 has the same characteristics as the voltage-controlled variable delay element 28 of the first ring oscillator 82a and the second ring oscillator 82b, so that when the first control signal is supplied, T / M can be generated. Further, when the second control signal is supplied, T /
N delay amounts can be generated.

FIG. 7 is a block diagram showing one embodiment of the variable delay circuit 100. The variable delay circuit 100
It includes a first delay compensator 20a, a second delay compensator 20b, and a delay unit 10. The first delay compensator 20a includes a first reference delay unit 26a, a phase comparator 22a, and a control signal generator 24.
a. The second delay compensator 20b includes a second reference delay 26b, a phase comparator 22b, and a control signal generator 24b.

The first reference delay unit 26a has N voltage-controlled variable delay elements 28 (N is a natural number) whose delay amount changes based on the first control signal generated by the first delay compensation unit 20a. The second reference delay unit 26b has (N + 1) voltage-controlled variable delay elements 29 (N is a natural number) whose delay amount changes based on the second control signal generated by the second delay compensation unit 20b. The voltage control type variable delay element 28 and the voltage control type variable delay element 29 have the same configuration and characteristics, and differ only in the supplied control signal. It is preferable that each of the first reference delay unit 26a and the second reference delay unit 26b has a different number of voltage-controlled variable delay elements. The delay unit 10 includes a voltage-controlled variable delay element (28, 2) having the same characteristics as the voltage-controlled variable delay element 28 included in the first reference delay unit 26a and the second reference delay unit 26b.
9) and a plurality of selectors 13. For example, it is preferable that the variable delay circuits 100 are generated in the same semiconductor device.

In the first delay compensating unit 20a, the first reference delay unit 26a delays a reference clock having a predetermined cycle by N (N is a natural number) voltage-controlled variable delay elements 28, and the first reference delay unit 26a A delay clock is generated and output to the phase comparator 22a. The phase comparator 22a compares the phase of the reference clock with the phase of the first delay clock, and outputs a comparison result to the control signal generator 24a.

The control signal generator 24a includes a phase comparator 22
a, the voltage-controlled variable delay element 28
Generates a first control signal that changes the amount of delay generated by the first control unit and supplies the first control signal to the first reference delay unit 26a and the delay unit 10.
For example, when the cycle of the reference clock is T, the control signal generator 24a generates the first control signal so that each voltage-controlled variable delay element 28 generates a delay amount of T / N. In another embodiment, the control signal generator 24a includes:
The phase of the clock obtained by dividing the reference clock and the first
The first control signal may be generated such that the phase of the first control signal coincides with that of the delay clock.

In the second delay compensator 20b, the second reference delay unit 26b has (N + 1) (N is a natural number) voltage-controlled variable delay elements 29. For example, when the cycle of the reference clock is T, The control signal generator 24b generates a second control signal so that each voltage-controlled variable delay element 29 generates a delay amount of T / (N + 1). The second reference delay unit 26b of the second delay compensator 20b, the phase comparator 2
2b and the function and operation of the control signal generator 24b
Since the functions and operations of the first reference delay unit 26a, the phase comparator 22a, and the control signal generation unit 24a included in the delay compensation unit 20a are the same, description thereof will be omitted.

The delay unit 10 generates a desired amount of delay based on delay data designating a combination of delay elements.
The input signal is delayed by selecting either the voltage control type variable delay element 28 or the voltage control type variable delay element 29. In another embodiment, a selector for distributing a plurality of control signals for setting a predetermined delay amount to the voltage-controlled variable delay element 28 is provided, and a voltage-controlled variable delay element is generated based on a desired delay amount generated by the delay unit 10. The control voltage applied to the delay element 28 may be distributed.

FIG. 8 shows the phase comparators (22a, 22a) of the variable delay circuit 100 described with reference to FIGS.
b, 84a, 84b) and control signal generators (24a,
4b, 86a, 86b) is a block diagram illustrating one embodiment. Phase comparators (22a, 22b, 84a, 8
4b) and control signal generators (24a, 24b, 86a,
86b), the phase comparator 22b has the same configuration and operation.
a and the control signal generator 24a.

The phase comparators 22a and 22b include flip-flops 36a and 36b, a delay element 38, and an AND circuit 4.
0, FET 42, FET 44 and capacitor 46. The control signal generators 24a and 24b are
8, a logical threshold voltage generator 50 and a differential amplifier circuit 52 are provided.

The flip-flop 36a has a logic value "1" based on the positive power supply voltage Vdd input to the terminal D.
From the terminal Q to the AND circuit 40 at the rising timing of the pulse of the reference clock. Further, the logic value “0” is output from the inverted output terminal Q to the FET 42. F
ET42 outputs the logical value “0” from the flip-flop 36a.
The gate is opened for the period during which is supplied, and the positive power supply voltage Vdd is output to the capacitor 46.

The flip-flop 36b has a logic value "1" based on the positive power supply voltage Vdd input to the terminal D.
Is output from the terminal Q to the AND circuit 40 and the FET 44 at the rising timing of the pulse of the delay clock supplied from the first reference delay unit 26a. The FET 44 opens its gate for a period during which the logic value “1” is supplied from the flip-flop 36 b and outputs the negative power supply voltage Vss to the capacitor 46.

The AND circuit 40 includes a flip-flop 36
The logical product of the logical values supplied from the terminal Q of a and the terminal Q of the flip-flop 36b is output to the delay element 38.
The delay element 38 delays the pulse indicated by the logical value “1” supplied from the AND circuit 40 by a predetermined amount and outputs the delayed pulse to the reset terminals R of the flip-flops 36a and 36b. Therefore, the capacitor 46 generates a potential indicating the phase difference between the reference clock and the delayed clock.

The differential amplifier circuit 48 amplifies the potential difference between the potential of the capacitor 46 and the reference potential Vc, generates a control signal Vn for changing the delay amount of the voltage-controlled variable delay element 28, and generates a logical threshold value. The voltage is output to the voltage generation unit 50 and the voltage-controlled variable delay element 28 described with reference to FIGS. 6 and 7.
In the present embodiment, the delay amount of the voltage-controlled variable delay element 28 is determined by two control signals, a control signal Vn and a control signal Vp.

The reference potential Vc is preferably a logical threshold voltage of the voltage-controlled variable delay element 28 determined by the ratio of the control signal Vn, the control signal Vp, the threshold voltage of the FET, and the drain current coefficient. For example, since the logical threshold voltage of a normal CMOS gate is near the midpoint between the positive power supply voltage Vdd and the negative power supply voltage Vss, the reference potential Vc is the midpoint potential between the positive power supply voltage Vdd and the negative power supply voltage Vss. It may be.

The logical threshold voltage generating section 50 may be the voltage-controlled variable delay element 28 described with reference to FIGS. 6 and 7, and the logical threshold voltage when the control signal Vp and the control signal Vn are applied. The voltage Vc 'is generated to generate the differential amplifier circuit 52
Output to

The differential amplifier circuit 52 amplifies the potential difference between the midpoint potential Vc and the logical threshold voltage Vc 'to perform negative feedback control so that the midpoint potential Vc and the logical threshold voltage Vc' become equal. The control signal Vp is applied to the logical threshold voltage generator 50 and the voltage-controlled variable delay element 2 described with reference to FIGS.
8 is output.

FIG. 9A is a circuit diagram of the voltage-controlled variable delay elements 28 and 29 included in the variable delay circuit 100 described with reference to FIGS. In the figure, Vdd is a positive power supply voltage, and Vss is a negative power supply voltage. The voltage-controlled variable delay elements 28 and 29 include transistors (10
2, 104, 106, 108). The transistor 102 changes the impedance between the source and the drain based on the potential of the control signal Vp supplied to the terminal Vp. The transistor 108 changes the impedance between the source and the drain based on the potential of the control signal Vn supplied to the terminal Vn. For example, the transistors may be CMOS.

The voltage-controlled variable delay elements 28 and 29 change the amount of delay generated based on the control signal Vp and the control signal Vn. As the potential of the control signal Vp decreases and / or the potential of the control signal Vn increases, the amount of delay generated by the voltage-controlled variable delay elements 28 and 29 decreases. Conversely, as the potential of the control signal Vp increases and / or as the potential of the control signal Vn decreases, the amount of delay generated by the voltage-controlled variable delay elements 28 and 29 increases.

FIG. 9B is a circuit diagram of the voltage-controlled variable delay elements 28 and 29 included in the variable delay circuit 100 described with reference to FIGS. In the figure, Vdd is a positive power supply voltage, and Vss is a negative power supply voltage. The control signal Vp is input to the control terminal Vp, and the control signal Vn is input to the control terminal Vn. The voltage control type variable delay element 28 has transistors (110 and 112). The transistor 110 changes the impedance between the source and the drain based on the potential of the control signal Vp supplied to the terminal Vp. The transistor 112 has a terminal V
n based on the potential of the control signal Vn supplied to the
Change the impedance between the drains. For example, the transistors may be CMOS.

The voltage-controlled variable delay elements 28 and 29 change the amount of delay generated based on the control signal Vp and the control signal Vn. As the potential of the control signal Vp decreases and / or the potential of the control signal Vn increases, the amount of delay generated by the voltage-controlled variable delay elements 28 and 29 decreases. Conversely, as the potential of the control signal Vp increases and / or as the potential of the control signal Vn decreases, the amount of delay generated by the voltage-controlled variable delay elements 28 and 29 increases.

FIG. 10 is a block diagram showing one embodiment of the variable delay circuit 100. Variable delay circuit 100
Includes a first delay compensator 54a, a second delay compensator 54b, and a delay unit 10. The first delay compensator 54a includes a first reference delay 56a, a phase comparator 58a, and a control signal generator 60a. The second delay compensator 54b includes a second reference delay 56b, a phase comparator 58b, and a control signal generator 60.
b.

The first reference delay section 56a has M (M is a natural number) voltage / load capacitance control type variable delay elements 72 for changing the delay amount using the drive impedance and the load capacitance. The second reference delay unit 56b includes a first reference delay unit 56a.
Have N (N is a natural number) voltage / load capacitance control type variable delay elements 72 less than the voltage / load capacitance control type variable delay elements 72 included in.

In the present embodiment, the delay amount of the voltage / load capacitance control type variable delay element 72 is controlled by the control signal VDP and control signal VDN for controlling the driving impedance, and the capacitance load control signal VCP and the capacitance load for controlling the capacitance load. Determined by signal VCN.

The delay section 10 has a minute variable delay section 71 and a variable delay section 73. The minute variable delay unit 71 and the variable delay unit 73 are a voltage / load capacitance control type variable delay element 72 included in the first reference delay unit 26a and the second reference delay unit 26b.
And a plurality of voltage / load capacitance control type variable delay elements 72 having the same characteristics as the above. For example, the variable delay circuit 100
Preferably, they are created on the same semiconductor device. Further, the variable delay unit 73 has a plurality of selectors 13.

In the first delay compensating section 54a, the voltage / load capacitance control type variable delay element 72 of the first reference delay section 56a is set to a state in which no capacitive load is used. The first reference delay unit 56a delays the reference clock having a predetermined cycle by the M voltage / load capacitance control type variable delay elements 72 and outputs the delayed clock to the phase comparator 58a. The phase comparator 58a compares the phase of the reference clock with the phase of the delayed clock, and outputs the comparison result to the control signal generator 6.
0a.

The control signal generator 60a includes a phase comparator 58
The control signal VDP and the control signal VDN are generated based on the comparison result supplied from a and output to the first reference delay unit 56a and the second reference delay unit 56b. In another embodiment, the control signal generator 60a controls the control signal VDP and the control signal VD such that the phase of the clock obtained by dividing the reference clock and the phase of the delayed clock match.
N may be generated.

In the second delay compensating section 54b, the voltage / load capacity control type variable delay element 72 of the second reference delay section 56b is set to use a capacitive load, and the control signal is sent from the first delay compensating section 54a. VDP and control signal VDN
Is supplied. The second reference delay unit 56b delays the reference clock by the N voltage / load capacitance control type variable delay elements 72 and outputs the delayed clock to the phase comparator 58b.
The phase comparator 58b compares the phase of the reference clock with the phase of the delayed clock and outputs a comparison signal to the control signal generator 60b.
Output to The control signal generator 60b is provided with a phase comparator 58
Based on the comparison result supplied from b, a capacitive load control signal VCP and a capacitive load control signal VCN are generated and output to the second reference delay unit 56b. In another embodiment, the control signal generation unit 60b controls the capacitive load control signal VCP and the capacitive load control signal VCN so that the phase of the clock obtained by dividing the reference clock and the phase of the delayed clock match. May be generated.

For example, if the number of the first reference delay units 56a is N (N
Is a natural number) and the second reference delay unit 56b has N-1 voltage / load capacitance control type variable delay elements 72, the cycle of the reference clock is T Then, the first delay compensating unit 54a generates the control signal VDP and the control signal VDN in which each voltage / load capacitance control type variable delay element 72 generates a delay amount of T / N without using the capacitive load.

In the second delay compensator 54b, each voltage / load capacitance control type variable delay element 72 generates a delay amount of T / (N-1). The N-1 voltage / load capacitance control type variable delay elements 72 are provided with a control signal VDP from the first delay compensator 54a.
And the control signal VDN are supplied, the second delay compensator 54b

A capacitance load control signal V for setting a delay amount of T / (N−1) −T / N = T / N / (N−1) by a capacitance load.
A CP and a capacitive load control signal VCN are generated. The control signal VDP, the control signal VDN, the capacitive load control signal VCP, and the capacitive load control signal VCN generated by the first delay compensating unit 54a and the second delay compensating unit 54b are variable voltage / load capacitance control types of the delay unit 10. The signal is supplied to the delay element 72.

The delay unit 10 generates a desired delay amount based on delay data specifying a combination of delay elements.
Whether or not to use the capacitive load of the voltage / load capacitance control type variable delay element 72 of the minute variable delay unit 71 is set.
In addition, a combination of the voltage / load capacitance control type variable delay element 72 included in the variable delay unit 73 generates an integer multiple of the delay amount of each voltage / load capacitance control type variable delay element 72.

For example, if the period of the reference clock is T and the first
When the reference delay unit 56a has N voltage / load capacitance control variable delay elements 72 and the second reference delay unit 56b has N-1 voltage / load capacitance control variable delay elements 72,
The plurality of voltage / load capacitance control type variable delay elements 72 included in the minute variable delay unit 71 each have a relationship of T / (N−1) −T / N = T / N / (N -1) can be varied. The variable delay unit 73 can generate a delay amount that is an integral multiple of the T / N delay amount without using a capacitive load. In another embodiment, a delay amount that is an integral multiple of the delay amount of T / (N−1) may be generated by using the load capacitance. In still another embodiment, a selector for distributing a plurality of control signals for setting a predetermined delay amount to the variable delay element 72 of the voltage / load capacitance control type is provided, based on a desired delay amount generated by the delay unit 10. The control voltage applied to the voltage / load capacitance control type variable delay element 72 may be distributed.

FIG. 11A is a circuit diagram of the phase comparator 58a and the control signal generator 60a described with reference to FIG. The phase comparator 58a has the same configuration as the phase comparator 22a described with reference to FIG. 8 and has the same function and operation, and a description thereof will be omitted. Differential amplifier circuit 48a
The control signal VDN obtained by amplifying the potential difference between the reference potential Vc and the potential of the capacitor 46 indicating the phase difference between the reference clock and the delayed clock is supplied to the logical threshold voltage generator 50.
And outputs to the voltage / load capacitance control type variable delay element 72 included in the variable delay circuit 100 described with reference to FIG.

The logical threshold voltage generator 50 controls the control signal V
It generates a logical threshold voltage Vc ′ when the DN and the control signal VDP are given, and outputs it to the differential amplifier circuit 52a.
The differential amplifier circuit 52a amplifies the potential difference between the logical threshold voltage Vc 'and the reference potential Vc to perform negative feedback control, and controls the control signal VDP so that the midpoint potential Vc and the logical threshold voltage Vc' become equal. Is the logical threshold voltage generator 50, and FIG.
Is output to the voltage / load capacitance control type variable delay element 72 included in the variable delay circuit 100 described with reference to FIG.

FIG. 11B is a circuit diagram showing the phase comparator 58b and the control signal generator 60b described with reference to FIG. The phase comparator 58b has the same configuration as the phase comparator 22a described with reference to FIG. 8 and has the same function and operation, and a description thereof will be omitted. Differential amplifier circuit 48b
The capacitance load control signal VCN obtained by amplifying the potential difference between the reference potential Vc and the potential of the capacitor 46 indicating the phase difference between the reference clock and the delayed clock is obtained by using the logical threshold voltage generator 50 and FIG. Variable delay circuit 1 described
00 has a voltage / load capacitance control type variable delay element 72
Output to

The logical threshold voltage generator 50 generates a logical threshold voltage Vc 'when the capacitive load control signal VCN and the capacitive load control signal VCP are given, and generates the differential amplifier circuit 5.
2b. The differential amplifier circuit 52b amplifies the potential difference between the logical threshold voltage Vc 'and the reference potential Vc to perform negative feedback control, and performs capacitive load control such that the midpoint potential Vc and the logical threshold voltage Vc' become equal. The signal VCP is generated and output to the voltage / load capacitance control type variable delay element 72b.

FIG. 11C is a diagram showing a circuit diagram of the logical threshold voltage generator 50 included in FIG. 11A. The logical threshold voltage generator 50 is an inverting gate, and has a voltage /
It is preferable to have the same characteristics as the inverting gate of the load capacitance control type variable delay element 72. The logical threshold voltage generator 50 includes transistors (114, 116, 118,
120). The transistor 114 changes the impedance between the drain and the source based on the potential of the control signal VDN supplied to the gate terminal. The transistor 120 changes the impedance between the drain and the source based on the potential of the control signal VDP supplied to the gate terminal. The output value of the inverting gate is fed back.
It is preferable that the logical threshold voltage generator 50 included in FIG. 11B is the same circuit as the inverting gate described with reference to FIG. When used as the logical threshold voltage generator 50 shown in FIG.
4 is a capacitive load control signal VCN supplied to the gate terminal.
The impedance between the drain and the source is changed based on the potential of the source. The transistor 120 changes the drain-source impedance based on the potential of the capacitive load control signal VCP supplied to the gate terminal.

FIG. 12 is a circuit diagram of the voltage / load capacitance control type variable delay element 72 included in the variable delay circuit 100 described with reference to FIG. The voltage / load capacitance control type variable delay element 72 includes a voltage control type variable delay unit 77, a time constant control unit 76, a capacitance load switching unit 79, and a capacitor 75. The voltage-controlled variable delay unit 77 includes a transistor (11
4, 116, 118, 120). The capacitive load switching unit 79 includes an inverter 130, a transistor (122,
124). The time constant control unit 76 has transistors (126, 128).

The voltage control type variable delay unit 77 has the same configuration and operation as the voltage control type variable delay element 28 described with reference to FIG. Capacity load switching unit 7
Reference numeral 9 switches whether to use a capacitive load based on the logical value supplied to the terminal CONT. When a capacitive load is used, a logical value “1” is supplied to the terminal CONT. When a capacitive load is not used, the logical value “0” is output from the terminal CONT.
Supplied to

The time constant controller 76 changes the time constant of the capacitor 75. Further, it is desirable that the time constant control unit 76 is inserted in series between the capacitor 75 and the output terminal of the voltage / load capacitance control type variable delay element 72. In the present embodiment, the time constant control unit 76 includes the transistor (1
26, 128).

In the time constant control section 76, the transistor 126 operates according to the capacitive load control signal V supplied to the gate terminal.
The impedance between the drain and the source is changed based on the potential of CN. The transistor 128 changes the impedance between the drain and the source based on the potential of the capacitive load control signal VCP supplied to the gate terminal. For example, transistors (126, 128) may be N-channel and P-channel CMOS. For example, as the potential of the capacitive load control signal VCN increases and / or as the potential of the capacitive load control signal VCP decreases, the impedance decreases and the amount of delay generated by the capacitive load increases.

Further, as the potential of the capacitive load control signal VCN decreases and / or as the potential of the capacitive load control signal VCP increases, the impedance increases and the delay generated by the capacitive load decreases. Capacitor 75 has a predetermined capacity. The voltage / load capacity control type variable delay element 72 generates a delay amount based on the impedance of the time constant control unit 76 and the capacity of the capacitor 75.

FIG. 13 is a block diagram showing one embodiment of the variable delay circuit 100. Variable delay circuit 100
Includes a first delay compensator 62a, a second delay compensator 62b, and a delay unit 10. The first delay compensator 62a includes a first reference delay unit 68a, a phase comparator 64a, and a control signal generator 66a. The second delay compensator 62b includes a second reference delay unit 68b, a phase comparator 64b, and a control signal generator 66.
b.

The first reference delay section 68a has M (M is a natural number) drive impedance control type variable delay elements 74 for changing the delay amount by changing the drive impedance.
The second reference delay unit 68b has N (N is a natural number) drive impedance control type variable delay elements 74 different from the first reference delay unit 68a.

The delay section 10 has a minute variable delay section 81 and a variable delay section 83. The minute variable delay section 81 and the variable delay section 83 include a drive impedance control type variable delay element 74 having the same characteristics as the drive impedance control type variable delay element 74 included in the first reference delay section 68a and the second reference delay section 68b. Have multiple. For example, the variable delay circuit 1
00 are preferably generated in the same semiconductor device. Further, the variable delay unit 83 has a plurality of selectors 13.

In the present embodiment, the delay amount of the drive impedance control type variable delay element 74 is determined by a control signal VDN1, a control signal VDP1, a control signal VDN2, and a control signal VDP2 for controlling the drive impedance.

In the first delay compensating section 62a, the first reference delay section 68a generates a delayed clock by delaying the reference clock by N driving impedance control type variable delay elements 74. The phase comparator 64a compares the phase of the reference clock having a predetermined cycle with the phase of the delayed clock, and outputs a comparison result to the control signal generator 66a. The control signal generator 66a controls the control signal VDP1 and the control signal VDN based on the comparison result supplied from the phase comparator 64a.
1 is generated.

In the second delay compensating section 62b, the second reference delay section 68b delays the reference clock by the M driving impedance control type variable delay elements 74 to generate a delayed clock. The phase comparator 64b compares the phase of the reference clock with the phase of the delayed clock, and outputs a comparison result to the control signal generator 66b. The control signal generator 66b
A control signal VDP2 and a control signal VDN2 are generated based on the comparison result supplied from the phase comparator 64b. In another embodiment, the control signal generator 66a and the control signal generator 66b control the control signal VDN1 and the control signal VDN1 such that the phase of the clock obtained by dividing the reference clock and the phase of the delayed clock match. The VDP1, the control signal VDN2, and the control signal VDP2 may be generated.

The delay unit 10 generates a desired amount of delay based on delay data specifying a combination of delay elements.
The delay amount of the drive impedance control type variable delay element 74 included in the minute variable delay section 81 is changed. Further, the input signal is delayed by a combination of the drive impedance control type variable delay element 74 included in the variable delay section 83.

The minute variable delay section 81 includes the first delay compensation section 6
Control signal VDP1 and control signal VD supplied from 2a
N1 and one of the control signal VDP2 and the control signal VDN2 supplied from the second delay compensator 62b are switched to generate a minute delay amount.

The variable delay unit 83 includes a first delay compensator 62a
Control signal VDP1 and control signal VDN1 supplied from
Generates a delay amount that is an integral multiple of T / M. In another embodiment, the variable delay unit 83 includes the second delay compensator 62b
Control signal VDP2 and control signal VDN2 supplied from
, A delay amount that is an integral multiple of T / N may be generated. In still another embodiment, a plurality of control signals for generating a predetermined amount of delay are controlled by a drive impedance control type variable delay element 74.
And a control signal to be supplied to the drive impedance control type variable delay element 74 based on a desired delay amount generated by the delay unit 10.

FIG. 14 is a circuit diagram of the phase comparator 64a and the control signal generator 66b included in the variable delay circuit 100 described with reference to FIG. The configuration and operation of the phase comparator 64a are the same as the configuration and operation of the phase comparator 22a described with reference to FIG. The control signal generator 66a includes a differential amplifier 67a, a logic threshold voltage generator 70a, and a differential amplifier 69a. The logic threshold voltage generator 70a includes transistors (132, 134, 1).
44, 146, 136, 138).

The differential amplifier 67a amplifies the potential difference between the potential of the capacitor 46 indicating the phase difference between the reference clock and the delayed clock and the reference potential Vc to generate the control signal VDN1.

The logic threshold voltage generator 70a outputs the control signal V
The logic threshold voltage Vc ′ when the control signal VDN2 is applied is generated. The logic threshold voltage generation unit 70a
The driving impedance control type variable delay element 74 (see FIG. 15) may be in a state where a logical value “0” is input to the terminal CONT, and it is preferable to have the same transistor.

The differential amplifier 69a amplifies the potential difference between the logic threshold voltage Vc 'supplied from the logic threshold voltage generator 70a and the reference voltage Vc to generate a control signal VDP1. The phase comparator 64b and the control signal generator 66b included in the variable delay circuit 100 described with reference to FIG.
4 has the same configuration and operation as those of the phase comparator 64a and the control signal generator 66a described with reference to FIG.

FIG. 15 is a circuit diagram of the driving impedance control type variable delay element 74. The driving impedance control type variable delay element 74 includes transistors (132, 13).
4, 136, 138, 140, 142, 144, 14
6, 148, 150) and inverters 152, 154. Drive impedance control type variable delay element 74
Can select the impedance set by the control signals VDP1 and VDN1 or the impedance set by the control signals VDP2 and VDN2 based on the logical value supplied from the terminal CONT.

When the logical value "0" is supplied from the terminal CONT, the driving impedance control type variable delay element 74
Generates a delay amount with an impedance set by the control signal VDN1 and the control signal VDP1. Control signal V
As the potential of DN1 increases and / or as the potential of control signal VDP1 decreases, the driving impedance decreases, and the amount of delay generated decreases. Further, as the potential of the control signal VDN1 decreases and / or as the potential of the control signal VDP1 increases, the driving impedance increases, and the generated delay amount increases.

When the logical value “1” is supplied from the terminal CONT, the driving impedance control type variable delay element 74
Generates a delay amount with an impedance set by the control signal VDN2 and the control signal VDP2. Control signal V
As the potential of DN2 increases, the drive impedance decreases as the potential of control signal VDP2 decreases, and the generated delay amount decreases. Also, the control signal VD
As the potential of N2 decreases and / or control signal V
As the potential of DP2 increases, the driving impedance increases and the amount of delay generated increases.

As described above, the present invention has been described using the embodiment. However, the technical scope of the present invention is not limited to the scope described in the above embodiment. It is apparent to those skilled in the art that various changes or improvements can be added to the above embodiment. It is apparent from the description of the appended claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

[0101]

As is apparent from the above description, according to the present invention, a desired delay amount can be generated.

[Brief description of the drawings]

FIG. 1 shows a conventional variable delay circuit 100.

FIG. 2 shows a minute variable delay element 12;

FIG. 3 is a graph showing a relationship between delay data and an actually generated delay amount.

FIG. 4 shows a block diagram of a semiconductor test apparatus.

FIG. 5 shows a semiconductor device 96 having a semiconductor test section 97 for testing a device under test 98.

FIG. 6 is a block diagram illustrating one embodiment of a variable delay circuit 100.

FIG. 7 is a block diagram illustrating one embodiment of a variable delay circuit 100.

8 is a circuit diagram of a phase comparator 22a and a control signal generator 24a included in the variable delay circuit 100 described with reference to FIGS. 6 and 7. FIG.

FIG. 9 shows a circuit diagram of a voltage-controlled variable delay element 28.

FIG. 10 is a block diagram illustrating one embodiment of a variable delay circuit 100.

11 shows the phase comparator 58a and the control signal generator 6 included in the variable delay circuit 100 described with reference to FIG.
0a shows a circuit diagram.

FIG. 12 shows a voltage / load capacitance control type variable delay element 72.
FIG.

FIG. 13 is a block diagram showing one embodiment of a variable delay circuit 100.

14 is a variable delay circuit 1 described with reference to FIG.
00 has a phase comparator 64a and a control signal generator 66
The circuit diagram of FIG.

FIG. 15 is a circuit diagram of a driving impedance control type variable delay element 74.

[Explanation of symbols]

10 delay unit, 12 variable delay element, 14
Variable delay unit, 20 delay compensator, 22 phase comparator, 24 control signal generator, 26 reference delay unit, 28 voltage-controlled variable delay element, 36 ...
Flip-flop, 38: delay element, 40: A
ND circuit, 42 ... FET, 44 ... FET, 46
... capacitors, 48 ... differential amplifier circuits, 52 ...
A differential amplifier circuit, 54 a delay compensator, 56 a reference delay unit, 58 a phase comparator, 60 a control signal generator, 62 a delay compensator, 64・ Phase comparator, 66 ・ ・ ・ Control signal generator, 68 ・ ・ ・ Reference delay section, 71 ・ ・ ・ Small variable delay section, 72 ・ ・ ・ Voltage / load capacitance control type variable delay element, 73 ・ ・ ・ Variable Delay section, 74
... Variable delay element of driving impedance control type, 75
..Capacity load unit, 76 ... time constant control unit, 77 ...
Voltage-controlled variable delay section, 79 ... Capacitive load switching section, 8
0: delay compensation unit, 81: minute variable delay unit, 82
... Ring oscillator, 83 ... Variable delay unit, 84 ...
.Phase comparator, 86 ... Control signal generator, 88 ...
Selector, 90: pattern generator, 92: shaped pattern generator, 93: device under test, 94 ...
・ Device contact portion, 95 ・ ・ ・ Comparator, 96 ・ ・ ・ Semiconductor device, 98 ・ ・ ・ Device under test, 100 ・ ・ ・ Variable delay device

[Procedure amendment]

[Submission date] March 16, 2001 (2001.3.1.
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

Claims (19)

[Claims] 1. A variable delay circuit for generating a desired delay amount, comprising: a plurality of reference delay units each having a different number of first variable delay elements whose delay amount changes based on a control signal; A plurality of control signals to be given to the first variable delay elements included in each of the plurality of reference delay elements are respectively generated according to the number of the first variable delay elements included in each of the plurality of reference delay sections. And a delay unit that controls the plurality of second variable delay elements having the same characteristics as the first variable delay element by the plurality of control signals to generate the desired delay amount. A variable delay circuit, comprising: 2. The number of the reference delay units is M (M is a natural number).
A first reference delay unit having the variable delay elements described above, and N (N is a natural number) of the first variable delay elements different from the number of the first variable delay elements included in the first reference delay unit. A second reference delay unit, wherein the delay compensation unit generates the control signal to be provided to the first variable delay element of the first reference delay unit.
The variable delay circuit according to claim 1, further comprising: a delay compensator; and a second delay compensator configured to generate the control signal to be provided to the first variable delay element included in the second reference delay unit. 3. The reference delay unit includes a ring oscillator that has a different number of the first variable delay elements and generates an oscillation clock having a predetermined cycle according to the number of the first variable delay elements. The variable delay circuit according to claim 1, wherein: 4. The delay compensator includes a phase comparator for comparing a phase of a reference clock having a predetermined cycle with a phase of a delay clock obtained by delaying the reference clock by the first variable delay element. 4. The variable delay circuit according to claim 1, further comprising: a control signal generation unit that generates the control signal based on the control signal. 5. The variable delay circuit according to claim 4, wherein the control signal generator generates the control signal such that the phase of the reference clock matches the phase of the delayed clock. 6. The apparatus according to claim 1, further comprising a selector for supplying any one of the plurality of control signals supplied from the delay compensation unit to the second variable delay element. The variable delay circuit according to any one of the above. 7. The first variable delay element includes a capacitor having a predetermined capacitance and a time constant control unit that changes a time constant of the capacitor, and changes a delay amount according to the time constant. The variable delay circuit according to claim 1, wherein: 8. The variable delay circuit according to claim 7, wherein the time constant control section has a transistor and changes a time constant of the capacitor by changing a gate voltage applied to the transistor. 9. A variable delay circuit for generating a desired delay amount to a signal to be output to an output terminal, the variable delay circuit being inserted in series between a capacitor having a predetermined capacitance and the capacitor and the output terminal. A variable delay element having a time constant control unit for changing a time constant of the capacitor, and a variable delay element for changing a delay amount according to the time constant; and selecting the variable delay element based on the desired delay amount. And a delay section for generating the desired delay amount. 10. The variable delay circuit according to claim 9, wherein the time constant control unit has a transistor and changes a time constant of the capacitor by changing a gate voltage applied to the transistor. 11. A semiconductor test apparatus for testing a semiconductor device, comprising: a pattern generator for generating a test pattern to be input to the semiconductor device; and a first variable delay element having a delay amount that changes based on a control signal. A plurality of reference delay units having different numbers, a delay compensation unit for respectively generating a plurality of control signals to be provided to the first variable delay element according to the number of the first variable delay elements, A delay unit that controls a plurality of second variable delay elements having the same characteristic as the variable delay element by the plurality of control signals to generate a delay clock having a delay amount according to an operation characteristic of the semiconductor device; A shaping test pattern generator for shaping the test pattern based on the delay clock to generate a shaping test pattern; and A device contact unit that inputs a test pattern to the semiconductor device, and a comparator that determines pass / fail of the semiconductor device based on an output signal output from the semiconductor device that has input the shaping test pattern. Semiconductor testing equipment. 12. The reference delay unit includes a ring oscillator that has a different number of the first variable delay elements and generates an oscillation clock having a predetermined cycle according to the number of the first variable delay elements. The variable delay circuit according to claim 11, wherein: 13. The device according to claim 11, further comprising a selector for supplying any one of the plurality of control signals supplied from the delay compensation unit to the second variable delay element. Variable delay circuit. 14. The first variable delay element includes a capacitor having a predetermined capacity, and a time constant control unit that changes a time constant of the capacitor, and changes a delay amount according to the time constant. 14. The variable delay circuit according to claim 11, wherein: 15. A semiconductor device having a semiconductor test unit for testing a semiconductor device, wherein the plurality of reference delay units have different numbers of first variable delay elements whose delay amount changes based on a control signal; A delay compensator for respectively generating a plurality of control signals to be provided to the first variable delay element according to the number of first variable delay elements; and a plurality of delay compensation sections having the same characteristics as the first variable delay element. A semiconductor test unit having a delay unit that controls a second variable delay element with the plurality of control signals and generates a timing used for testing a device-under-test based on operating characteristics of the semiconductor device; A semiconductor device comprising: a semiconductor test section; and a device under test to be tested. 16. The reference delay unit includes a ring oscillator that has a different number of the first variable delay elements and generates an oscillation clock having a predetermined cycle according to the number of the first variable delay elements. The variable delay circuit according to claim 15, wherein: 17. The apparatus according to claim 15, further comprising a selector for supplying any one of the plurality of control signals supplied from the delay compensation unit to the second variable delay element. Variable delay circuit. 18. The first variable delay element includes a capacitor having a predetermined capacitance and a time constant control unit that changes a time constant of the capacitor, and changes a delay amount according to the time constant. The variable delay circuit according to any one of claims 15 to 17, wherein: 19. A delay signal generating method for generating a delay signal obtained by delaying an input signal by a desired time, comprising: a plurality of first variable delay elements having different numbers of first variable delay elements whose delay amount changes based on a control signal. Generating a plurality of clocks by a reference delay unit; comparing the phases of the plurality of clocks with a reference clock; and controlling the plurality of clocks based on the compared phases. Correcting each of the signals, controlling the delay amount of the first variable delay element based on the corrected control signal, receiving the control signal, and controlling based on the control signal; A plurality of second variable delay elements having the same characteristics as the first variable delay element are controlled based on the modified control signal to control the input signal. Delay signal generating method, characterized in that it comprises a step of generating the delay signal delayed the desired time.