JP3304926B2 - Voltage correction oscillation device and oscillation frequency control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillating circuit comprising a semiconductor integrated circuit, and more particularly, to a voltage correction oscillating circuit whose oscillation frequency changes in accordance with a power supply voltage.

[0002]

2. Description of the Related Art There is known a voltage correcting oscillator which detects a voltage level of a power supply voltage and controls a frequency of an output signal in accordance with the detected voltage level. As an example of such a voltage correction oscillator, an oscillator circuit described in JP-A-8-65048 is known.

As shown in FIG. 6, this oscillation circuit includes an oscillation vibrator 50 made of quartz or ceramic,
Capacitors 51 and 5 connected to both ends of oscillation oscillator 50
2, oscillation inverters 56 to 60 whose input terminals and output terminals are connected by a feedback resistor 55, a square shaping inverter 53 for shaping a signal output from the oscillation inverter 60 into a square wave, and a power supply voltage VDD. And a voltage detection circuit 54. Oscillation inverters 56-60
Is composed of a switched inverter including a P-channel MOS transistor and an N-channel transistor, as shown in FIG.

The power supply detection circuit 54 detects the detected power supply voltage V
When the DD is low, the control signals S1 to S5 are all set to the high level, and the oscillation inverters 60 to 64 are set to the operating state. As a result, the power supplied to the oscillation oscillator 50 increases, and the oscillation frequency increases.

On the other hand, when the detected power supply voltage VDD is high, the power supply detection circuit 54 sets an arbitrary number of control signals S1 to S5 to low level to reduce the number of oscillating inverters to be activated. Thereby, the oscillation oscillator 5
The power supplied to 0 decreases, and the oscillation frequency drops.

As described above, this voltage-correcting oscillation device varies (controls) the oscillation frequency by changing the number of oscillation inverters to be activated according to the change in the power supply voltage VDD.

[0007]

However, in the above-described voltage-correction oscillation circuit, following the fluctuation of the power supply voltage VDD,
To precisely control (variable) the oscillation frequency, a large number of oscillation inverters are required and a complicated control circuit for controlling the on / off of each oscillation inverter is required. For this reason, this causes a size increase of the voltage correction oscillation device and an increase in cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a voltage-corrected oscillation device which has a simple structure and precisely controls an oscillation frequency in response to a fluctuation in a power supply voltage. I do.

[0009]

According to a first aspect of the present invention, there is provided a voltage-corrected oscillation apparatus comprising: a voltage-controlled oscillator that oscillates at a frequency corresponding to a voltage value of a supplied voltage signal; An output circuit that outputs an output signal of the voltage-controlled oscillator to the outside, a variable delay circuit that delays an output signal of the voltage-controlled oscillator by a time corresponding to a voltage value of the power supply voltage, and an output of the voltage-controlled oscillator. A delay pulse generation circuit that generates a pulse signal having a pulse width corresponding to a delay time of the variable delay circuit based on a signal and an output signal of the variable delay circuit; and a voltage signal that smoothes the pulse signal. And a smoothing circuit for supplying the voltage-controlled oscillator to the voltage-controlled oscillator, wherein an output signal of the voltage-controlled oscillator is output.

According to this configuration, the oscillation frequency output from the voltage-controlled oscillator can be controlled by smoothing the output signal of the voltage-controlled oscillator and the delay pulse signal generated based on the delay signal. Since the delay time can be changed in an analog manner according to the voltage value, it is possible to control the oscillation frequency precisely according to the power supply voltage. Further, since the configuration can be made only by the delay circuit and the pulse generation circuit other than the voltage controlled oscillator, the configuration is also easy.

The pulse generation circuit, for example, takes an exclusive OR of an output signal of the voltage controlled oscillator and an output signal of the variable delay circuit and outputs the result as the pulse signal.

[0012] The smoothing circuit may include an integrating circuit for integrating the voltage of the pulse signal and outputting the integrated signal to the voltage controlled oscillator.

The variable delay circuit operates, for example, using the power supply voltage as an operating voltage, and is constituted by a plurality of cascaded inverter circuits.

The inverter circuit includes, for example, a CMOS inverter circuit in which the power supply voltage (Vdd) is applied to a power supply terminal and a reference voltage (GND) is applied to a ground terminal.

A method for controlling an oscillation frequency according to a second aspect of the present invention is a method for controlling an oscillation frequency in accordance with a voltage value of a power supply voltage, wherein the method includes controlling an oscillation frequency in accordance with a voltage value of a supplied voltage signal. An output step of outputting a signal having a frequency that has been adjusted, a delay signal generation step of generating a delay signal obtained by delaying the output signal by a time corresponding to a voltage value of the power supply voltage, An exclusive OR operation is performed to generate a pulse signal having a pulse width corresponding to the delay time, and the pulse signal is smoothed to generate the voltage signal.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a voltage correction oscillator according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a voltage correction oscillator according to an embodiment of the present invention.

As shown in the figure, this voltage-correcting oscillator includes a delay block 1 and an EXOR (EXplusive).
OR) Gate 2, low-pass filter 3, VCO
(Voltage Controlled Oscil
and a waveform shaping inverter 5.

The delay block 1 has an input terminal connected to the output terminal A of the VCO 4 and delays an input signal in accordance with the voltage level of the power supply voltage Vdd applied to the power supply voltage input terminal. Output to C. The delay block 1 includes, for example, a plurality of cascade-connected buffers 10a to 10m, as shown in FIG. The number of buffers 10a to 10m connected in cascade can be arbitrarily set according to the time to be delayed.

The buffers 10a to 10m have a power supply voltage Vd
It is connected between the power supply voltage input terminal to which d is applied and the ground. The first-stage buffer 10a has an input terminal connected to the input terminal of the delay block 1, and an output terminal connected to the input terminal of the subsequent (second-stage) buffer 10b.

As shown in FIG. 2, buffers 10a to 10m include P-channel MOS (hereinafter, PMOS) transistors 11a to 13a and N-channel MOS (hereinafter, NMO).
S) CMOS including transistors 14a to 16a
(Complementary MOS) circuit.

The PMOS transistor 11a has a gate terminal connected to the input terminal of the buffer 10a, a source terminal connected to the power supply voltage input terminal, and a drain terminal connected to the PMOS transistor 11a.
It is connected to the source terminal of S transistor 12a.
The PMOS transistor 12a has a gate terminal connected to the input terminal of the buffer 10a, and a drain terminal connected to the PMOS transistor 12a.
It is connected to the source terminal of transistor 13a. P
The MOS transistor 13a has a gate terminal connected to the input terminal of the buffer 10a, and a drain terminal connected to the output terminal of the buffer 10a.

The NMOS transistor 14a has a gate terminal connected to the input terminal of the buffer 10a, a drain terminal connected to the output terminal of the buffer 10a,
The source terminal is connected to the drain terminal of the NMOS transistor 15a. The NMOS transistor 15a
The gate terminal is connected to the input terminal of the buffer 10a, and the source terminal is connected to the drain terminal of the NMOS transistor 16a. The NMOS transistor 16a has a gate terminal connected to the input terminal of the buffer 10a, and a source terminal connected to the ground.

Each of the buffers 10a to 10m charges and discharges a parasitic capacitance to delay an input signal. Here, when the power supply voltage Vdd decreases, the charging voltage of the parasitic capacitance decreases, and the on-resistance of each transistor increases. Therefore, the charging / discharging time of the parasitic capacitance becomes longer, and as a result, the delay time becomes longer. On the other hand, when the power supply voltage Vdd increases, the charging voltage of the parasitic capacitance increases, and the on-resistance of each transistor decreases. Therefore, the charging / discharging time of the parasitic capacitance is shortened, and as a result, the delay time is shortened.

The EXOR gate 2 has one input terminal C connected to the output terminal of the delay block 1 and the other input terminal B connected to the output terminal A of the VCO 4, and takes an exclusive OR of both input signals. Output to the input terminal D of the low-pass filter 3.

The input terminal D of the low-pass filter 3 is EX.
Connected to the output terminal of OR gate 2 and EXOR gate 2
To generate an oscillation frequency control signal by integrating the output signal of
Output to the input terminal E of VCO4. This low-pass filter 3 includes, for example, resistors R1 and R2 as shown in FIG.
And capacitors C1 and C2.

The VCO 4 has an input terminal E connected to the output terminal of the low-pass filter 3, oscillates at a frequency corresponding to the voltage value of the signal output from the low-pass filter 3, and outputs an oscillation signal to an input terminal of the waveform shaping inverter 5. I do. Also,
The output signal of the VCO 4 is fed back and branched into two, and output to the input terminal of the delay block 1 and one input terminal B of the EXOR gate 2. The VCO 4 has a characteristic that the oscillation cycle increases as the voltage supplied to the input terminal increases.

The input terminal of the waveform shaping inverter 5 is V
The VCO 4 is connected to the output terminal A of the CO 4 and shapes the voltage waveform of the oscillation signal output from the VCO 4 and outputs the shaped signal as an output signal of the voltage correction oscillator.

Next, the operation of the voltage correction oscillator having the above configuration will be described with reference to FIGS.

First, it is assumed that the power supply voltage Vdd applied to the power supply voltage input terminal of the voltage correction oscillator is in a stable state at the voltage V1.

The VCO 4 inputs the signal output from the low-pass filter 3 via the input terminal E, oscillates at a frequency (f1) corresponding to the voltage value (e1) of the input signal, and FIG. An oscillation signal having a predetermined pulse width as shown in (1) is output to the waveform shaping inverter 5 through the output terminal A. This oscillation signal is fed back and supplied also to the delay block 1 and the EXOR gate 2.

As shown in FIG. 3C, the delay block 1 delays the input oscillation signal by a time t1 corresponding to the power supply voltage Vdd, and supplies the delayed signal to one input terminal C of the EXOR gate 2. Output

The other input terminal B of the EXOR gate 2 receives the same signal as the oscillation signal shown in FIG. The EXOR gate 2 takes an exclusive OR of the two input signals, generates a pulse signal having a pulse width t1 as shown in FIG. 3D, and outputs the pulse signal to the low-pass filter 3.

The low-pass filter 3 inputs a pulse signal having a pulse width t1 as shown in FIG. 3D through an input terminal D, smoothes the pulse signal, and outputs a voltage e1 as shown in FIG.
And output to the VCO 4.

The VCO 4 oscillates at a frequency f1 corresponding to the voltage e1 of the signal supplied from the low-pass filter 3 via the input terminal E. Thus, in a stable state,
The oscillation frequency f1 of the VCO 4 is balanced with the output voltage e1 of the low-pass filter 3, and the VCO 4 continues to oscillate at the constant frequency f1. The waveform shaping inverter 5 shapes the voltage waveform of the input oscillation signal and outputs it as an output signal of the voltage correction oscillation device.

Next, it is assumed that the power supply voltage Vdd of the power supply correction oscillation device has dropped from V1 to V2 for some reason.

As described with reference to FIG.
Oscillates at a frequency f1 corresponding to the voltage value of the input signal, and converts a signal having a predetermined pulse width as shown in FIG. 4A into the waveform shaping inverter 5, the delay block 1, and the EXO.
Output to R gate 2.

The first to m-th buffers 10a to 10m of the delay block 1 charge and discharge with a parasitic capacitance and a predetermined time constant to delay the input signal, but when the power supply voltage Vdd is V1
From V2 to V2, the charging voltage of the parasitic capacitance decreases, the on-resistance of each transistor increases, the charge / discharge time increases, and as a result, the delay time increases. Assuming that the increased delay time is α, the delay block 1 delays the rise of the signal by a time t2 (t2 = t1 + α) corresponding to the voltage value of the input signal, as shown in FIG. Output to EXOR gate 2.

The EXOR gate 2 receives the signal shown in FIG. 4 (B) and the delay signal shown in FIG. 4 (C), performs an exclusive OR operation, and has a pulse width as shown in FIG. 4 (D). A pulse signal at t2 is generated and output to the low-pass filter 3.

The low-pass filter 3 inputs a signal having a pulse width as shown in FIG. 4D through an input terminal D and smoothes the signal. Since the pulse width has increased from t1 to t2, the low-pass filter 3 generates an oscillation frequency control signal having a voltage higher than the voltage e1 shown in FIG. 3E as shown in FIG. Output.

The VCO 4 inputs an oscillation frequency control signal of a relatively high voltage as shown in FIG. 4E via an input terminal E, and gradually increases the frequency. Thus, as shown in FIGS. 5A to 5E, the oscillation frequency f
2, the voltage e2 of the frequency control signal, and the delay time t2 are stabilized in a state corresponding to the power supply voltage Vdd (= V2).

Thereafter, when the power supply voltage Vdd further decreases, the oscillation frequency further increases through the same process as described above. On the other hand, when the power supply voltage Vdd increases, the delay time in the delay block 1 becomes shorter than t2, the voltage of the oscillation frequency control signal decreases, and the oscillation frequency of the VCO 4 decreases. Then, for example, when the power supply voltage Vdd is changed from V2 to V1
, The oscillation frequency is f1 and the delay time is t
1. The voltage of the oscillation frequency control signal is stabilized at e1.

As described above, the voltage correction oscillator according to the present embodiment integrates the exclusive OR signal of the feedback signal of VCO 4 and the signal obtained by delaying the feedback signal by the time corresponding to the power supply voltage Vdd. Thus, the oscillation frequency of the VCO 4 can be controlled according to the fluctuation of the power supply voltage with a simple configuration of supplying the VCO 4 to the VCO 4.

The present invention is not limited to the above embodiment, but can be arbitrarily changed. For example, the PMOS transistors 11a to 13a and the NM
By changing the number of OS transistors 14a to 16a, the delay time can be adjusted by changing the on-resistance values of the PMOS transistor and the NMOS transistor.

[0045]

As described above, according to the present invention, the oscillation frequency can be precisely controlled with a simple configuration in response to the fluctuation of the power supply voltage.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a voltage correction oscillation device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a delay block and a buffer according to the embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the voltage correction oscillator.

FIG. 4 is a timing chart for explaining an operation in a transient state of the voltage correction oscillation device when a supplied power supply voltage fluctuates low.

FIG. 5 is a timing chart for explaining an operation in a stable state of the voltage correction oscillator when the supplied power supply voltage fluctuates low.

FIG. 6 is a block diagram illustrating an example of a conventional voltage correction oscillation device.

FIG. 7 is a block diagram showing an oscillation inverter of a conventional voltage correction oscillation device.

[Explanation of symbols]

Reference Signs List 1 delay block 2 EXOR gate 3 low-pass filter 4 VCO 5, 53 waveform shaping inverter 10 a to 10 m buffer 11 a, 12 a, 13 a P-channel MOS transistor 14 a, 15 a, 16 a N-channel MOS transistor Vdd, VDD power supply voltage input terminal R55 resistor 50 Oscillator 56-60 Oscillator inverter 51, 52 Capacitor 54 Voltage detection circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03B 5/32 H03B 5/04 H03H 11/20

Claims (6)

(57) [Claims] 1. A voltage-corrected oscillator for changing an oscillation frequency according to a voltage value of a power supply voltage, comprising: a voltage-controlled oscillator oscillating at a frequency corresponding to a voltage value of a supplied voltage signal; An output circuit that outputs an output signal to the outside; a variable delay circuit that delays an output signal of the voltage controlled oscillator by a time corresponding to a voltage value of the power supply voltage; an output signal of the voltage controlled oscillator; and the variable delay A pulse generation circuit that generates a pulse signal having a pulse width corresponding to a delay time of the variable delay circuit based on an output signal of the circuit; and a voltage control circuit that generates the voltage signal by smoothing the pulse signal. And a smoothing circuit for supplying to the oscillator. 2. The delay pulse generation circuit according to claim 1, wherein the delay pulse generation circuit outputs a pulse signal of an exclusive OR of an output signal of the voltage controlled oscillator and an output signal of the variable delay circuit. Oscillator for voltage correction. 3. The voltage correction oscillator according to claim 1, wherein the smoothing circuit includes an integration circuit for integrating the voltage of the pulse signal and outputting the integrated signal to the voltage controlled oscillator. apparatus. 4. The variable delay circuit according to claim 1, wherein the variable delay circuit operates using the power supply voltage as an operating voltage, and includes a plurality of cascaded inverter circuits. 3. The voltage-corrected oscillator according to claim 1. 5. The inverter circuit according to claim 1, wherein said power supply voltage is applied to a power supply terminal, and a reference voltage is applied to a ground terminal.
The voltage correction oscillator according to claim 4, comprising a MOS inverter circuit. 6. A method for controlling an oscillation frequency according to a voltage value of a power supply voltage, comprising: an output step of outputting a signal having a frequency corresponding to a voltage value of a supplied voltage signal; and an output of the output step A delay step of generating a delay signal by delaying a signal by a time corresponding to the voltage value of the power supply voltage; and taking an exclusive OR of the output signal and the delay signal,
An oscillation frequency control method, comprising: a delay pulse generation step of generating a pulse signal having a pulse width corresponding to the delay time; and a step of generating the voltage signal by smoothing the pulse signal.