JP2001024485A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit in which the fluctuation of a generated clock can be reduced against the fluctuation of a power supply voltage. SOLUTION: A PLL circuit is provided with a phase comparator, a loop filter, and a voltage control transmitter including a voltage/current converting circuit for converting a control voltage outputted from the loop filter into current, and a CMOS ring oscillator 1 constituted of plural ring oscillators 5 having current sources corresponding to the output current. The voltage/ current converting circuit 7 uses a variable resistance changing according to the fluctuation of a power supply voltage as an element for deciding the output current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL (Phase Locked Loop) circuit in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram showing a basic configuration of a conventional PLL circuit. In the figure, 101 is a phase comparator PC, 102 is a low-pass filter LPF, 103 is an amplifier, and 104 is a voltage controlled oscillator VCO. is there. This operation will be described. The reference signal fref and the output signal fvc of the voltage controlled oscillator are input to the PC and the error component fref is input.
-Fvc is output. Thereafter, a DC component is extracted from the output from the phase comparator by a low-pass filter to obtain a correction value voltage. The output signal fvc of the voltage controlled oscillator accurately matches the reference signal fref by repeating the loop by the loop filter formed by these.

FIG. 4 shows a conventional voltage-controlled oscillator of a PLL circuit as shown in FIG.
1 is a CMOS ring oscillator, 2a to 2e are P-type MOS transistors for current control, 3a to 3e are N-type MOS transistors for current control, and 4a to 4e are P-type MOS transistors 2a to 2e on the P-type MOS transistor side. Is an odd number of Cs connected to the N-type MOS transistors 3a to 3e on the N-type MOS transistor side.
MOS inverters 5 and CMOS inverters 4a to 4e
Is a ring oscillator connected in a ring shape, and 6 is a buffer gate for amplifying the output of the ring oscillator 5.
The above-described CMOS ring oscillator 1 includes a ring oscillator 5 and a buffer gate 6. Here, the ring oscillator is a circuit in which an odd-numbered logic gate of an inverted output such as an inverter, a NAND, or a NOR is connected in series, and the output of the last stage is returned to the input of the first stage and self-oscillates.

[0004] Reference numeral 7 denotes a voltage-current conversion circuit, and 10a '.
Is a first current synthesis circuit, 10b is a second current synthesis circuit,
8 is the output Vin from the loop filter of the PLL circuit +
3f is an N-type MOS having an output of the differential amplifier 8 as a gate electrode and a negative input as a source electrode.
A transistor 2f is a P-type MOS transistor provided between the N-type MOS transistor 3f and the power supply voltage VDD;
2g is a P-type transistor forming a current mirror circuit with the P-type MOS transistor 2f, 3g is an N-type transistor provided between the P-type MOS transistor 2g and the ground potential GND, and 9a is a difference from the source electrode of the N-type MOS transistor 3f. Connection between the negative input of the operational amplifier 8 and the ground voltage G
The first current combining circuit 10a 'is a resistor provided between the differential amplifier 8 and the N-type MOS transistor 3.
f, a resistor 9a, and a P-type MOS transistor 2f, and the second current combining circuit 10b includes a P-type MOS transistor 2g and an N-type MOS transistor. The P-type MOS transistor 2g and the N-type MOS transistor 3g constitute a current mirror circuit with the current control P-type MOS transistors 2g to 2e and the current control N-type MOS transistors 3a to 3e of the CMOS ring oscillator 1, respectively. I have.

Next, the operation will be described. When the output Vin from the loop filter is input to the voltage controlled oscillator, the differential amplifier 8 acts so that the + side input and the − side input have the same potential, so that the output Vin and the − side input have the same potential. Thus, the gate potential of the N-type MOS transistor 3f is controlled. Since the negative input of the differential amplifier 8 is connected to the resistor 9a, the voltage Vin is applied to the resistor 9a. Therefore, the output current I determined by the potential Vin and the resistor 9a flows through the first current synthesis circuit 10a '. On the other hand, the same current I flows in the second current synthesis circuit 10b because the P-type transistor 2f and the P-type MOS transistor 2g form a current mirror circuit.

On the other hand, the transmission frequency fvc of the CMOS ring oscillator 1 is determined by the time for charging and discharging the parasitic capacitance of each output of the CMOS inverters 4a to 4e. The magnitude of the current required for charging is determined by the current flowing through the current control P-type MOS transistors 2a to 2e.
Constitutes a current mirror circuit with the P-type MOS transistor 2f, so that the current becomes the same as the current of the first current combining circuit 10a '.

The magnitude of the current required for discharging is determined by the current flowing through the current control N-type MOS transistors 3a to 3e.
Since 3e forms a current mirror circuit with the N-type transistor 3g, the current becomes the same as the current of the second current synthesizing circuit 10b.

Therefore, when the current I of the first current synthesizing circuit 10a 'changes, the time for charging and discharging the parasitic capacitance at each output of the CMOS inverters 4a to 4e changes, and as a result, the CMOS ring oscillator 1 Transmission frequency f
vc will change.

The oscillation frequency fvc of the CMOS ring oscillator 1 changes depending on the current I of the first current synthesis circuit 10a ', but also depends on the power supply voltage VDD. The reason for relying on the power supply voltage VDD is that the threshold voltage of the CMOS inverters 4a to 4e, that is, the threshold voltage depends on the power supply voltage VDD.
The threshold voltages of the OS inverters 4a to 4e increase as the power supply voltage VDD increases and decrease as the power supply voltage VDD decreases.

Therefore, when the current I for charging / discharging the parasitic capacitance of each output part of the CMOS inverters 4a to 4e is constant, the power supply voltage VDD is high until the threshold voltage of the CMOS inverters 4a to 4e is reached. The longer the power supply voltage VDD, the shorter the power supply voltage VDD. As a result, the transmission frequency fv of the CMOS ring oscillator 1
c is slower as the power supply voltage VDD is higher, and the power supply voltage VD
The lower the D, the faster.

[0011]

The conventional PLL circuit is
As described above, since a part of the current control oscillator is constituted by the ring oscillator 5, the CMOS ring oscillator 1 changes the frequency by the power supply voltage VDD.
There is a problem that the generated clock fluctuates due to the fluctuation of the power supply voltage VDD. SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has as its object to obtain a PLL circuit in which a generated clock has a small variation with respect to a variation in a power supply voltage VDD.

[0012]

A PLL circuit according to the present invention has a phase comparator, a loop filter, a voltage-current conversion circuit for converting a control voltage output from the phase filter into a current, and an output current thereof. A voltage-controlled oscillator having a current source and including a plurality of logic gate circuits electrically connected in a ring shape, the voltage-current conversion circuit having a power supply voltage as an element for determining an output current. A variable resistor that changes according to the fluctuation is used.

A PLL circuit according to the present invention includes a voltage dividing circuit in which a variable resistor divides a voltage between a power supply voltage and a ground voltage, a P-type MOS transistor having its output electrically connected to a gate electrode, and an electrical connection between the gate electrode and the ground voltage. A transmission gate formed of an N-type MOS transistor and a resistor, and the transmission gate and the resistor are connected in series or in parallel.

[0014] In the PLL circuit according to the present invention, the oscillation circuit is formed of a CMOS ring oscillator.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a diagram showing a P according to Embodiment 1 of the present invention.
FIG. 3 is a circuit diagram showing a voltage controlled oscillator of an LL circuit, in which 1 is a CMOS ring oscillator, 2a to 2e are P-type MOS transistors for current control, 3a to 3e are N-type MOS transistors for current control, 4a 4 to 4e are odd-numbered CMOS inverters connected to P-type MOS transistors 2a to 2e on the P-type MOS transistor side and N-type MOS transistors 3a to 3e on the N-type MOS transistor side, and 5 is a CMOS inverter 4a.
4e are ring oscillators connected in a ring, and 6 is a buffer gate for amplifying the output of the ring oscillator 5. The CMOS ring oscillator 1 includes a ring oscillator 5 and a buffer gate 6.

7 is a voltage-current conversion circuit, 10a is a first current synthesis circuit, 10b is a second current synthesis circuit, 8
Is an N-type MOS transistor having an output Vin from the loop circuit of the PLL circuit as a + side input, 3f is an N-type MOS transistor having an output of the differential amplifier 8 as a gate electrode and a − side input as a source electrode, 2f is an N-type MOS transistor. A P-type MOS transistor provided between the transistor 3f and the power supply voltage VDD;
g is a P-type MOS transistor forming a current mirror circuit with the P-type MOS transistor 2f, and 3g is a P-type MOS transistor.
N-type MOS transistor provided between transistor 2g and ground potential GND, 2h is a P-type MOS transistor,
3h is an N-type MOS transistor, 12a is a transmission gate including a P-type MOS transistor 2h and an N-type MOS transistor 3h, 9b, 9c and 9d are resistors, 13 is a resistor 9c and a resistor 9d, and includes a power supply voltage VDD and ground. This is a voltage dividing circuit that divides the voltage between the voltages GND by these components. The variable resistor 11a is composed of a transmission gate 12a, a resistor 9b, and a voltage dividing circuit 13. The gate electrodes of the P-type MOS transistor 2h and the N-type MOS transistor 3h constituting the transmission gate 12a are connected to the ground voltage GND and the output of the voltage dividing circuit 13, respectively.

The output potential of voltage dividing circuit 13 is equal to power supply voltage VD
Since the output potential increases as D increases, the N-type MOS
The impedance between the source and the drain of the transistor 3h decreases as the power supply voltage VDD increases. Accordingly, the resistance value of the variable resistor 11a, which is composed of a series combination of the transmission gate 12a and the resistor 9b, is also equal to the power supply voltage VDD.
The higher is the smaller.

The P-type MOS transistor 2g and the N-type MOS transistor 3g are the current control P-type MOS transistors 2g to 2g of the CMOS ring oscillator 1, respectively.
2e, and a current mirror circuit with the current control N-type MOS transistors 3a to 3e.

Next, the operation will be described. When the output Vin from the loop filter is input to the voltage-controlled oscillator, the differential amplifier 8 acts so that the positive input and the negative input have the same potential, so that the output Vin and the negative input have the same potential. The gate potential of the N-type MOS transistor 3f is controlled. The negative input of the differential amplifier 8 is a variable resistor 11a.
, The voltage Vin is applied to the variable resistor 11a. Therefore, the first current combining circuit 1
An output current I determined by the potential Vin and the variable resistor 11a flows through 0a. Therefore, due to the power supply voltage dependence of the resistance value of the variable resistor 11a, the current I of the current synthesis circuit 10a increases as the power supply voltage VDD increases, and the power supply voltage VDD
The lower is the smaller. On the other hand, the second current synthesis circuit 10
In b, the same current I flows because the P-type MOS transistor 2f and the P-type MOS transistor 2g form a current mirror circuit.

The CMOS ring oscillator 1 is a CMOS ring oscillator.
The transmission frequency fvc is determined by the time for charging and discharging the parasitic capacitance of each output unit of the inverters 4a to 4e.
The magnitude of the current required for charging is determined by the current flowing through the current control P-type MOS transistors 2a to 2e. The current control P-type MOS transistors 2a to 2e constitute a current mirror circuit with the P-type MOS transistor 2f. Therefore, the current becomes the same as the current of the first current synthesis circuit 10a and becomes the current I. The magnitude of the current required for discharging is determined by the current flowing through the current control N-type MOS transistors 3a to 3e.
Since e forms a current mirror circuit with the N-type MOS transistor 3g, it becomes the same as the current of the second current combining circuit 10b and becomes the current I.

As described above, the current I of the first current combining circuit 10a is determined by the positive input Vin of the differential amplifier 8 and the variable resistor 11a. Therefore, the current combining circuit 10a is controlled by the dependency of the resistance value of the variable resistor 11a on the power supply voltage VDD.
The current I increases as the power supply voltage VDD increases, and decreases as the power supply voltage VDD decreases.

The CMOS ring oscillator 1 has a C
The threshold voltage of the MOS inverters 4a to 4e increases as the power supply voltage VDD increases, and acts so as to increase the time to reach the threshold voltage of the CMOS inverters 4a to 4e. Since the power supply voltage VDD increases as the power supply voltage VDD increases, the charge / discharge time of the capacitance parasitic to each output unit of the CMOS inverters 4a to 4e is shortened. That is, the current I that charges and discharges the parasitic capacitance of each output unit of the CMOS inverters 4a to 4e changes. As a result, the transmission frequency fvc of the CMOS ring oscillator 1
Can be less dependent on the power supply voltage VDD.

As described above, according to the first embodiment, the PLL circuit is used as an element for determining the output current I of the voltage-current conversion circuit 5 constituting the voltage controlled oscillator 104.
The transmission gate 12a and the resistor 9b are connected in series, and the resistance value of the transmission gate 12a is configured using the variable resistor 11a which is controlled by the voltage dividing circuit 13 for dividing the voltage between the power supply voltage VDD and the ground voltage GND. The variable resistor 11a is connected to the CMOS inverter 4a to
In order to compensate for the change in frequency with respect to the change in the threshold voltage of the CMOS inverter 4e, the current I that charges and discharges the parasitic capacitance of each output of the CMOS inverters 4a to 4e acts so as to change. The effect of reducing the fluctuation due to the power supply voltage VDD is obtained.

Embodiment 2 FIG. FIG. 2 is a circuit diagram showing a voltage controlled oscillator included in a PLL circuit according to a second embodiment of the present invention.
A variable resistor provided between the side input and the ground voltage GND;
2j is a P-type MOS transistor, 3j is an N-type MOS transistor, 12b is a transmission gate composed of a P-type MOS transistor 2j and an N-type MOS transistor 3j, 9e is a resistor, and 13 is a voltage dividing circuit. Since the corresponding parts are shown, the description is omitted.
The transmission gate 12b and the resistor 9e are connected in parallel between the negative input of the differential amplifier 8 and the ground voltage GND, and the P-type MOS transistor 2j and the N-type MOS transistor 3j constituting the transmission gate 12b
Are respectively connected to the ground voltage GND and the voltage dividing circuit 1
3 is connected to the output.

Next, the operation will be described. Voltage dividing circuit 13
Is higher as the power supply voltage VDD is higher, the impedance between the source and the drain of the N-type transistor 3j is lower as the power supply voltage VDD is higher. Therefore, the resistance value of the variable resistor 11b, which is a parallel combined resistor of the transmission gate 12b and the resistor 9e, decreases as the power supply voltage VDD increases.

The current value I of the current synthesizing circuit 10a operates in the same manner as the circuit of FIG.
And the variable resistance 11b. Therefore, due to the power supply voltage dependence of the resistance value of the variable resistor 11b, the current I of the current combining circuit 10a increases as the power supply voltage VDD increases and decreases as the power supply voltage VDD decreases.

Since the CMOS ring oscillator 1 is the same as the circuit of FIG. 1, the threshold voltages of the CMOS inverters 4a to 4e increase as the power supply voltage VDD increases, and the time to reach the threshold voltages of the CMOS inverters 4a to 4e increases. However, as described above, the current I of the current combining circuit 10a also increases as the power supply voltage VDD increases, so that the CMOS inverters 4a to 4a
e serves to shorten the charge / discharge time of the parasitic capacitance of each output section. That is, the CMOS inverters 4a to 4e
The current I for charging / discharging the parasitic capacitance of each output section of the CMOS inverters 4a to 4e changes so as to compensate for the change in the frequency with respect to the change in the threshold voltage.
As a result, the transmission frequency f of the CMOS ring oscillator 1
It is possible to reduce the power supply voltage dependency of vc.

As described above, according to the second embodiment, in the PLL circuit, the transmission gate 12b and the resistor are used as elements for determining the output current I of the voltage-current conversion circuit 7 constituting the voltage controlled oscillator VCO. 9e is connected in parallel, and the variable resistance 11b configured to control the resistance value of the transmission gate 12b by the voltage dividing circuit 13 for dividing the voltage between the power supply voltage VDD and the ground voltage GND is used, so that the CMOS inverters 4a to 4e are used. Of the CMOS inverters 4a-4e so as to compensate for the change in the frequency with respect to the change in the threshold voltage of the CMOS inverter 4a-4e. The effect of reducing the fluctuation due to the voltage is obtained.

The voltage dividing circuit 1 of the first and second embodiments
Reference numeral 3 divides the power supply voltage VDD and the ground voltage GND by the resistors 9c and 9d. However, the present invention is not limited to this, and the same effect can be obtained by dividing the voltage by a capacitor or a diode.

In the first and second embodiments, each of the variable resistors 11a and 11b is constituted by the transmission gates 12a and 12b and the resistors 9b and 9e.
The present invention is not limited to b, and the same effect can be obtained by using an arbitrary N-type MOS transistor and a resistor.

[0031]

As described above, according to the present invention, a voltage-controlled oscillator converts a control voltage output from a loop filter into a current, and a current source corresponding to the output current. And a transmission circuit comprising a plurality of logic gate circuits connected in a ring, and the voltage-current conversion circuit uses a variable resistor that changes in accordance with a change in power supply voltage as an element that determines an output current. Because the variable resistor compensates for the change in the frequency with respect to the change in the threshold voltage of the logic gate circuit in which the variable resistor is connected in a ring shape, the current that charges and discharges the parasitic capacitance at each output of the logic gate circuit is changed. Therefore, there is an effect that the fluctuation of the clock generated by the transmission circuit due to the power supply voltage is reduced.

A PLL circuit according to the present invention has a voltage dividing circuit in which a variable resistor divides a voltage between a power supply voltage and a ground voltage, a P-type MOS transistor whose output is electrically connected to a gate electrode, and a gate electrode which is electrically connected to a ground voltage. A transmission gate composed of an N-type MOS transistor and a resistance, and the transmission gate and the resistance are connected in series or in parallel, so that the control means changes the control amount in accordance with the fluctuation of the power supply voltage. The variable resistor can be changed by the output from the voltage dividing circuit, and there is an effect that the fluctuation of the clock generated from the above-mentioned transmitting circuit due to the power supply voltage is reduced.

In the PLL circuit according to the present invention, the oscillation circuit is constituted by a CMOS ring oscillator. Therefore, the CM circuit compensates for a change in the frequency with respect to a change in the threshold voltage of the CMOS inverter included therein.
A variable resistor can be configured to change the current that charges and discharges the parasitic capacitance of each output of the OS inverter, and the current in the voltage-current conversion circuit changes the control amount according to the fluctuation of the power supply voltage. Since it acts as control means for causing the clock, the fluctuation of the clock generated by the above-mentioned oscillation circuit due to the power supply voltage is reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a voltage-controlled oscillator included in a PLL circuit according to Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram of a voltage controlled oscillator included in a PLL circuit according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a basic configuration of a conventional PLL circuit.

FIG. 4 is a circuit diagram of a voltage controlled oscillator included in a conventional PLL circuit.

[Explanation of symbols]

1 CMOS ring oscillator, 2a-2h P-type MO
S transistor, 3a-3h N-type MOS transistor, 4a-4e CMOS inverter, 5 ring oscillator, 6 buffer gate, 7 voltage-current conversion circuit, 8 differential amplifier, 9a-9e resistance, 10a, 10
a 'current combining circuit, 11a, 11b variable resistor, 12
a, 12b transmission gate, 13 voltage divider circuit, 101 phase comparator, 102 low-pass filter, 1
03 Amplifier, 104 Voltage controlled transmitter.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J043 AA02 AA07 BB01 DD02 DD07 DD14 DD15 LL01 5J106 AA04 CC03 CC21 CC38 CC41 DD05 JJ01 KK14 LL01

Claims (3)

[Claims] An electric circuit comprising a phase comparator, a loop filter, a voltage-current conversion circuit for converting a control voltage output from the loop filter into a current, and a current source corresponding to the output current. A voltage-controlled oscillator including an oscillation circuit composed of a plurality of logic gate circuits connected to each other, wherein the voltage-current conversion circuit changes according to a change in power supply voltage as an element for determining the output current. A PLL circuit using a variable resistor. 2. A voltage dividing circuit in which a variable resistor divides a voltage between a power supply voltage and a ground voltage, a P-type MOS transistor having an output electrically connected to a gate electrode, and an N-type MOS transistor having a gate electrode electrically connected to a ground voltage. The PLL circuit according to claim 1, further comprising a transmission gate and a resistor, wherein the transmission gate and the resistor are connected in series or in parallel. 3. The PLL circuit according to claim 1, wherein the transmission circuit comprises a CMOS ring oscillator.