JP2002246899A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit which is hardly affected by any incoming noise by setting a wide output frequency band without increasing the gain of a VCO in a simple circuit constitution whose circuit scale is smaller than a conventional manner. SOLUTION: This PLL circuit is provided with two PLL circuits, that is, a main PLL circuit part 2 for outputting a signal with a desired output frequency Fo from a first VCO 14 and a sub-PLL circuit part 3 for automatically adjusting a second control voltage VCOIN2 of a first control voltage VCOIN1 and the second control voltage VCOIN2 for controlling the oscillation frequency of a first VCO 14 of the main PLL circuit part 2 according to an output frequency Fo. The frequency-division rate of a second programmable counter 21 for setting the oscillation frequency of the sub-PLL circuit part 3 is set according to a frequency-division rate set by a first programmable counter 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit, and more particularly to a PLL circuit capable of setting an output frequency in a wide range.
It relates to an LL circuit.

[0002]

2. Description of the Related Art FIG. 7 is a schematic block diagram showing a configuration example of a conventional PLL circuit, and FIG. 8 shows an example of a control voltage-output frequency characteristic in the voltage controlled oscillator shown in FIG. FIG. In the PLL circuit 100 shown in FIG. 7, a programmable counter 101 serving as a frequency divider performs a PLL multiplication setting by changing a counter value according to a setting signal input from the outside. The phase of the input signal and the input signal of the predetermined reference frequency Fr input from the outside are compared by the phase comparator 102.

[0003] The comparison result of the phase comparator 102 is smoothed by a low-pass filter (hereinafter, referred to as LPF) 103, and then output as a voltage VCOIN to a voltage-controlled oscillator (hereinafter, referred to as VCO) 104. The VCO 104 outputs an output signal having a frequency Fo according to the input voltage VCOIN. Assuming that the frequency division ratio of the programmable counter 101 is 1 / N, the output frequency Fo can be represented by Fo = N × Fr. In order to obtain the signal of the target frequency,
The frequency characteristics of the VCO 104 become important.

[0004]

However, in recent years, there has been a tendency to require a PLL circuit capable of outputting a signal of a wide band frequency.
The characteristics of the VCO 104 as shown in FIG. 8 are required. VCO
The characteristics of the VCO 104 vary depending on power supply voltage, temperature, and process variations.
, That is, the change in the output frequency Fo with respect to the change in the control voltage VCOIN increases. However, when the gain of the VCO 104 increases, when the control voltage VCOIN changes due to external noise, the amount of fluctuation of the output frequency Fo increases, which causes a problem of causing an increase in jitter.

Therefore, as a method for lowering the gain of the VCO, there is a PLL circuit using an integrator as shown in FIG. 9, the integrator 105 controls the VCO so that the control voltage VCOIN from the LPF 103 becomes a predetermined voltage.
The control voltage VCOINa of 106 is adjusted. VCOIN
When the voltage of a reaches the upper limit or the lower limit, the control voltage VC
Adjustment is made so that a desired output frequency Fo is output at OIN. The control voltage-output frequency characteristic of the VCO 104 in FIG. 9 is as shown in FIG. 10, and the gain of the VCO 104 can be reduced.

A PLL circuit using such an integrator is disclosed in Japanese Patent Laid-Open No. Hei 10-21634.
However, the digital integrator disclosed in Japanese Patent Application Laid-Open No. 10-21634 has a problem that the circuit scale is large. In contrast, in the case of the analog integrator,
There is a problem that it is difficult to manage the offset and to guarantee the performance due to the fluctuation of the process and the temperature.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a simple circuit configuration with a smaller circuit size than the conventional one, and has a wide output frequency band without increasing the gain of the VCO. Accordingly, it is an object to obtain a PLL circuit which is hardly affected by external noise.

[0008]

A PLL circuit according to the present invention comprises: a first voltage controlled oscillator for generating and outputting a signal having a frequency corresponding to a first control voltage and a second control voltage;
A first frequency divider that divides and outputs an output signal of the voltage controlled oscillator, and compares the phase of the output signal of the first frequency divider with a signal input from the outside, and determines a voltage corresponding to the phase difference. , A first low-pass filter that integrates an output signal of the first phase comparator and outputs the integrated signal as a first control voltage to a first voltage-controlled oscillator, a first control voltage and a predetermined first control voltage. 2
A second method of generating and outputting a signal having a frequency corresponding to the control voltage
A voltage-controlled oscillator, a second frequency divider that divides an output signal of the second voltage-controlled oscillator and outputs the divided signal, and compares the phase of the output signal of the second frequency divider with a signal input from the outside. A second phase comparator that outputs a voltage corresponding to the phase difference, and an output signal of the second phase comparator, which is integrated into a first control signal as a second control voltage.
A second low-pass filter for outputting to each of the voltage-controlled oscillator and the second voltage-controlled oscillator, wherein the first frequency divider is configured to divide the frequency in accordance with a frequency division ratio setting signal input from outside to set the frequency division ratio. The frequency divider performs frequency division at a frequency ratio and outputs a signal corresponding to the set frequency division ratio to a second frequency divider.
The frequency division is performed at a frequency division ratio according to the frequency division ratio setting signal and the signal input from the first frequency divider.

Specifically, the second frequency divider performs frequency division at the same frequency division ratio as the first frequency divider according to the frequency division ratio setting signal within a predetermined frequency division ratio range. Outside the range of the predetermined frequency division ratio, frequency division is performed at a predetermined frequency division ratio according to a signal from the first frequency divider.

Further, the variable range of the frequency division number at which the frequency division is performed by the second frequency divider may be smaller than the variable range of the frequency division number at which the frequency division is performed by the first frequency divider. Good.

Further, the second low-pass filter includes a first low-pass filter.
The time constant may be made larger than that of the low-pass filter.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. FIG. 1 is a block diagram illustrating an example of a PLL circuit according to an embodiment of the present invention. In FIG. 1, a PLL circuit 1 includes a main PLL circuit unit 2 that outputs an output signal of an output frequency Fo that is multiplied with respect to an input signal of a predetermined reference frequency Fr, and a voltage-controlled oscillator (hereinafter, referred to as the main PLL circuit unit 2). , VCO) and a sub PLL circuit unit 3 for controlling the control voltage-output frequency characteristics.

The main PLL circuit section 2 includes a first programmable counter 11, a first phase comparator 12, a first low-pass filter (hereinafter, referred to as a first LPF) 13, and a first VCO 1.
4. A first programmable counter 11 forming a first frequency divider has a data signal D input from the outside.
The multiplication setting of the PLL is performed by changing the count value according to S.
The first phase comparator 12 compares the phases of the signal divided by 1 and the input signal of the reference frequency Fr input from the outside. The first phase comparator 12 outputs a voltage according to the comparison result. The output voltage is smoothed by the first LPF 13, and then output to the first VCO 14 as the first control voltage VCOIN1. The first VCO 14 receives the input first control voltage VCOIN1 and a second control voltage VCOIN2 described later.
And outputs an output signal having a frequency Fo corresponding to

On the other hand, the sub PLL circuit section 3 includes a second programmable counter 21, a second phase comparator 22, a second low-pass filter (hereinafter, referred to as a second LPF) 23, and a second V
It is composed of CO24. The second programmable counter 21 serving as a second frequency divider performs a PLL multiplication setting by changing a count value according to the data signal DS and a setting signal input from the first programmable counter 11. The phase of the signal divided by the programmable counter 21 and the input signal of the reference frequency Fr input from the outside are compared by the second phase comparator 22.

The second phase comparator 22 outputs a voltage corresponding to the comparison result, and the output voltage is smoothed by the second LPF 23 and then output to the first VCO 14 and the second VCO 24 as the second control voltage VCOIN2. You. Also,
The second VCO 24 has a predetermined reference voltage VREF as the first control voltage VCOIN1a, for example, 1 / the power supply voltage VCC.
2, and outputs an output signal having a frequency corresponding to the first control voltage VCOIN1a and the second control voltage VCOIN2 to the second programmable counter 21.

FIG. 2 is a circuit diagram showing an example of the first VCO 14. The first VCO 14 will be described with reference to FIG. 2, the first VCO 14 includes a ring oscillator unit 31 and a ring oscillator control unit 32 that controls a current supplied to the ring oscillator of the ring oscillator unit 31 to control a frequency of a signal output from the ring oscillator. Have been. FIG. 2 shows an example in which a plurality of inverter circuits are used as delay circuits constituting a ring oscillator.

The ring oscillator section 31 includes a ring oscillator 41 formed by a plurality of inverter circuits INV1 to INVn (n is an odd number of n> 1). Furthermore,
The ring oscillator section 31 includes a corresponding inverter circuit I
P-channel MOS transistors (hereinafter, referred to as PMOS) for controlling the current from the DC power supply for NV1 to INVn.
N-channel MOS transistors (hereinafter referred to as NMOS transistors) QN1 to QNn for controlling currents flowing to QP1 to QPn and ground GND.
It has.

On the other hand, the ring oscillator control section 32 includes a PMOS transistor 43 to 45 forming a current mirror circuit with each of the PMOS transistors QP1 to QPn, an NMOS transistor 46 forming a current mirror circuit with each of the NMOS transistors QN1 to QNn, A first VI converter 47 for flowing a current according to the first control voltage VCOIN1 and a second VI converter 48 for flowing a current according to the second control voltage VCOIN2 are provided. Furthermore, the first V-
The I converter 47 includes an NMOS transistor 51 and a resistor 52.
, And the second VI converter 48 includes an NM
It is formed by a series circuit of an OS transistor 53 and a resistor 54.

In the ring oscillator section 31, the ring oscillator 41 is formed by connecting inverters INV1 to INVn in a ring shape, and the output terminal of the inverter INVn forms the output terminal of the first VCO 14. The corresponding PMOS transistors QP1 to QPn are connected between the inverters INV1 to INVn and a power supply terminal to which the power supply voltage VCC is applied (hereinafter, referred to as a VCC terminal). Furthermore, corresponding NMOS transistors QN1 to QNn are connected between the inverters INV1 to INVn and the ground.

Next, in the ring oscillator control section 32, a series circuit of a PMOS transistor 43 and an NMOS transistor 46 is connected between the VCC terminal and the ground, and the gate of the PMOS transistor 43 is
It is connected to each gate of S transistors QP1 to QPn. The gate of the NMOS transistor 46 is connected to the drain of the NMOS transistor 46 and to each of the gates of the NMOS transistors QN1 to QNn. The NMOS transistor 46 and QN1 to QNn form a current mirror circuit.

Next, between the VCC terminal and the gate of the PMOS transistor 43, each of the PMOS transistors 44 and 45, whose gates and drains are connected, are connected in parallel, and the gate of the PMOS transistor 43 and the ground are connected to each other. Between the first VI converter 47 and the second VI
The converters 48 are respectively connected in parallel. Thus, each of the PMOS transistors 43 to 45, QP1 to QP
n forms a current mirror circuit.

The first VI converter 47 receives the first control voltage VCOI input to the gate of the NMOS transistor 51.
The second VI converter 48 supplies a bias current i1 according to the second control voltage VCOIN2 input to the gate of the NMOS transistor 53.
Flow 2 Also, the first VI converter 47 and the second VI
Converter 48 receives a correspondingly input first control voltage VCO
When bias currents i1 and i2 corresponding to IN1 and the second control voltage VCOIN2 are applied, currents corresponding to the respective currents flow to the PMOS transistors 43 to 45 and QP1 to QPn, respectively. Further, a current corresponding to the current flowing from the PMOS transistor 43 is supplied to each NMOS transistor 4.
6, QN1 to QNn.

The first output amplitude level having the power supply voltage width
The oscillation frequency of the VCO 14 is proportional to the amount of current supplied to the inverters INV1 to INVn forming a delay circuit. That is, a current of (i1 + i2) flows from the PMOS transistor 43 to the NMOS transistor 46, and in each of the inverters INV1 to INVn of the ring oscillator 41, the current becomes a charge / discharge current when the current operates, and determines the oscillation frequency of the ring oscillator 41.

Thus, the first control voltage VCOIN
By controlling the first and second control voltages VCOIN2, the current flowing through each of the inverters INV1 to INVn can be controlled, and the delay time of each of the inverters INV1 to INVn can be controlled. The frequency Fo of the signal can be changed. Since the second VCO 24 is the same as the first VCO 14 except that the first control voltage VCOIN1a is input to the gate of the NMOS transistor 51, the description thereof is omitted.

Here, the main PLL circuit section 2 has, for example, a reference frequency Fr of 1 MHz and an output frequency Fo of 50 to 32.
If it is required to output a 0 MHz signal, the first
As the programmable counter 11, a counter capable of dividing the frequency by 50 to 320 is used. The first VCO 14 has an output frequency F corresponding to two control voltages VCOIN1 and VCOIN2.
Generate and output the signal of o. When changing the output frequency Fo, the setting of the division ratio of the first programmable counter 11 is switched by the division ratio setting signal DS from the outside.

The main PLL circuit section 2 controls the first control voltage VCOIN1 for the first VCO 14 to perform PLL lock.
And the bias currents i1 and i2 of the first VCO 14 are changed by the second control voltage VCOIN2 from the sub PLL circuit unit 3, the operating speed of the ring oscillator 41 is changed, and the output frequency F of 50 to 320 MHz is changed.
The signal of o is output.

On the other hand, in the sub PLL circuit section 3, the second programmable counter 21
The variable range of the frequency division ratio is made narrower than 1. For example, the main PLL circuit unit 2 outputs the output frequency Fo as described above.
Is a specification that outputs an output signal of 50 to 320 MHz, the second programmable counter 21
The variable range of the frequency division number may be set to 128 to 256 by using a device capable of dividing the frequency by 256 and performing logic control or the like from the outside on the second programmable counter 21.

Here, the respective internal configurations of the first programmable counter 11 and the second programmable counter 21 as described above will be described. FIG. 3 is a diagram showing an example of each internal configuration of the first programmable counter 11 and the second programmable counter 21. In FIG. 3, the first
The programmable counter 11 includes a 9-bit counter 61
, Nine D-type flip-flops DF1 to DF9, and N
An OR circuit 62 is provided.

Each of the D-type flip-flops DF1 to DF9 is connected in series.
A predetermined clock signal clk from the outside is input to each of the clock signal input terminals of FIG.
The clock signal input terminals and the clock signal clk are omitted. The least significant bit of the 9-bit counter 61 (FIG. 3)
A signal from a non-inverting output terminal Q of a D-type flip-flop DF1 is input to a 1B input terminal serving as an input terminal. Further, in the 9-bit counter 61, 2B
Signals from the non-inverting output terminals Q of the corresponding D-type flip-flops DF2 to DF9 are input to the 9B input terminal forming the most significant bit (MSB in FIG. 3) input terminal from the input terminal. An external frequency division ratio setting signal DS for setting a frequency division ratio is input to a D input terminal of a D-type flip-flop DF9 that outputs a signal to the D-type flip-flop DF9.

As described above, the 9-bit counter 61
Based on the 9-bit data input from the type flip-flops DF1 to DF9, the signal input from the first VCO 14 is frequency-divided at a set frequency division ratio and output to the first phase comparator 12. On the other hand, the 9-bit counter 61
The non-inverting output terminals Q of the D-type flip-flops DF8 and DF9 connected corresponding to the upper 2 bits 8B and 9B input terminals of the NOR circuit 62 are connected corresponding to the two input terminals of the NOR circuit 62. . The signals output from the non-inverting output terminal Q of the D-type flip-flop DF9 and the output terminal of the NOR circuit 62 are output to the second programmable counter 21 as signals for setting the frequency division ratio.

Next, the second programmable counter 21
Is a 9-bit counter 71, nine D-type flip-flops DF11 to DF19, and seven OR circuits 72 to 78.
It is composed of Each D-type flip-flop DF11-
DF19 is connected in series, and a D-type flip-flop DF
A predetermined clock signal clk from the outside is input to each of the clock signal input terminals of 11 to DF19. However, in FIG. 3, the respective clock signal input terminals and the clock signal clk are omitted. 1B of 9-bit counter 71
A signal from the non-inverting output terminal Q of the D-type flip-flop DF11 is input to the input terminal.

Further, in the 9-bit counter 71, 2
The signals from the non-inverting output terminals Q of the corresponding D-type flip-flops DF12 to DF19 are input from the B input terminal to the 9B input terminal, respectively, and the D input terminal of the D-type flip-flop DF19 outputting the signal to the 9B input terminal. Receives a frequency division ratio setting signal DS for setting the frequency division ratio.

As described above, the 9-bit counter 71 sets the D
Based on the 9-bit data input from the flip-flops DF11 to DF19, the second VCO2
4 is divided by the set division ratio and output to the second phase comparator 22. On the other hand, among the D-type flip-flops DF18 and DF19 connected corresponding to the upper two bits of the 8B input terminal and the 9B input terminal of the 9-bit counter 71, the set terminal of the D-type flip-flop DF19 (hereinafter referred to as the S terminal). ) And a reset terminal (hereinafter, referred to as an R terminal) of the D-type flip-flop DF18, a signal from the non-inverting output terminal Q of the D-type flip-flop DF9 is input.

The R of the D-type flip-flop DF19
Terminal and the S terminal of the D-type flip-flop DF18,
Output signals of the NOR circuit 62 are input.
Further, the output signal from the NOR circuit 62 is
The signals from the non-inverting output terminal Q of the D-type flip-flop DF9 are input to the other input terminals of the OR circuits 72 to 78, respectively. The output signals of the OR circuits 72 to 78 are output from the corresponding D-type flip-flops DF11 to DF17.
Is input to each of the R terminals.

An operation example at the time of PLL lock in such a configuration will be described in detail. First, when the set output frequencies of the main PLL circuit section 2 and the sub PLL circuit section 3 are 128
The case where the frequency is higher than or equal to MHz and lower than 256 MHz will be described.
In this case, the first set by the division ratio setting signal DS
The frequency division ratios of the programmable counter 11 and the second programmable counter 21 exceed 1/256 and are equal to or less than 1/128. On the other hand, the second VCO of the sub PLL circuit unit 3
The first control voltage VCOIN1a input to the power supply 24 is fixed at a predetermined reference voltage VREF. Therefore, the sub-P
The LL circuit unit 3 adjusts the second control voltage VCOIN2 so that the second VCO 24 outputs a signal of a desired frequency. When the sub PLL circuit unit 3 performs PLL lock, the first
The operating characteristics of the CO 14 are determined.

FIG. 4 is a diagram showing an example of a control voltage-output frequency characteristic of the second VCO 24, and FIG.
FIG. 14 is a diagram illustrating an example of a control voltage-output frequency characteristic of No. 14; The main PLL circuit unit 2 operates to perform PLL lock in the same manner as the sub PLL circuit unit 3. In the first VCO 14, the second control voltage VCOIN2 is
And the first control voltage VCOIN1 is
Supplied from the LPF 13. The main PLL circuit unit 2
The first VCOIN1 is adjusted for L-lock, but the output frequency characteristic of the first VCO14 is the second VCO24.
Therefore, the first VCO 14 outputs a signal of a desired frequency when the first control voltage VCOIN1 is equal to the reference voltage VREF.

For example, in FIGS. 4 and 5, the second VC
When O24 is outputting a signal of a frequency of 128 MHz, the characteristic of the first VCO 14 is a. The output frequency from the second VCO 24 is set to 180 MHz in accordance with the frequency division ratio setting signal DS input to the second programmable counter 21.
, The second control voltage VCOIN2 increases, and the characteristics of the first VCO 14 shift to b. Such behavior is
The automatic adjustment is performed not only when the setting of the second programmable counter 21 is switched but also for each variation due to the process and the temperature. The time constant of the second LPF 23 of the sub PLL circuit unit 3 is equal to the time constant of the first PLL circuit unit 2.
It must be larger than the LPF 13 so as to be less susceptible to external noise.

Next, when the output frequency Fo is not less than 50 MHz and less than 128 MHz,
The operation in the case where the frequency is equal to or lower than Hz will be described. Output frequency F
When o is 50 MHz or more and less than 128 MHz, the 9-bit counter 61 of the first programmable counter 11
9 input from D-type flip-flops DF1 to DF9
The upper two bits of the bit data are all "00".

Therefore, the non-inverting output terminal Q of the D-type flip-flop DF9 becomes low level and the NOR circuit 6
2 becomes high level, and the OR gates 72 to 72
All the output terminals 78 are at the high level. For this reason, the 9-bit counter 71 of the second programmable counter 21 has D-type flip-flops DF11 to DF1.
9-bit data from 9 to “01000000” is input, and the second programmable counter 21 sets the division ratio to 1/128 which is the maximum value of the division variable range. As described above, the sub PLL circuit unit 3 has an output frequency of 128M
Hz to adjust the second control voltage VCOIN2,
The second VCO circuit 24 has a frequency of 128 MHz as shown in FIG.
The signal of the frequency of is output.

At this time, the main PLL circuit unit 2 adjusts the first control voltage VCOIN1 so that the output frequency is in the range of 50 to 128 MHz with the characteristic a in FIG.
A signal having a desired output frequency Fo is output.

On the other hand, when the output frequency Fo is equal to or greater than 256 MHz and equal to or less than 320 MHz, the 9-bit counter 61 of the first programmable counter 11 stores the upper one bit of the 9-bit data input from the D-type flip-flops DF1 to DF9 as " 1 ". Therefore, the non-inverting output terminal of the D-type flip-flop DF9 goes high, and all the output terminals of the OR circuits 72 to 78 go high. From this, the 9-bit counter 71 of the second programmable counter 21 stores the 9 bits of “10000000” from the D-type flip-flops DF11 to DF19.
The bit data is input, and the second programmable counter 21 sets the frequency division ratio to 1/256 which is the minimum value of the frequency division variable range.

As described above, the sub PLL circuit unit 3 controls the second control voltage VCOI so that the output frequency becomes 256 MHz.
N2 is adjusted, and the second VCO circuit 24 outputs a signal having a frequency of 256 MHz as shown in FIG. At this time,
The main PLL circuit unit 2 adjusts the first control voltage VCOIN1 so that the output frequency is in the range of 256 to 320 MHz with the characteristic of c in FIG.
The signal of is output. From the above, the main PLL circuit unit 2
The control voltage-output frequency characteristic of the first VCO 14 in FIG.

As described above, the PL in the present embodiment is
The L circuit outputs a signal of a desired output frequency Fo to the first VCO 1
4 and a first PLL circuit 2 for controlling the oscillation frequency of the first VCO 14 in the main PLL circuit unit 2.
Two PLLs such as a sub PLL circuit unit 3 that automatically adjusts the second control voltage VCOIN2 in accordance with the output frequency Fo among the control voltage VCOIN1 and the second control voltage VCOIN2.
Circuit, and the frequency division ratio of the second programmable counter 21 for setting the oscillation frequency of the sub PLL circuit unit 3.
The setting is made in accordance with the frequency division ratio set in the first programmable counter 11. Accordingly, a wide output frequency band can be obtained without increasing the gain of the VCO with a simple circuit configuration having a smaller circuit size than in the related art, and the fluctuation amount of the output frequency caused by noise or the like can be reduced. Therefore, an increase in jitter can be prevented.

In the description of the above embodiment, the case where each of the first programmable counter 11 and the second programmable counter 21 uses a 9-bit counter has been described as an example. This is an example taking the case of 320 MHz as an example,
A counter having a number of bits corresponding to the output frequency range may be used in the first programmable counter 11 and the second programmable counter 21 and a D-type flip-flop corresponding to the number of bits may be provided.

[0045]

As is apparent from the above description, according to the PLL circuit of the present invention, the first voltage controlled oscillator for generating and outputting a signal having a frequency corresponding to the first control voltage and the second control voltage is provided. The first frequency divider that divides the output signal and outputs the divided signal performs the frequency division at the frequency division ratio according to the frequency division ratio setting signal input from the outside in order to set the frequency division ratio. A signal corresponding to the frequency division ratio is output to the second frequency divider, and an output signal of the second voltage controlled oscillator that generates and outputs a signal having a frequency corresponding to the predetermined first control voltage and the predetermined second control voltage is divided. The second frequency divider which outputs the frequency is divided at a frequency division ratio according to the frequency division ratio setting signal and the signal input from the first frequency divider.
Accordingly, a wide output frequency band can be obtained without increasing the gain of the VCO with a simple circuit configuration having a smaller circuit size than in the related art, and the fluctuation amount of the output frequency caused by noise or the like can be reduced. Therefore, an increase in jitter can be prevented.

Specifically, the second frequency divider performs frequency division at the same frequency division ratio as that of the first frequency divider according to the frequency division ratio setting signal within a predetermined frequency division ratio range. Outside the range of the frequency division ratio, frequency division is performed at a predetermined frequency division ratio according to a signal from the first frequency divider. From this, when the second frequency divider performs frequency division within the range of the predetermined frequency division ratio, the first voltage controlled oscillator
At the same first control voltage as the predetermined first control voltage applied to the second voltage control generator, it is possible to output a signal having an output frequency corresponding to the input second control voltage, A wide output frequency band can be obtained without increasing the gain.

Also, the variable range of the frequency division number at which the frequency division is performed by the second frequency divider is smaller than the variable range of the frequency division number at which the frequency division is performed by the first frequency divider. The voltage-controlled oscillator can output a signal having an output frequency corresponding to the first control voltage outside the range of the frequency division number at which the frequency division is performed by the second frequency divider. Since an output frequency characteristic corresponding to the voltage can be obtained, a wide output frequency band can be obtained without increasing the gain of the voltage controlled oscillator.

Further, since the time constant of the second low-pass filter is made larger than that of the first low-pass filter, the second low-pass filter can be made less susceptible to external noise, so that the reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a first VCO 14 of FIG.

FIG. 3 is a diagram showing an example of each internal configuration of a first programmable counter 11 and a second programmable counter 21 of FIG.

FIG. 4 is a diagram showing an example of a control voltage-output frequency characteristic in a second VCO 24 of FIG.

FIG. 5 is a diagram showing an example of a control voltage-output frequency characteristic in the first VCO 14 of FIG.

6 is a diagram illustrating an example of a control voltage-output frequency characteristic in the PLL circuit of FIG. 1;

FIG. 7 is a schematic block diagram showing a configuration example of a conventional PLL circuit.

8 is a diagram illustrating an example of a control voltage-output frequency characteristic of the VCO illustrated in FIG. 7;

FIG. 9 is a schematic block diagram showing another configuration example of a conventional PLL circuit.

FIG. 10 is a diagram illustrating an example of a control voltage-output frequency characteristic of the VCO illustrated in FIG. 9;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 PLL circuit 2 Main PLL circuit part 3 Sub PLL circuit part 11 1st programmable counter 12 1st phase comparator 13 1st LPF 14 1st VCO 21 2nd programmable counter 22 2nd phase comparator 23 2nd LPF 24 2nd VCO 31 Ring oscillator Unit 32 ring oscillator control unit 41 ring oscillator

Claims (4)

[Claims] A first voltage-controlled oscillator for generating and outputting a signal having a frequency corresponding to the first control voltage and the second control voltage; and a frequency-divided output signal of the first voltage-controlled oscillator for output. A 1-frequency divider; a first phase comparator that compares a phase of an output signal of the first frequency divider with a signal input from the outside and outputs a voltage corresponding to the phase difference; A first low-pass filter for integrating the output signal of the comparator and outputting the integrated signal as a first control voltage to the first voltage-controlled oscillator; and generating a signal having a frequency corresponding to predetermined first and second control voltages. A second voltage controlled oscillator for outputting, an output signal of the second voltage controlled oscillator, a second frequency divider for dividing the output signal, and an output signal of the second frequency divider and an externally input signal. A second phase comparator for comparing phases and outputting a voltage corresponding to the phase difference; A second low-pass filter that integrates an output signal of the comparator and outputs the integrated signal as a second control voltage to the first voltage-controlled oscillator and the second voltage-controlled oscillator, respectively. In order to set the frequency, the frequency division is performed at the frequency division ratio according to the frequency division ratio setting signal input from the outside, and the signal according to the frequency division ratio set is output to the second frequency divider. The frequency divider includes the frequency division ratio setting signal and the first
A PLL circuit, which performs frequency division at a frequency division ratio according to a signal input from a frequency divider. 2. The second frequency divider performs frequency division at the same frequency division ratio as the first frequency divider in accordance with the frequency division ratio setting signal within a predetermined frequency division ratio range. 2. The PLL circuit according to claim 1, wherein the frequency division is performed at a predetermined frequency division ratio according to a signal from the first frequency divider outside the range of the frequency ratio. 3. The variable range of the frequency division number at which the frequency division is performed by the second frequency divider is smaller than the variable range of the frequency division number at which the frequency division is performed by the first frequency divider. P according to claim 2
LL circuit. 4. The PLL circuit according to claim 1, wherein the second low-pass filter has a larger time constant than the first low-pass filter.