JPH05175834A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To obtain the phase locked loop circuit provided with an optimum synchronizing characteristic, stationary characteristic and transient response characteristic for each number of frequency division even when the number of frequency division is changed and a loop gain is changed. CONSTITUTION:A low-pass filter 20 equipped with a selecting circuit to select plural resistance values and plural capacitors according to a frequency dividing number select signal is connected to a phase comparator 10 to detect phase difference between an input signal 1 and a frequency divider signal 5, plural voltage controlled oscillators 30 are connected to this low-pass filter, a selecting circuit to select one of these voltage controlled oscillators is connected, and a frequency divider 40 is connected to the output of the selecting circuit. A frequency dividing number select signal S is impressed to the selecting circuit of the low-pass filter 20, and the filter characteristics are changed by selecting the plural resistors and capacitors. The frequency dividing number select signal S is impressed to the selecting circuit of the voltage controlled oscillator 30, and a frequency change amount is changed corresponding to the controlled voltage change amount of the voltage controlled oscillators 30 by selecting one of them.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and more particularly to detecting a phase difference so that a signal obtained by dividing an oscillator oscillation signal by a frequency divider matches the frequency or phase of an input signal. Then, the present invention relates to a phase locked loop circuit which is controlled by feedback.

[0002]

2. Description of the Related Art FIG. 10 shows a conventional phase locked loop (Phase
It is a figure which shows a Locked Loop (following PLL) circuit. As shown in the figure, the input signal 1, and the divided signal 5 obtained by dividing the output signal 4 by the divider 40 are the phase comparator 10
, The phase comparator 10 is connected to the low-pass filter 20, and the low-pass filter 20 is connected to the voltage controlled oscillator (Voltage Co
ntrolled oscillator (hereinafter referred to as VCO circuit) 30. Further, the frequency division number selection signal S is given to the frequency divider 40.

The phase comparator 10 generates an error signal 2 corresponding to the phase difference between the input signal 1 and the divided signal 5. PLL
Is synchronized, the phase of the divided signal 5 divided by the divider 40 matches the phase of the input signal 1, and the voltage of the error signal 2 of the phase comparator 40 does not change.

The low-pass filter 20 removes a high frequency component and noise contained in the output error signal 2 of the phase comparator 10 and determines the phase characteristic and the synchronization characteristic of the PLL based on the amplitude and the phase characteristic. The VCO circuit 30 is an oscillator whose oscillation frequency is determined by the VCO control signal 3 output from the low-pass filter 20, and the output signal 4 is divided by passing through the frequency divider 40 to be output from the phase comparator 10. It becomes one input signal and forms a PLL feedback loop.

FIG. 11 is a timing chart when the frequency divider 40 of the PLL circuit shown in FIG. 10 divides by two. The phase difference between the input signal 1 and the divided signal 5 is detected by the phase comparator 10, and the error signal 2 having a pulse width corresponding to the phase difference is output. Divided signal 5 as shown in period a
Is delayed in phase with respect to the input signal 1, the error signal 2
Becomes a pulse in the positive direction in which the oscillation frequency of the VCO circuit 30 is increased by the VCO control signal 3. On the contrary, when the frequency-divided signal 5 leads the input signal 1 in phase as shown in the period b, the error signal 2 is a negative pulse in which the oscillation frequency of the VCO circuit 30 is lowered by the VCO control signal 3. Become. When the phases of the divided signal 5 and the input signal 1 shown in the period c are the same, the error signal 2 has a constant value.

The high frequency component and noise of the error signal 2 are filtered by the low pass filter 20 and the VCO control signal 3 is output. The VCO circuit 30 uses the VCO control signal 3
It oscillates at a frequency according to the potential of. In the case of FIG. 11, it oscillates at twice the frequency of the input signal 1. The output signal 4 having the frequency is divided by 2 in the frequency divider 40 to obtain a divided signal 5.

The PLL circuit repeats the phase delay period a and the phase advance period b of FIG. 11 to input signal 1 and divided signal 5.
The feedback works so that are in the same phase, and tries to stabilize the system.

FIG. 12 is a diagram showing a circuit of the low-pass filter 20. R1 and R2 are resistors and C is a capacitance, which represents a lag lead filter. In FIG. 10, when the frequency division number of the frequency divider 40 is N, the natural frequency ω _n is ((K / N) / (R1 · C + R2 ·
C)) ^1/2 , the damping ratio ζ is (1/2) ・ ω _n・ (R2 ・ C
+ N / K).

FIG. 13 is a diagram showing a VCO circuit 30, which is composed of an n-channel type MOS transistor and a p-channel type MOS transistor. V
An oscillation frequency proportional to the potential of the VCO control signal 3 is obtained by the ring oscillator including the inverter chain 31 whose current amount is controlled by the CO control signal 3. VC
The amount of change in the oscillation frequency per unit potential of the O control signal 3 is one factor that determines the loop gain.

When the number of inverter stages in the inverter chain 31 is large, the oscillation frequency is low because the signal propagation delay time due to the inverter chain is large, and when the number of stages is small, the oscillation frequency is high because the signal propagation delay time due to the inverter chain is small.

When designing a PLL circuit, the resistance values of the resistors R1 and R2, the capacitance value of the capacitance C, and the loop gain K are determined so that the synchronization characteristic, the steady characteristic, and the transient response characteristic are optimized. , Fix it.

[0012]

Since the conventional PLL circuit is configured as described above, it is necessary to determine the resistance value, the capacitance value, and the loop gain that provide the optimum characteristics for the specific frequency division number. However, there is a problem that optimum characteristics cannot be obtained for other frequency division numbers.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a PLL circuit which can obtain optimum characteristics for all frequency division numbers.

[0014]

A PLL circuit according to the present invention is a PLL circuit that detects a phase difference and controls by feedback so that the frequency or phase of an oscillator always matches the frequency or phase of an input signal. A selection circuit having a VCO circuit in which a plurality of inverter circuits whose current amount is controlled by the output signal of the low-pass filter are connected in a ring shape so that the number of connection stages of the inverters forming the ring can be selected according to the frequency division number selection signal. It is equipped with.

Further, in the PLL circuit according to the present invention, the output signal of the low-pass filter is used in the PLL circuit which detects the phase and controls by feedback so that the frequency or phase of the oscillator always matches the frequency or phase of the input signal. A plurality of ring oscillators in which a plurality of inverter circuits whose current amounts are controlled by a ring are connected to each other are provided with a VCO circuit connected to a selection circuit, and the transistor size of the inverter circuits of the plurality of ring oscillators is a ring. Different from each oscillator, one of the oscillation signals of the plurality of ring oscillators can be selected according to the frequency division number selection signal.

Further, the PLL circuit according to the present invention is a low-pass filter in a PLL circuit which detects a phase difference and controls by feedback so that the frequency or phase of the oscillator always matches the frequency division number or phase of the input signal. Is provided with a selection circuit so that the resistance value and the capacitance value can be selected according to the frequency division number selection signal.

Further, the PLL circuit according to the present invention is a PLL circuit which detects a phase difference and controls by feedback so that the frequency or phase of the oscillator always matches the frequency or phase of the input signal. A low-pass filter having a selection circuit capable of selecting a resistance value and a capacitance value according to the above, and a plurality of inverter circuits whose current amount is controlled by the output signal of the low-pass filter are connected in a ring shape, The number of connection stages of the inverters forming the ring can be selected according to the number selection signal.

Further, the PLL circuit according to the present invention is a PLL circuit which detects a phase difference and controls by feedback so that the frequency or phase of the oscillator always matches the frequency or phase of the input signal. A low-pass filter having a selection circuit so that the resistance value and the capacitance value can be selected according to the above, and a plurality of inverter circuits whose current amount is controlled by the output signal of the low-pass filter are connected in a ring shape. A plurality of ring oscillators are provided with a VCO circuit connected to a selection circuit, and transistor sizes of inverter circuits of the plurality of ring oscillators are different for each ring oscillator. It is configured so that one can be selected from the oscillation signals.

[0019]

In the present invention, the VCO circuit connects a plurality of inverter circuits whose current amount is controlled by the output signal of the low-pass filter in a ring shape, and connects the number of inverters forming the ring in accordance with the frequency division number selection signal. Since the selection circuit capable of selecting is selected, the number of stages of the ring forming the VCO circuit can be selected for each frequency division number, and an optimum loop gain can be obtained for each frequency division number.

In the present invention, in the VCO circuit, a plurality of inverter circuits whose current amount is controlled by the output signal of the low-pass filter are connected in a ring shape, and the transistor sizes of the inverter circuits of the plurality of ring oscillators are ring-shaped. Different for each oscillator, since a plurality of ring oscillators are connected to the selection circuit, one can be selected from the oscillation signals of the plurality of ring oscillators according to the frequency division number selection signal for each frequency division number. Optimal loop gain is obtained for each.

In the present invention, since the low-pass filter is provided with the selection circuit so that the resistance value and the capacitance value can be selected according to the frequency division number selection signal, the optimum filter characteristic can be obtained for each frequency division number.

According to the present invention, there is provided a low-pass filter having a selection circuit capable of selecting a resistance value and a capacitance value according to a frequency division number selection signal, and a plurality of current amounts are controlled by an output signal of the low-pass filter. Inverter circuits are connected in a ring shape, and a VCO circuit having a selection circuit is provided so that the number of connection stages of the inverters forming the ring can be selected according to the frequency division number selection signal. Loop gain and filter characteristics are obtained.

According to the present invention, the low-pass filter is provided with the selection circuit so that the resistance value and the capacitance value can be selected according to the frequency division number selection signal, and the current amount is controlled by the output signal of the low-pass filter. A plurality of ring oscillators in which a plurality of inverter circuits are connected in a ring shape are connected to a selection circuit, and the transistor size of the inverter circuits of the plurality of ring oscillators is different for each ring oscillator. According to the above, since the VCO circuit capable of selecting one from the oscillation signals of the plurality of ring oscillators is provided, optimum loop gain and filter characteristics can be obtained for each frequency division number.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a PLL circuit according to a first embodiment of the present invention, in which the frequency division number selection signal is 1
One PLL circuit. As shown in the figure, the reference input signal 1 and the frequency-divided signal 5 divided by the frequency divider 40 are input to the phase comparator 10. The error signal 2 from the phase comparator 10 is given to the low pass filter 20, and the VCO control signal 3 is given from the low pass filter 20 to the VCO circuit 30. Further, the VCO circuit 30 is supplied with the frequency division number selection signal S. The output signal 4 of the VCO circuit 30 is applied to the frequency divider 40 controlled by the frequency division number selection signal S, and the frequency division signal 5 is obtained. It serves as one input signal of the phase comparator 10 and forms a feedback loop.

FIG. 2 is a circuit diagram showing an embodiment of the VCO circuit 30 in the block diagram shown in FIG. 1 which is the first embodiment. The VCO circuit 30 used in this embodiment is
An n-channel MOS transistor whose gate is supplied with a VCO control signal 3 and whose source is grounded, and a p-channel MOS transistor whose gate and drain are connected to the drain of the n-channel MOS transistor and whose source is connected to a power supply. , Delay blocks 31 and 32,
And it is comprised by the selection circuit 30S.

The delay blocks 31 and 32 have the same structure, and the p-channel type MOS transistor having the gate connected to the drain of the n-channel type MOS transistor and the source connected to the power source and the VCO control signal 3 are gated. And an n-channel MOS transistor whose source is grounded, and in which the p-channel MOS transistor and the n-channel MOS transistor sharing the signal and the drain of which are commonly provided between the two transistors are connected in series. A plurality of unit delay circuits connected to are connected in series. The output signal of the delay block 31 is the input signal of the delay block 32.

The selection circuit 30S is composed of a CMOS transmission gate and an inverter for generating an inverted signal of the frequency division number selection signal S. The input signal of the CMOS transmission gate is the delay block 31.
And 32 outputs are provided. The gate of the CMOS transmission gate is supplied with the frequency division number selection signal S or its inverted signal. The output signal of the CMOS transmission gate is the output signal 4 of the VCO circuit 30.
And is the input signal of the delay block 31.

Next, the operation of the PLL circuit of FIG. 1 will be described. The phase comparator 10 generates an error signal 2 corresponding to the phase difference between the input signal 1 and the divided signal 5. When the PLL is in the synchronous state, the phase of the divided signal 5 divided by the divider 40 matches the phase of the input signal 1, and the voltage of the error signal 2 of the phase comparator 40 does not change.

The low-pass filter 20 allows the phase comparator 10 to operate.
The potential of the VCO control signal 3 from which the high frequency component and noise included in the error signal 2 output from the unit delay circuit are controlled to control the amount of current flowing through the unit delay circuit, thereby controlling the delay time in the unit delay circuit. Frequency division selection signal S is "1" in binary display
If, the CM to which the output of the delay block 32 is connected
The OS transmission gate is turned on and the output signal is selected to be the output signal 4 of the VCO circuit 30 and the input signal of the delay block 31. In this case, VC
The ring oscillator constituting the O circuit is a circuit including the delay blocks 31 and 32.

On the contrary, when the frequency division number selection signal S is "0" in the binary display, the CMOS transmission gate to which the output of the delay block 31 is connected is turned on to select the output signal and the VCO circuit 30. Output signal 4 and input signal of the delay block 31. In this case, the ring oscillator forming the VCO circuit is a circuit including the delay block 31.

The number of unit delay circuits included in the ring is smaller in the case where the delay block forming the VCO circuit is only the delay block 31 than in the case where it is formed by the delay block 31 and the delay block 32. A high frequency is obtained for a potential of 3. Therefore VC
The frequency change amount with respect to the change amount of the potential of the O control signal 3 is large, and the gain in the VCO circuit is high.

When the frequency division number selection signal S is "1" in binary display, the frequency division number is M, the gain of the VCO circuit portion is K _M , and the frequency division number selection signal S is "0" in binary display. If the frequency division number is L,
Let the gain of the VCO circuit portion be K _L and L> M. VC
The gain in the O circuit portion becomes K _M / K _L times smaller in the case of M division than in the case of L division. On the other hand, the change in gain due to the frequency divider becomes L / M times, and the gain becomes large.
Therefore, the change of the gain in the entire system becomes L / M times, and the gain becomes large. Therefore, the gain of the whole system is (K _M · L)
/ (K _L / M) times. By setting K _M / K _L = L / M, the same characteristics can be obtained without changing the gain in the entire system.

Next, another example of the first embodiment will be described. FIG. 3 is a block diagram showing a PLL circuit according to another example of the first embodiment, and this example is a PLL circuit having N frequency division number selection signals. As shown in the figure, the reference input signal 1 and the frequency-divided signal 5 divided by the frequency divider 40 are input to the phase comparator 10. The error signal 2 from the phase comparator 10 is given to the low pass filter 20, and the VCO control signal 3 is given from the low pass filter 20 to the VCO circuit 30. Further, the VCO circuit 30 has a frequency division number selection signal S
1 to SN are given. Output signal 4 of VCO circuit 30
Is applied to the frequency divider 40 controlled by the frequency division number selection signals S1 to SN, and the frequency division signal 5 is obtained. The divided signal 5 becomes one input signal of the phase comparator 10 and forms a feedback loop.

FIG. 4 shows another example of the first embodiment shown in FIG.
4 is a circuit diagram showing an embodiment of a VCO circuit 30 in the block diagram shown in FIG. The VCO circuit 30 includes N delay blocks shown in FIG. 2, and has a configuration in which the selection signals S1 to SN are connected to the selection circuits 31S to 3NS, respectively.

Next, the operation of the PLL circuit of FIG. 3 will be described. The phase comparator 10 generates an error signal 2 corresponding to the phase difference between the input signal 1 and the divided signal 5. When the PLL is in the synchronous state, the phase of the divided signal 5 divided by the divider 40 matches the phase of the input signal 1, and the voltage of the error signal 2 of the phase comparator 40 does not change.

The low-pass filter 20 allows the phase comparator 10 to operate.
The amount of current flowing through the unit delay circuit is controlled by the potential of the VCO control signal 3 from which the high frequency component and the noise included in the output error signal 2 are removed, and the delay time in the unit delay circuit is controlled. Only one of the frequency division number selection signals S1 to SN becomes "1" in the binary display, the CMOS transmission gate to which the output of the delay block is connected is turned on, the output signal is selected, and the VCO circuit 30 It becomes the output signal 4 and the input signal of the delay block 31.
In this way, the gain / decrease of the frequency divider causes an increase / decrease in the gain, and therefore, the number of stages of the unit delay circuit included in the ring oscillator configuring the VCO circuit is selected by the frequency division number selection signal. Increase or decrease the gain to maintain the overall gain of the system.

Next, a second embodiment of the present invention will be described. The block configuration of the PLL circuit of the second embodiment is the first
3 is the same as FIG. 3 showing another example of the above embodiment, but the VCO circuit 30 used therein is different. FIG. 5 shows a circuit diagram of a VCO circuit used in the second embodiment. VCO circuit 30
Includes N VCO circuits 30 of FIG. 13 shown in the conventional example. Each VCO circuit has a different transistor size (gate width and gate length) constituting the VCO circuit. VC
The output signals of the O circuits 301 to 30N are the selection circuits 3 respectively.
Input to a CMOS transmission gate of 1S to 3NS. The frequency division number selection signals S1 to SN and the inversion signal are applied to the gates of the CMOS transmission gates of the selection circuits 31S to 3NS. The outputs of the CMOS transmission gates of the selection circuits 31S to 3NS are connected to the same node, and the oscillation signal of the selected VCO circuit is VCO.
It becomes the output signal 4 of the circuit 30.

Since the sizes of the transistors forming the VCO circuits 301 to 30N are different, the amount of current flowing through the unit delay circuit is different, the delay time per unit delay circuit is also different, and the oscillation depending on the change amount of the VCO control signal for each ring oscillator. The frequencies are different. Therefore, the VCO circuits 301 to 30N
Have different gains. In this way, the increase and decrease of the gain by the divider due to the increase and decrease of the number of divisions,
By selecting one from a plurality of VCO circuits having different gains, the gain of the VCO circuit portion is increased or decreased to maintain the gain of the entire system.

Next, a third embodiment of the present invention will be described. FIG. 6 is a diagram showing a PLL circuit according to the third embodiment of the present invention. In this embodiment, the frequency division number selection signal is N PLL circuits. As shown in the figure, the reference input signal 1 and the frequency-divided signal 5 divided by the frequency divider 40 are input to the phase comparator 10. The error signal 2 from the phase comparator 10 is given to the low pass filter 20 controlled by the frequency division number selection signals S1 to SN, and the low pass filter 20 outputs VC.
The O control signal 3 is given to the VCO circuit 30. The output signal 4 of the VCO circuit 30 is supplied to the frequency divider 40 controlled by the frequency division number selection signals S1 to SN, and the frequency division signal 5 is obtained. The divided signal 5 becomes one input signal of the phase comparator 10 and forms a feedback loop.

FIG. 7 is a circuit diagram showing a low pass filter used in the third embodiment. It is composed of resistors R1 and R2 each having a selection circuit 50 and a capacitor C. As the resistor R1, resistors R11 to R1N having different resistance values to which the error signal 2 is applied are arranged in parallel, and the selection circuit 5 is provided.
It is connected to 0. The resistor R2 is connected to the output signal from the selection circuit of the capacitance C and has different resistances R21 to R21.
2N are arranged in parallel and connected to the selection circuit 50. As for the capacitor C, capacitors C11 to C1N whose one ends are grounded are arranged in parallel and connected to the selection circuit 50. The frequency division number a priori signals S1 to SN are applied to the selection circuit 50.

Next, a PL including the low-pass filter 20 shown in FIG.
The operation of the L circuit will be described. Frequency division selection signal S1
If only one of the SNs is a binary display of "1" or negative logic, it becomes "0" and the frequency division number is determined.
The selection circuit 50 added to the resistors R1 and R2 and the capacitance C of the low-pass filter 20 also has the frequency division number selection signals S1 to S1.
One of N inputs controlled by SN and input to the selection circuit 50 is selected and output.

When the frequency division number changes, the loop gain of the entire system changes, and the synchronization characteristics related to the time required for locking, the stationary characteristics related to the stationary phase error and the noise band, and the transient response characteristics related to the natural frequency and the attenuation rate are obtained. Change. However, the increase or decrease of the loop gain due to the change of the frequency division number is selected and changed by the frequency division number selection signal to change the resistance value and the capacitance value of the reduction filter, thereby preventing the deterioration of the previous period characteristics. For example, the natural frequency ω _N is (K
/ N / (R1 · C + R2 · C) ^1/2 , and even if N increases and natural frequency ω _N decreases, small resistances R1 and R2
If the capacitance C and the capacitance C are selected, the decrease in the value of the natural frequency ω _N can be suppressed.

FIG. 8 is a circuit diagram showing a low-pass filter used in another example of the third embodiment. Selection circuit 5
It is composed of resistors R1 and R2 having 0 and a capacitor C. The resistor R1 is a resistor R1 to which the error signal 2 is given.
N resistors are arranged in series up to a resistor R1N starting from 1 and connected to the selection circuit 50. As for the resistor R2, N resistors are arranged in series up to the resistor R2N starting from the resistor R21 connected to the output signal from the selection circuit of the capacitance C, and connected to the selection circuit 50. As for the capacitor C, capacitors C11 to C1N, one of which is grounded, are arranged in parallel and connected to the selection circuit 50. The frequency dividing number selection signals S1 to SN are applied to the selection circuit 50.

In the low-pass filter shown in FIG. 8, resistors are connected in series, and the sum of the resistance values from the input terminal of the resistor R1 or R2 to the node whose output is selected by the selection circuit is the resistance of the resistor R1 or R2. It becomes a value. As a result, the increase / decrease of the loop gain due to the change of the frequency division number is selected by the frequency division number selection signal to change the resistance value and the capacitance value of the low pass filter to prevent the deterioration of the synchronization characteristic, the steady characteristic and the transient response characteristic. ..

Next, a fourth embodiment of the present invention will be described. FIG. 9 is a block diagram showing a PLL circuit according to the fourth embodiment of the present invention, and this embodiment is a PLL circuit having N frequency division number selection signals. As shown in the figure, the phase comparator 10 is supplied with the reference input signal 1 and the divided signal 5 divided by the divided signal 40. The error signal 2 from the phase comparator 10 is given to the low-pass filter 20 controlled by the frequency division number selection signals S1 to SN, and the previous period low frequency filter 20 controls VC controlled by the frequency division number selection signals S1 to SN.
The VCO control signal 3 is applied to the O circuit 30. The output signal 4 of the VCO circuit 30 is applied to the frequency divider 40 controlled by the frequency division number selection signals S1 to SN, and the frequency division signal 5 is obtained. The divided signal 5 becomes one input signal of the phase comparator 10 and forms a feedback loop.

Next, the operation of the fourth embodiment will be described. An embodiment of the low-pass filter shown in FIG. 9 is shown in FIG.
An embodiment of the CO circuit is shown in FIG. The phase comparator 10 has an error signal 2 corresponding to the phase difference between the input signal 1 and the divided signal 5.
To occur. When the PLL is in the synchronous state, the phase of the divided signal 5 divided by the divider 40 matches the phase of the input signal 1, and the voltage of the error signal 2 of the phase comparator 40 does not change.

Only one of the frequency division number selection signals S1 to SN becomes "1" in the binary display, and the frequency division number is determined by the frequency divider 40. Further, in the reduction filter 20, the resistance R
1 and R2, and the selection circuit 50 added to the capacitor C is also controlled by the frequency division number selection signals S1 to SN and selects and outputs one of the N inputs input to the selection circuit 50. The low pass filter removes high frequency components and noise contained in the output error signal 2 of the phase comparator 10.

The amount of current flowing through the unit delay circuit is controlled by the potential of the VCO control signal 3 which is the output signal of the low pass filter, and the delay time in the unit delay circuit is controlled. Only one of the frequency division number selection signals S1 to SN becomes "1" in the binary display, and the output of the delay block is connected to C.
Of the MOS transmission gates, the CMOS transmission gate to which the frequency division number selection signal which has become "1" is applied is turned on to select the delay block output signal to become the output signal 4 of the VCO circuit 30 and the delay block 31. It becomes the input signal of.

In this way, the performance of the low-pass filter is changed by selecting the resistance value and the capacitance value of the low-pass filter by the frequency-division-number selection signal as the gain and the gain of the frequency divider increase and decrease with the increase and decrease of the frequency division number. In addition, by increasing or decreasing the gain of the VCO circuit portion by selecting the number of stages of the unit delay circuit included in the ring oscillator configuring the VCO circuit with the frequency division number selection signal, the synchronization characteristics, the steady characteristics and Prevents deterioration of transient response characteristics.

Next, a fifth embodiment of the present invention will be described. FIG. 9 is a block diagram showing a PLL circuit according to a fifth embodiment of the present invention, and this embodiment is a PLL circuit having N frequency division number selection signals. As shown in the figure, the reference input signal 1 and the frequency-divided signal 5 divided by the frequency divider 40 are input to the phase comparator 10. The error signal 2 from the phase comparator 10 is applied to the low-pass filter 20 controlled by the frequency division number selection signals S1 to SN, and the low frequency filter 20 controls the VCO controlled by the frequency division number selection signals S1 to SN.
The VCO control signal 3 is provided to the circuit 30. The output signal 4 of the VCO circuit 30 is supplied to the frequency divider 40 controlled by the frequency division number selection signals S1 to SN, and the frequency division signal 5 is obtained. The divided signal 5 becomes one input signal of the phase comparator 10 and forms a feedback loop.

Next, the operation of the fifth embodiment will be described. An embodiment of the low-pass filter shown in FIG. 9 is shown in FIG.
An example of the CO circuit is shown in FIG. The phase comparator 10 has an error signal 2 corresponding to the phase difference between the input signal 1 and the divided signal 5.
To occur. When the PLL is in the synchronous state, the phase of the divided signal 5 divided by the divider 40 matches the phase of the input signal 1, and the voltage of the error signal 2 of the phase comparator 40 does not change.

Only one of the frequency division number selection signals S1 to SN becomes "1" in the binary display, and the frequency division number is determined by the frequency divider 40. Further, in the low pass filter 20, the resistance R
1 and R2, the selection circuit 50 added to the capacitor C also selects and outputs one of the N inputs input to the selection circuit 50 according to the frequency division number selection signals S1 to SN. The low pass filter removes high frequency components and noise contained in the output error signal 2 of the phase comparator 10.

Since the n-channel type MOS transistor and the p-channel type MOS transistor constituting the VCO circuits 301 to 30N have different transistor sizes, the VCO circuits 301 to 30N have different gains. The gain of the VCO circuit portion is increased or decreased by selecting one from a plurality of VCO circuits having different gains according to the frequency division number selection signals S1 to SN.

In this way, the performance of the low-pass filter is changed by selecting the resistance value and the capacitance value of the low-pass filter by the frequency-division selection signal as much as the gain increase / decrease by the frequency divider is caused by the increase / decrease of the frequency division number. In addition, by selecting one of a plurality of VCO circuits having different gains by the frequency division number selection signal to increase or decrease the gain of the VCO circuit portion, the synchronous characteristic, steady state characteristic and transient response of the entire system Prevents deterioration of characteristics.

[0055]

As described above, according to the present invention, the VC
In a PLL circuit that detects a phase difference and controls by feedback so that the frequency or phase of the O circuit always matches the frequency or phase of the input signal,
A frequency divider that divides the oscillation signal of the O circuit according to a frequency division number selection signal, and a phase comparator that outputs a signal corresponding to the phase difference between the two signals of the frequency divider output signal and the input signal,
A low-pass filter that removes high-frequency components and noise of the output signal of the phase comparator; and a VCO circuit whose oscillation frequency changes according to the output signal of the low-pass filter.
In the CO circuit, a plurality of inverter circuits whose current amount is controlled by the output signal of the low-pass filter are connected in a ring shape, and the number of connecting stages of the inverters forming the ring is selected according to the frequency division number selection signal. Since the selection circuit is provided in, the deterioration of the performance due to the increase or decrease of the loop gain due to the change of the frequency division number can be controlled, and the optimum loop gain can be obtained for each frequency division number.

Further, according to the present invention, in the PLL circuit which detects the phase difference and controls by feedback so that the frequency or phase of the VCO circuit always matches the frequency or phase of the input signal, the oscillation of the VCO circuit. A frequency divider that divides a signal according to a frequency division number selection signal, a phase comparator that outputs a signal corresponding to a phase difference between two signals of the frequency divider output signal and the input signal, and the phase comparator A low-pass filter for removing high-frequency components and noise of the output signal, and a VCO circuit whose oscillation frequency changes according to the output signal of the low-pass filter, wherein the VCO circuit uses the output signal of the low-pass filter for the amount of current. A plurality of ring oscillators in which a plurality of inverter circuits controlled in a ring shape are connected to a selection circuit, Since the transistor size of the inverter circuit is different for each ring oscillator and the selection circuit is provided so as to select one of the oscillation signals of the plurality of ring oscillators according to the frequency division number selection signal, the frequency division number changes. There is an effect that it is possible to obtain the optimum loop gain for each frequency division number by controlling the deterioration of the performance due to the increase or decrease of the loop gain.

Further, according to the present invention, in the PLL circuit which detects the phase difference and controls by feedback so that the frequency or phase of the VCO circuit always matches the frequency or phase of the input signal, the oscillation of the VCO circuit. A frequency divider that divides a signal according to a frequency division number selection signal, a phase comparator that outputs a signal corresponding to a phase difference between two signals of the frequency divider output signal and the input signal, and the phase comparator A low-pass filter that removes high-frequency components and noise of the output signal, and a VCO circuit whose oscillation frequency changes according to the output signal of the low-pass filter. Also, since the selection circuit is provided so that the capacitance value is selected, the deterioration of the performance due to the increase or decrease of the loop gain due to the change of the frequency division number is suppressed, and the frequency division number is reduced. There is an effect that it is possible to respectively obtain the optimum filter characteristic.

Further, according to the present invention, in the PLL circuit which detects the phase difference and controls by feedback so that the frequency or phase of the VCO circuit always matches the frequency or phase of the input signal, the oscillation of the VCO circuit. A frequency divider that divides a signal according to a frequency division number selection signal, a phase comparator that outputs a signal corresponding to a phase difference between two signals of the frequency divider output signal and the input signal, and the phase comparator A low-pass filter for removing high-frequency components and noise of the output signal, and a VCO circuit whose oscillation frequency changes according to the output signal of the low-pass filter, wherein the low-pass filter has a resistance value according to the frequency division number selection signal. And a capacitance value are selected, and the VCO circuit has a ring-shaped plurality of inverter circuits whose current amount is controlled by the output signal of the low-pass filter. Since the selection circuit is provided so that the number of connecting stages of the inverters forming the ring is selected according to the frequency division number selection signal, the deterioration of the performance due to the increase or decrease of the loop gain due to the change of the frequency division number is prevented. There is an effect that it is possible to suppress and obtain the optimum filter characteristic and loop gain for each frequency division number.

Further, according to the present invention, in the PLL circuit which detects the phase difference and controls by feedback so that the frequency or phase of the VCO circuit always matches the frequency or phase of the input signal, the oscillation of the VCO circuit. A frequency divider that divides the signal according to the frequency division number selection signal,
A phase comparator that outputs a signal corresponding to a phase difference between the output signal of the frequency divider and the two signals of the input signal; a low-pass filter that removes high-frequency components and noise of the output signal of the phase comparator; A VCO circuit whose oscillation frequency changes according to an output signal of the low-pass filter, wherein the low-pass filter has a resistance value and a capacitance value selected according to the frequency division number selection signal, and the VCO circuit includes the low-pass filter. A plurality of ring oscillators in which a plurality of inverter circuits whose current amount is controlled by the output signal of the filter are connected in a ring shape are connected to a selection circuit, and the transistor size of the inverter circuits of the plurality of ring oscillators is the ring oscillator. The selection circuit is different from each other, and the selection circuit is provided so that one of the oscillation signals of the plurality of ring oscillators is selected according to the frequency division number selection signal. Suppressing degradation in performance due to the increase or decrease in loop gain caused by the frequency division number is changed, there is an effect that it is possible for each frequency division number optimal filter characteristic and loop gain, respectively.

[Brief description of drawings]

FIG. 1 is a block diagram of a PLL circuit showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a VCO circuit according to the first embodiment of the present invention.

FIG. 3 is a PLL showing another example of the first embodiment of the present invention.
It is a block diagram of a circuit.

FIG. 4 shows a VC in another example of the first embodiment of the present invention.
It is a circuit diagram of an O circuit.

FIG. 5 is a circuit diagram of a VCO circuit according to a second embodiment of the present invention.

FIG. 6 is a block diagram of a PLL circuit showing a third embodiment of the present invention.

FIG. 7 is a circuit diagram of a low pass filter according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram of a low pass filter in another example of the third embodiment of the present invention.

FIG. 9 is a block diagram of a PLL circuit showing fourth and fifth embodiments of the present invention.

FIG. 10 is a block diagram showing a conventional PLL circuit.

FIG. 11 is a timing chart showing the operation of a conventional PLL circuit.

FIG. 12 is a circuit diagram of a low-pass filter in a conventional PLL circuit.

FIG. 13 is a circuit diagram of a VCO circuit in a conventional PLL circuit.

[Explanation of symbols]

 1 Input signal 2 Error signal 3 VCO control signal 4 Output signal 5 Divided signal 10 Phase comparator 20 Low-pass filter 30, 301 to 301N VCO circuit 40 Divider S, S1 to SN selection signal 31 to 3N Voltage control type inverter Chain 30S to 3NS, 50 Selection circuit R1, R11 to R1N, R2, R21 to R2N Resistance C, C11 to C1N Capacitance

Claims (5)

[Claims] 1. A phase-locked loop circuit that detects a phase difference and controls by feedback so that the frequency or phase of the oscillator always matches the frequency or phase of the input signal. A frequency divider that divides according to a number selection signal, a phase comparator that outputs a signal corresponding to a phase difference between two signals of the output signal of the frequency divider and the input signal, and an output signal of the phase comparator A low-pass filter for removing high-frequency components and noise, and an oscillator whose oscillation frequency changes according to the output signal of the low-pass filter, wherein the oscillator is connected in a ring shape, and the output signal of the low-pass filter causes a current to flow. A plurality of inverter circuits whose amounts are controlled; and a selection circuit for selecting the number of connecting stages of the inverters forming the ring according to the frequency division number selection signal. Phase locked loop circuit, characterized in that it. 2. A phase locked loop circuit that detects a phase difference and controls by feedback so that the frequency or phase of the oscillator always matches the frequency or phase of the input signal, and divides the oscillation signal of the oscillator. A frequency divider that divides according to a number selection signal, a phase comparator that outputs a signal corresponding to a phase difference between two signals of the output signal of the frequency divider and the input signal, and an output signal of the phase comparator A low-pass filter for removing high-frequency components and noise, and an oscillator whose oscillation frequency changes according to the output signal of the low-pass filter, wherein the oscillators have mutually different transistor sizes of the inverter circuit, A plurality of ring oscillators in which a plurality of inverter circuits whose current amount is controlled by an output signal are connected in a ring shape; Phase locked loop circuit, characterized in that force and a selection circuit for selecting and outputting one from the oscillation signal of the plurality of ring oscillators in accordance connected the frequency division number selection signal. 3. A phase-locked loop circuit that detects a phase difference and controls by feedback so that the frequency or phase of the oscillator always matches the frequency or phase of the input signal, and divides the oscillation signal of the oscillator. A frequency divider that divides according to a number selection signal, a phase comparator that outputs a signal corresponding to a phase difference between two signals of the output signal of the frequency divider and the input signal, and an output signal of the phase comparator A low-pass filter that removes high-frequency components and noise, and an oscillator whose oscillation frequency changes according to the output signal of the low-pass filter, wherein the low-pass filter selects a resistance value and a capacitance value according to the frequency selection signal. A phase locked loop circuit comprising a selection circuit. 4. The phase-locked loop circuit according to claim 1, wherein the low pass filter includes a selection circuit that selects a resistance value and a capacitance value according to the frequency division number selection signal. Phase locked loop circuit. 5. The phase-locked loop circuit according to claim 2, wherein the low-pass filter includes a selection circuit that selects a resistance value and a capacitance value according to the frequency division number selection signal. Phase locked loop circuit.