JP3350345B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to improvement of a power supply system of a semiconductor device, and more particularly to stabilization of a power supply voltage of a semiconductor device using a PLL circuit.

[0002]

2. Description of the Related Art An example of a conventional semiconductor device is schematically shown in FIG. The logic circuit formed on the semiconductor substrate is supplied with a power supply voltage VDD and a ground voltage GND from an external power supply (not shown). In a logic circuit of an LSI operating at high speed, a delay between signals inside becomes a problem. The delay time of a logic circuit varies depending on the manufacturing process, operating temperature, and power supply voltage.

For this reason, when designing a circuit, it is necessary to provide a sufficient circuit design margin so that the circuit operates stably even if the delay time varies. For example, in the case of a digital circuit, the design is confirmed by a logic simulation, but in the logic simulation, an IV (inverter), a NAND, or the like that constitutes the logic circuit is checked.
The simulation is performed by preliminarily registering the characteristics of the delay time under typical conditions of the basic circuit in a library and applying a margin coefficient K to a variation in the delay time due to a variation in a manufacturing process, an operating temperature, and a power supply voltage. .

[0004]

Therefore, in order to design a semiconductor device that operates under all conditions, it is necessary to design a circuit that operates even when a margin coefficient K is multiplied. However, since the margin coefficient K is usually large, even when operating under typical conditions, it may happen that the simulation does not operate when the margin coefficient is changed, and it may be necessary to repeat circuit correction and simulation many times.

The drain current ID in the saturation region of the MOS LSI is proportional to W / L * (VDD−Vth) ² as the channel width W and the channel length L of the transistor. Power supply voltage VDD
Becomes smaller, the channel length L, the power supply voltage VDD, and the threshold V
The variation of the delay time with respect to the variation of th becomes large. For this reason, the margin coefficient K must be increased as the device is miniaturized, which causes a problem that the circuit design is difficult and the development period becomes longer.

[0006] Such a problem is particularly remarkable when a logic circuit is designed to operate with a low-voltage power supply in order to miniaturize the logic circuit and reduce power consumption, because the design margin is small. .

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device having less variation in delay time.

Another object of the present invention is to provide a semiconductor device capable of accurately setting a power supply voltage to be supplied to a logic circuit and sufficiently suppressing a variation from a set value.

[0009]

In order to achieve the above object, a semiconductor device according to the present invention comprises a logic circuit which operates on a first power supply voltage, and a clock for generating a clock signal having a frequency corresponding to the second power supply voltage. A generator, a phase comparator for comparing the phase of the clock signal with a reference clock signal,
A low-pass filter section for smoothing an input signal by an integration circuit; a charge pump section for charging and discharging the low-pass filter section based on a result of the phase comparison; and a first power supply having a level corresponding to an output of the low-pass filter section A power supply voltage generator for generating a voltage, wherein the first and second power supply voltages for operating the logic circuit and the clock generator are shared and supplied from the power supply voltage generator. It is characterized by having done.

[0010] The semiconductor device of the present invention further comprises a logic circuit operable by the first power supply voltage, a clock generator for generating a clock signal having a frequency corresponding to the second power supply voltage,
A phase comparison unit for comparing the phase of the clock signal with a reference clock signal; a low-pass filter unit for smoothing an input signal by an integration circuit; and a charge pump unit for charging and discharging the low-pass filter unit based on the result of the phase comparison A buffer amplifier that determines the level of the second power supply voltage according to the DC output of the low-pass filter unit; and a power supply voltage generator that determines the level of the first power supply voltage according to the level of the second power supply voltage And a setting unit that sets the first and second power supply voltages according to the frequency of the reference clock signal.

As described above, the internal power supply voltage generator and the PLL (phase locked loop) are provided in the semiconductor device having the logic circuit, and the voltage / frequency converter (2) corresponding to the VCO (voltage controlled oscillator) of the PLL is provided. The internal power supply voltage generated by the internal power supply voltage generation unit is controlled by the control input voltage of (2). The control input voltage of the voltage / frequency conversion means (2) is controlled by a PLL so that the output clock of the voltage / frequency conversion means (2) is fixed at a certain frequency (reference frequency). By using the internal power supply voltage formed by this control input voltage, a low power supply voltage can be obtained and maintained accurately. Since the internal power supply voltage formed here always keeps the delay time of the voltage / frequency conversion means (2) representing the delay time of the LSI at a constant value, the delay time of the logic circuit is also kept at a constant value. You. For this reason, it is possible to obtain an LSI having a small design margin and no delay time variation.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. In the semiconductor device, an internal power supply voltage generator 1 for supplying circuit power and an internal power supply voltage generator 1 are provided.
A logic circuit 6 that performs required logic processing using the voltage generated by the internal power supply voltage generator as a circuit power supply, a voltage control oscillator 2 that uses the voltage generated by the internal power supply voltage generator 1 as a control input, and a voltage control oscillator 2
Phase comparator (or frequency comparator) 3 for comparing the output clock of the phase comparator with an externally input reference clock, a charge pump 4 for performing charge / discharge based on the comparison output data of the phase comparator 3, and a charge pump 4 Integrate the output of
A low-pass filter (LPF) 5 for supplying a smoothed output to a control input terminal of the internal power supply voltage generator 1.

FIG. 2 shows an example of the configuration of the internal power supply voltage generator 1. In this example, the internal power supply voltage generator 1 includes an operational amplifier 1a and a PMOS transistor 1b. The output of the low-pass filter unit 5 is the operational amplifier 1
When supplied to the inverting input terminal of a, a voltage proportional to the output of the low-pass filter section 5 is applied to the gate of the PMOS transistor 1b, and the conduction of the PMOS transistor is controlled. As a result, an internal power supply voltage V0 obtained by lowering the voltage from the power supply VDD is obtained. In the example of FIG. 2, the output of the low-pass filter unit 5 and the voltage of the internal power supply voltage generation unit 1 are set to PL
When the L loop is configured, they are made equal.

FIG. 3 shows an example of the configuration of the voltage controlled oscillator 2. In this example, the voltage controlled oscillator 2 is constituted by a ring oscillator in which an odd number of inverters are connected in a ring. By controlling the voltage applied to both ends of each inverter by the internal power supply voltage, the amplitude of the output signal is controlled, and oscillation occurs at a frequency corresponding to the applied voltage.

FIG. 4 shows an example of the configuration of the phase comparator 3. The phase comparison unit 3 includes, for example, two D flip-flops 3a and 3b and three NAND gates 3c to 3e, 1
It can be configured by three inverters 3f. The operation of this circuit is shown in FIG. The phase comparator 3 outputs an UP signal when the output clock signal fV of the voltage controlled oscillator 2 lags behind the reference clock signal fref. When the output clock signal fV of the voltage controlled oscillator 2 advances with respect to the reference clock signal fref, a DN signal is output.

FIG. 6 shows an example of the configuration of the charge pump section 4. The charge pump unit 4 includes a PMOS transistor 4a, a charging current source 4b,
c, a discharge current source 4d. When the UP signal is "L", the PMOS transistor 4a conducts, and the current source 4b charges the integration circuit of the low-pass filter unit 5 in the next stage. When the DN signal is "H", the NMOS transistor 4c conducts, and the integration circuit of the low-pass filter unit 5 at the next stage is discharged by the suction current source 4d.

FIG. 7 shows an example of the configuration of the low-pass filter unit 5. A low-pass filter is configured by an integrating circuit including the resistors R1 and R2 and the capacitor C1. The output of the low-pass filter unit 5 is supplied to the internal power supply voltage generator 1.

FIG. 8 shows an example of the configuration of a circuit connected after the logic circuit 6. Since the logic circuit 6 is driven by a low internal power supply voltage, the output level is low. The level shift unit 21 is used to obtain a standardized output signal of the LSI with this low output. The I / O buffer 22 is driven by the output of the level shift unit 21. I / O
An external circuit (device) (not shown) and a logic circuit are connected via the buffer 22. The logic circuit 6 uses the internal power supply to
The / O buffer unit 22 operates with an external interface power supply, and the level shift unit 21 operates with an internal power supply and an external interface power supply.

Normally, since the output signal of the LSI is specified, it is necessary to supply a power supply voltage satisfying the specification to the output buffer. However, when the output signal of the internal logic circuit is directly connected to the output buffer, the logic circuit becomes “H”.
Since the output signal voltage of the level is lower than the power supply voltage of the output buffer, the PMOS transistor (not shown) of the output buffer is not completely turned off when the output of the logic circuit is at "H" level. For this reason, a DC current flows through the output buffer. To prevent this, a level shift circuit is inserted.

FIG. 9 shows an example of a circuit configuration of the level shift section 21. The level shift circuit is composed of two cross-connected PMOS transistors and two NMOS transistors respectively connected to these two transistors. External interface (IF) power is applied to both ends of this circuit. Then, the complementary output of the logic circuit 6 is applied to the gates of the two NMOS transistors, and a shift output is obtained at the drain of the PMOS transistor.

Next, the operation of the above circuit will be described. The phase comparator 3 compares the output clock fV of the voltage controlled oscillator 2 with the reference clock fref. If the phase of the output clock fV of the voltage controlled oscillator 2 is earlier, the DN signal corresponds to the phase difference, and the UP signal corresponds to the phase difference. It outputs with a pulse of the specified width. The charge pump unit 4 performs charging or discharging according to the pulse width of the UP signal or the DN signal, and converts the phase difference signal into an analog voltage. The low-pass filter unit 5 converts the capacitor charge charged or discharged by the charge pump unit 4 into a DC voltage. In addition, harmonic noise components are removed. The internal power supply voltage generator 1 generates a voltage proportional to the output voltage of the low-pass filter 5 as an internal power supply voltage. The internal power supply voltage is supplied to the logic circuit 6 and the voltage controlled oscillator 2 as described above.

If the phase of the output clock fV of the voltage controlled oscillator 2 is later than that of the reference clock fref, the UP signal having the phase difference is output from the phase comparator 3 and the charge pump 4 pulses the UP signal. A minute charge is made. Therefore, the voltage of the output of the LPF 5 slightly increases. The output voltage of the operational amplifier 1 in FIG. 2 decreases because the input voltage on the inverting input terminal side increases. As a result, a large amount of output current of the PMOS transistor 1b flows, and the output voltage (internal power supply voltage) of the internal power supply voltage generation unit increases. For this reason, the frequency of the output clock fv of the voltage controlled oscillator 2 increases, and the reference clock fref
It operates so as to be in the same phase as. Therefore, the internal power supply voltage generator 1, voltage control oscillator 2, phase comparator 3, charge pump 4, and low-pass filter 5 operate as a PLL loop.

Conversely, the output clock f of the voltage controlled oscillator 2
If V is ahead of the reference clock fref in phase, the output voltage of the internal power supply voltage generator 1 decreases. For this reason, the frequency of the output clock fV of the voltage controlled oscillator 2 becomes lower, and it operates so that it has the same phase as the reference clock fref.

As described above, the output voltage of the internal power supply voltage generator 1 is settled by the phase locked loop to a voltage at which the output clock fV of the voltage controlled oscillator 2 has the same frequency as the reference clock fref. The phase-locked loop operates so that the reference frequency and the frequency of the voltage controlled oscillator 2 are the same even if there is a variation in the process and the temperature. Therefore, the output voltage of the internal power supply voltage generator 1 is always the voltage controlled oscillator. Section 2 settles down to a voltage operating at the reference frequency. Therefore, it is possible to set the internal power supply voltage that is accurately maintained by the reference frequency fref. The reference frequency fref can be used by dividing or multiplying the LSI system clock. The power supply VDD supplied from the outside does not affect the output voltage of the internal power supply voltage generator 1 as long as the voltage is sufficiently higher than the internal power supply in which the circuit of FIG. Therefore, by using this stable power supply voltage as the internal power supply voltage of the LSI, a logic circuit having no delay variation can be configured.

The internal power supply voltage generator shown in FIG. 2 operates so that the input voltage and the output voltage of the internal power supply voltage generator become the same. Any device capable of generating a voltage whose frequency is equal to the reference frequency may be used. For example, an output voltage that is inversely proportional to the input voltage may be output. In this case, by switching the input of the phase comparison unit 3, it operates as a PLL.

In the example shown in FIG. 1, the output of the voltage controlled oscillator 2 is connected to the phase comparator 3, but the clock is divided by 1 / N between the voltage controlled oscillator 2 and the phase comparator 3. May be configured to have a frequency divider inserted therein.

The power supply for the external interface and the power supply for the operational amplifier 1a and the PMOS transistor 1b shown in FIG. 8 may be different from each other. Further, the power supply may be shared.

FIG. 10 shows a second embodiment of the present invention. In the figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and description of such parts is omitted.

The difference between this configuration and the configuration of FIG. 1 is that the output of the internal power supply voltage generator 1 and the power supply of the voltage controlled oscillator 2 are separated. Also, the buffer amplifier 7 drives the voltage controlled oscillator 2 with the output voltage of the low-pass filter 5.
Is added. Therefore, the internal power supply voltage V2
Is easily set to a value proportional to the output voltage V1 of the low-pass filter section 5. Of course, it is possible to set V1 = V2.

FIG. 11 shows an example of the buffer amplifier 7. The buffer amplifier can be configured by an operational amplifier.

FIG. 12 shows that the internal power supply voltage generator 1
An example in which the DC converter 13 is used is shown.
In the same figure, parts corresponding to those in FIG.
The description of such portions is omitted.

The frequency comparing unit 11 includes, for example, a counter for counting the frequency of the output signal fV of the voltage controlled oscillator 2, a counter for counting the frequency of the reference clock fref, and a comparator for comparing the values of both counters. Become. It should be noted that a configuration of a frequency / phase comparator for comparing the frequency and the phase can be adopted. It is also possible to use a phase comparator. The control clock generator 12 determines two clocks G1 and G2 based on the frequency comparison result.
Is controlled.

FIG. 13 shows a configuration example of the DC-DC converter 13. In this example, the DC-DC converter includes a switching power supply including a chopper circuit and a low-pass filter circuit. Clocks G1 and G2 are applied to the gates of the two MOS transistors M1 and M2, respectively, which constitute the chopper circuit. The transistors M1 and M2 are turned on and off alternately to form a trapezoidal waveform from the input DC power supply. This is passed through a secondary low-pass filter formed by the inductor Lf and the capacitor Cf to be converted into a DC voltage with a small ripple. For example, a DC voltage of 3.3 V or 1.5 V can be obtained from a power supply of DC 6 V. The voltage value is adjusted by the ratio of the on-time of the transistors M1 and M2. The overall operation of maintaining the power supply voltage is the same as in FIG.

In the embodiment, FIGS. 1, 10 and 1
The internal voltage generating circuit 2 is a step-down circuit for lowering the external voltage, but may be a booster circuit for raising the internal voltage higher than the external voltage.

Also, in the case of a product such as an MPU (microprocessor) that reduces the clock frequency in the standby mode to reduce the current consumption in the standby mode, the present invention is adopted to provide a reference in the standby mode. , The internal voltage can be further reduced as compared with the normal mode, and the current consumption can be reduced.

[0036]

As described above, since the power supply voltage of the logic circuit is stabilized by using the semiconductor device of the present invention, the delay variation in the logic circuit is reduced.
For this reason, the design period can be significantly reduced. Also,
In the past, the power supply voltage was kept constant externally,
By changing the reference frequency, it is possible to reduce the internal voltage by a fine setting to the limit where the logic circuit always operates, and it is possible to reduce the current consumption IDD of the logic circuit.

For example, conventionally, an LSI is designed to operate even if the power supply voltage fluctuates. However, considering the margin (operation guarantee) against the fluctuation of the power supply voltage, the LSI is used at the lowest voltage at which the LSI operates. I could not do it. However, according to the present invention, it has become possible to always use the lowest voltage at which the LSI operates. For this reason, a plastic package can be used even in a conventional product in which an inexpensive plastic package cannot be used due to low heat radiation. Also, LSIs for mobile devices that operate on batteries
In this case, it is possible to extend the life of the battery of the portable device.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of an internal power supply voltage generator 1 of FIG.

FIG. 3 is a circuit diagram showing an example in which the voltage controlled oscillator 2 of FIG. 1 is configured by a ring oscillator.

FIG. 4 is a block diagram illustrating a circuit configuration example of a phase comparison circuit 3 in FIG. 1;

FIG. 5 is a timing chart for explaining the operation of the phase comparison circuit 3;

FIG. 6 is a block diagram illustrating a circuit configuration example of a charge pump unit 4 of FIG. 1;

FIG. 7 is a circuit diagram showing a configuration example of a low-pass filter 5 of FIG.

FIG. 8 is an explanatory diagram illustrating a connection example of a logic circuit 6 and a subsequent circuit.

9 is a circuit diagram illustrating a configuration example of a level shift circuit 21. FIG.

FIG. 10 is a block diagram showing a second embodiment of the present invention.

11 is a block diagram illustrating a configuration example of a buffer amplification unit 7 in FIG.

FIG. 12 is a block diagram showing a third embodiment.

FIG. 13 is a circuit diagram showing a configuration example of a DC-DC converter 13.

FIG. 14 is a block diagram illustrating a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Internal power supply voltage generation part 2 Voltage control oscillation part 3 Phase comparison part 4 Charge pump part 5 Low pass filter part 6 Logic circuit part 7 Buffer amplification part 11 Frequency comparison part 12 Control clock generation part 13 DC-DC converter

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 3/155 H03M 19/00 H03L 7/06

Claims (5)

(57) [Claims] A logic circuit that operates on a first power supply voltage; a clock generation unit that generates a clock signal having a frequency corresponding to a second power supply voltage; and a phase comparison between the clock signal and a reference clock signal. A phase comparison unit, a low-pass filter unit for smoothing an input signal by an integration circuit, a charge pump unit for charging and discharging the low-pass filter unit based on the result of the phase comparison, and a level corresponding to an output of the low-pass filter unit. A power supply voltage generation unit that generates the first power supply voltage, wherein the first and second power supply voltages that operate the logic circuit and the clock generation unit are shared, and the power supply voltage generation unit A semiconductor device characterized by being supplied from a semiconductor device. 2. A logic circuit that operates on a first power supply voltage, a clock generator that generates a clock signal having a frequency corresponding to the second power supply voltage, and compares the phases of the clock signal and a reference clock signal. A phase comparison unit, a low-pass filter unit for smoothing an input signal by an integration circuit, a charge pump unit for charging and discharging the low-pass filter unit based on a result of the phase comparison, and a DC-output of the low-pass filter unit. A buffer amplifier that determines the level of the second power supply voltage; and a power supply voltage generator that determines the level of the first power supply voltage in accordance with the level of the second power supply voltage. A semiconductor device, wherein the first and second power supply voltages are set. 3. The semiconductor device according to claim 1, wherein said clock generator is constituted by a ring oscillator in which a plurality of unit circuits to which said power supply voltage is applied are connected in a cascade at both ends of the circuit. apparatus. 4. The semiconductor device according to claim 3, wherein said unit circuit is an inverter having a CMOS transistor configuration. 5. The frequency divider according to claim 1, further comprising a frequency divider that divides a clock signal output from the clock generator and supplies the frequency-divided clock signal to the phase comparator. Semiconductor device.