JP2007074709A - Voltage controlled oscillation circuit, phase-locked loop circuit using thereof, and semiconductor apparatus with same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a VCO circuit where of the frequency Fo variation of an output signal is reduced even when the power supply voltage is varied. <P>SOLUTION: The VCO circuit includes: a control portion to which a first voltage is input and from which a second voltage corresponding to the first voltage is output; a current source portion to which the second voltage is input and from which a current corresponding to the second voltage is output; and an oscillator circuit to which the current is input and from which a signal with a frequency in accordance with the current is output. The control portion includes an adjusting circuit which changes the second voltage in conjunction with variation of a power supply voltage. Accordingly, the frequency Fo variation of an output signal of the VCO circuit can be reduced even when the power supply voltage of the VCO circuit is varied. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a voltage controlled oscillation circuit and a clock generation circuit using the voltage controlled oscillation circuit. Further, the present invention relates to a semiconductor device provided with a clock generation circuit. In particular, the present invention relates to a phase locked loop circuit as a clock generation circuit.

  In recent years, semiconductors in which various circuits are integrated on the same insulating surface have been developed, and a phase locked loop circuit (Phase) is used as a circuit that generates a clock having an arbitrary frequency synchronized with a supplied signal. A Locked Loop circuit (hereinafter referred to as a PLL circuit) is known.

  The PLL circuit has a voltage controlled oscillation circuit (hereinafter referred to as a VCO (Voltage Controlled Oscillator) circuit), and uses the output of the VCO circuit as a feedback signal to perform phase comparison with a supplied signal. The PLL circuit adjusts the output signal by negative feedback so that the supplied signal and the feedback signal have a constant phase.

  In the VCO circuit, the frequency Fo of the output signal is controlled by an input voltage (hereinafter also referred to as a control voltage of the VCO circuit) Vin (a voltage means a potential difference from the ground unless otherwise specified). The relationship between the voltage and the output frequency changes depending on the fluctuation of the power supply voltage. For this reason, by providing a constant voltage circuit in the VCO circuit, stable phase synchronization of the PLL circuit is realized. However, the voltage generated by the constant voltage circuit varies due to variations in manufacturing conditions such as processes. When the voltage generated by the constant voltage circuit fluctuates, the relationship between the input voltage Vin of the VCO circuit and the frequency Fo of the output signal fluctuates. Further, when the relationship between the input voltage Vin of the VCO circuit and the frequency Fo of the output signal fluctuates, the PLL circuit using the VCO circuit sets the frequency of the output signal (free-running oscillation frequency) to a desired frequency (hereinafter, referred to as “frequency”). (Also referred to as locking at the desired frequency). For this reason, it is necessary to sufficiently widen the range of the power supply voltage of the VCO circuit that can be phase-synchronized with the signal supplied to the PLL circuit.

  As a countermeasure for the above-described problem, there is a method of widening the frequency range of the output signal of the VCO circuit. By doing so, it is possible to ensure that the PLL circuit locks in a desired frequency range even when the power supply voltage fluctuates due to various causes.

  The variable range of the frequency Fo of the output signal with respect to the input voltage Vin of the VCO circuit becomes large. For this reason, the rate of change in the frequency Fo of the output signal (hereinafter referred to as frequency control voltage gain) with respect to the input voltage Vin (hereinafter also referred to as control voltage) becomes steep. When the frequency control voltage gain is increased, the fluctuation of the output signal frequency Fo is increased even for a slight fluctuation of the control voltage, which adversely affects characteristics such as jitter (jitter: fluctuation of delay time of signal etc.).

In such a situation, in order to enable stable locking regardless of variations in circuit operating conditions and manufacturing conditions, a plurality of VCO circuits are provided, and the frequency ranges of output signals of the plurality of VCO circuits are different ranges. And a PLL circuit that selects an optimum VCO circuit from a plurality of VCO circuits has been proposed (see Patent Document 1).
JP 2001-251186 A

  However, in the conventional PLL circuit, a plurality of VCO circuits and a selection circuit for selecting an optimum VCO circuit have to be provided. Therefore, there is a drawback that the circuit scale becomes large. In addition, since the frequency ranges of the output signals of the plurality of VCO circuits are discrete, the lock of the PLL circuit may become unstable at the boundary of the frequency ranges.

  Therefore, an object of the present invention is to provide a VCO circuit in which the fluctuation of the output signal frequency Fo is small even when the power supply voltage fluctuates. It is another object of the present invention to provide a PLL circuit that can adjust the free-running oscillation frequency to be constant and realize a stable lock even when the power supply voltage of the VCO circuit varies. Furthermore, it aims at providing the semiconductor device carrying a PLL circuit.

  The voltage controlled oscillation circuit (VCO circuit) of the present invention includes a control unit that receives a first voltage and outputs a second voltage corresponding to the first voltage, and receives the second voltage and outputs the second voltage. A current source unit that outputs a current corresponding to the second voltage; an oscillation circuit that outputs a signal having a frequency corresponding to the current when the current is input; and the control unit includes an adjustment circuit; The adjusting circuit is characterized in that the second voltage is changed in conjunction with a change in power supply voltage.

  The adjustment circuit decreases the second voltage when the power supply voltage increases, and increases the second voltage when the power supply voltage decreases.

The specific configuration of the control unit is as follows.
(First configuration of control unit)
The control unit includes a first transistor, a second transistor, and a third transistor connected in series to the first transistor. The adjustment circuit includes the second transistor. The third transistor has a gate and a drain connected (hereinafter referred to as a diode connection). The current flowing through the source and drain of the third transistor (hereinafter referred to as drain current) is the sum of the drain current of the first transistor and the drain current of the second transistor. The first voltage is input to the gate of the first transistor. The second voltage is output from the drain of the first transistor. A third voltage is input to the gate of the second transistor. The third voltage changes in conjunction with fluctuations in the power supply voltage.

  The second transistor constitutes a constant current source that allows a constant current to flow according to the third voltage.

  In particular, both the first transistor and the second transistor are N-channel transistors, and when the power supply voltage increases, the third voltage decreases, and when the power supply voltage decreases, the third voltage becomes It is characterized by increasing. That is, the third voltage changes in a direction to decrease the drain current of the second transistor when the power supply voltage increases, and changes in a direction to increase the drain current of the second transistor when the power supply voltage decreases. It is characterized by doing.

  The current gain is adjusted by changing a ratio of the drain current of the second transistor to the drain current of the first transistor. The current gain is the amount of change in the current I flowing through the VCO circuit with respect to the change in the input voltage Vin of the VCO circuit.

  In the first configuration of the control unit, a fourth transistor that forms a current mirror circuit with the third transistor, and a fifth transistor that is connected in series with the fourth transistor and that is diode-connected. You may have. It is assumed that the transistors constituting the current mirror circuit have the same polarity, the gate voltages of these transistors are the same, and the source voltages are the same.

(Second configuration of control unit)
The control unit is connected in series with the first transistor, the second transistor, the third transistor connected in series with the first transistor, the fourth transistor, and the fourth transistor. And a fifth transistor. The adjustment circuit includes the second transistor. The third transistor is diode-connected. The fifth transistor is diode-connected. The first transistor and the fifth transistor constitute a current mirror circuit. The drain current of the third transistor is the sum of the drain current of the first transistor and the drain current of the second transistor. The first voltage is input to the gate of the fourth transistor. The second voltage is output from the drain of the first transistor. A third voltage is input to the gate of the second transistor. The third voltage changes in conjunction with fluctuations in the power supply voltage.

  The second transistor constitutes a constant current source that allows a constant current to flow according to the third voltage.

  In particular, the first transistor and the second transistor are both P-channel transistors, and when the power supply voltage increases, the third voltage increases, and when the power supply voltage decreases, the third voltage becomes It is characterized by decreasing. That is, the third voltage changes in a direction to decrease the drain current of the second transistor when the power supply voltage increases, and changes in a direction to increase the drain current of the second transistor when the power supply voltage decreases. It is characterized by doing.

  The current gain is adjusted by changing a ratio of the drain current of the second transistor to the drain current of the first transistor.

  In the second configuration of the control unit, a sixth transistor that forms a current mirror circuit with the third transistor, and a seventh transistor that is connected in series with the sixth transistor and that is diode-connected You may have.

  The above is a more specific configuration of the control unit.

  The present invention can be a phase-locked loop circuit (PLL circuit) using the voltage controlled oscillation circuit. For example, the voltage controlled oscillation circuit, the frequency divider, the phase comparator, and the loop filter can be used.

  A reference signal and an output of the frequency divider are input to the phase comparator, and a phase difference between the reference signal and an output signal of the frequency divider is output. An output of the phase comparator is output to the loop filter. Is input, noise (mainly high frequency components) of the input signal is removed and output, the output signal of the loop filter is input to the voltage controlled oscillation circuit, and the voltage is input to the frequency divider The output of the control oscillation circuit is input, and the frequency of the input signal is multiplied by 1 / N (N is an arbitrary natural number) and output.

  Furthermore, the present invention can provide a semiconductor device including the phase-locked loop circuit (PLL circuit). For example, the semiconductor device can be applied to a semiconductor device that transmits and receives information wirelessly. As such a semiconductor device, a wireless chip (also referred to as a wireless tag, an IC tag, an IC chip, an RF (Radio Frequency) tag, an RFID tag, an electronic tag, or a transponder), a mobile phone, a cordless phone, a wireless LAN, or the like can be given. .

  Since the VCO circuit of the present invention has the adjustment circuit, the fluctuation of the frequency Fo of the output signal can be reduced even if the power supply voltage fluctuates. In addition, the PLL circuit of the present invention can realize a stable lock by adjusting the free-running oscillation frequency to be constant even when the power supply voltage of the VCO circuit fluctuates.

Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in different drawings. The connection includes an electrical connection.
(Embodiment 1)

  FIG. 1 shows a block diagram of a voltage controlled oscillation circuit (VCO circuit 113) of the present invention. The VCO circuit 113 includes an oscillation circuit 201 and a voltage control current source 207. The voltage control current source 207 includes a control unit 204 and a current source unit 206. The current source unit 206 includes a circuit 202 including a P-channel transistor and a circuit 203 including an N-channel transistor. The control unit 204 includes an adjustment circuit 205.

  The control unit 204 receives the first voltage (denoted as Vin in FIG. 1) and outputs the second voltage (denoted as Vin2 and Vin2 ′ in FIG. 1) corresponding to the first voltage Vin. . The current source unit 206 receives the second voltage (Vin2, Vin2 ') and outputs a current (denoted as Ix in FIG. 1) corresponding to the second voltage (Vin2, Vin2'). Note that Vin2 is input to a circuit 202 including a P-channel transistor, the circuit 202 outputs a current Ix, Vin2 ′ is input to a circuit 203 including an N-channel transistor, and the circuit 203 is a current. -Ix is output. The oscillation circuit 201 receives the current Ix and outputs a signal having a frequency corresponding to the current Ix (denoted as OUT in FIG. 1). The control unit 204 includes an adjustment circuit 205, and the adjustment circuit 205 changes the second voltage (Vin2, Vin2 ') in conjunction with the fluctuation of the power supply voltage VDD.

  The adjustment circuit 205 decreases the second voltage Vin2 when the power supply voltage VDD increases, and increases the second voltage Vin2 when the power supply voltage VDD decreases.

Although FIG. 1 shows a configuration in which the circuit 202 including a P-channel transistor and the circuit 203 including an N-channel transistor are provided, the present invention is not limited to this. Only one of the circuit 202 and the circuit 203 may be used.
(Embodiment 2)

  In this embodiment, a more specific configuration of the control unit 204 in the configuration shown in Embodiment 1 will be described. Note that the present embodiment corresponds to the first configuration of the control unit described in [Means for Solving the Problems].

  FIG. 2 shows a circuit diagram of the current control unit 204. The control unit 204 includes a first transistor 302, a second transistor 303, and a third transistor 301 connected in series to the first transistor 302. Here, the adjustment circuit 205 included in the control unit 204 includes a second transistor 303. The third transistor 301 has a gate and a drain diode-connected.

  The drain current of the third transistor 301 is the sum of the drain current of the first transistor 302 and the drain current of the second transistor 303. The first voltage Vin is input to the gate of the first transistor 302. The second voltage Vin <b> 2 is output from the drain of the first transistor 302. A third voltage (denoted as BIAS in FIG. 2) is input to the gate of the second transistor 303. The second transistor 303 constitutes a constant current source that allows a constant current to flow according to the third voltage BIAS. The third voltage BIAS changes in conjunction with the fluctuation of the power supply voltage VDD.

  Note that the power supply voltage VDD is a potential difference between a high power supply potential (indicated as VDD in the drawing) with respect to a low power supply potential. In the figure, GND is shown as the low power supply potential. Hereinafter, the power supply voltage is simply expressed as VDD. Needless to say, the low power supply potential is not limited to GND, and an arbitrary potential lower than VDD can be used.

  The first transistor 302 and the second transistor 303 are both N-channel transistors. When the power supply voltage VDD increases, the third voltage BIAS decreases, and when the power supply voltage VDD decreases, the third voltage BIAS increases. . That is, the third voltage BIAS changes in a direction to decrease the drain current of the second transistor 303 when the power supply voltage VDD increases, and increases the drain current of the second transistor 303 when the power supply voltage VDD decreases. Change.

  A drain current (denoted as I in FIG. 2) of the third transistor 301 in FIG. 2 is determined according to a desired frequency of the output signal of the VCO circuit 113. Therefore, the drain current of the first transistor 302 (variable current, expressed as I ′ in FIG. 2) and the drain current of the second transistor 303 (constant current, expressed as I ″ in FIG. 2) Is a constant value I at a desired output frequency (I = I ′ + I ″).

  By changing the ratio of the drain current of the second transistor 303 to the drain current of the first transistor 302, the current gain of the VCO circuit 113 at a predetermined power supply voltage VDD can be adjusted. The current gain is a change amount of the current I with respect to a change in the input voltage Vin of the VCO circuit 113 at a predetermined power supply voltage VDD. By adjusting the design of the first transistor 302 (design related to the drain current, such as channel width and channel length), the variable current I ′ can be changed and the current gain of the VCO circuit 113 can be adjusted. Further, the constant current I ″ is changed by adjusting the design of the second transistor 303 (design related to the drain current such as channel width and channel length), and the frequency Fo of the output signal of the VCO circuit 113 is set to a desired value. The frequency can be adjusted.

  In the control unit 204 shown in FIG. 2, the third transistor 301 and the fourth transistor 311 constituting the current mirror circuit and the fourth transistor 311 are connected in series and are diode-connected fifth transistor. 312 may be included. Thus, the control unit 204 outputs the voltage Vin2 'corresponding to the second voltages Vin2 and Vin2.

  In the control unit 204 having the configuration illustrated in FIG. 2, the transistor that forms the current mirror circuit with the third transistor 301 is one of the fourth transistors 311, but is not limited thereto. A plurality of transistors that form a current mirror circuit with the third transistor 301 may be provided, and a transistor connected in series and diode-connected may be provided for each of the plurality of transistors. That is, a plurality of sets of the fourth transistor 311 and the fifth transistor 312 in FIG. 2 may be provided.

This embodiment mode can be implemented by being freely combined with Embodiment Mode 1.
(Embodiment 3)

  In the present embodiment, a more specific configuration of the control unit 204 in the configuration shown in the first embodiment is different from the configuration shown in FIG. 2 of the second embodiment. Note that the present embodiment corresponds to the second configuration of the control unit described in [Means for Solving the Problems].

  FIG. 3 shows a circuit diagram of the control unit 204. The control unit 204 includes a first transistor 411, a second transistor 403, a third transistor 412 connected in series to the first transistor 411, a fourth transistor 402, and a fourth transistor 402. And a fifth transistor 401 connected in series. The adjustment circuit 205 includes a second transistor 403. The third transistor 412 is diode-connected. The fifth transistor 401 is diode-connected. The first transistor 411 and the fifth transistor 401 constitute a current mirror circuit.

  The drain current of the third transistor 412 is the sum of the drain current of the first transistor 411 and the drain current of the second transistor 403. The first voltage Vin is input to the gate of the fourth transistor 402. The second voltage Vin <b> 2 is output from the drain of the first transistor 411. A third voltage (denoted as BIAS in FIG. 3) is input to the gate of the second transistor 403. The second transistor 403 constitutes a constant current source that allows a constant current to flow according to the third voltage BIAS. The third voltage BIAS changes in conjunction with the fluctuation of the power supply voltage VDD.

  The first transistor 411 and the second transistor 403 are both P-channel transistors. When the power supply voltage VDD increases, the third voltage BIAS increases, and when the power supply voltage VDD decreases, the third voltage BIAS decreases. . That is, the third voltage BIAS changes in a direction to decrease the drain current of the second transistor 403 when the power supply voltage VDD increases, and increases the drain current of the second transistor 403 when the power supply voltage VDD decreases. Change.

  The drain current of the third transistor 412 in FIG. 3 (denoted as I in FIG. 3) is determined according to the desired frequency of the output signal of the VCO circuit 113. Therefore, the drain current of the first transistor 411 (variable current, expressed as I ′ in FIG. 3) and the drain current of the second transistor 403 (constant current, expressed as I ″ in FIG. 3) Is a constant value I (I = I ′ + I ″) at a desired output frequency.

  By changing the ratio of the drain current of the second transistor 403 to the drain current of the first transistor 411, the current gain of the VCO circuit 113 at a predetermined power supply voltage VDD can be adjusted. The current gain is a change amount of the current I with respect to a change in the input voltage Vin of the VCO circuit 113 at a predetermined power supply voltage VDD. By adjusting the design of the first transistor 411 (design related to the drain current such as channel width and channel length), the variable current I ′ can be changed and the current gain of the VCO circuit 113 can be adjusted. Further, the constant current I ″ is changed by adjusting the design of the second transistor 403 (design related to the drain current such as channel width and channel length), and the frequency Fo of the output signal of the VCO circuit 113 is set to a desired value. The frequency can be adjusted.

  In the control unit 204 shown in FIG. 3, the third transistor 412 and the sixth transistor 422 constituting the current mirror circuit and the seventh transistor connected in series with the sixth transistor 422 and diode-connected. 421 may be included. Thus, the control unit 204 outputs the voltage Vin2 'corresponding to the second voltages Vin2 and Vin2.

  In the control unit 204 having the configuration illustrated in FIG. 3, the transistor that forms the current mirror circuit with the third transistor 412 is one of the sixth transistors 422, but is not limited thereto. A plurality of transistors that form a current mirror circuit with the third transistor 412 may be provided, and a transistor connected in series and diode-connected may be provided for each of the plurality of transistors. That is, a plurality of sets of the sixth transistor 422 and the seventh transistor 421 in FIG. 3 may be provided.

This embodiment mode can be implemented by being freely combined with Embodiment Mode 1 or Embodiment Mode 2.
(Embodiment 4)

  In this embodiment, a more specific structure of the adjustment circuit 205 is described. FIG. 4 shows the adjustment circuit 205. Note that an example of an N-channel transistor is described as a transistor to which the third voltage BIAS is input to the gate. That is, an example corresponding to the second embodiment is shown. The adjustment circuit 205 includes a monitor circuit 500 and a second transistor 303.

  The monitor circuit 500 includes a P-channel transistor 501, a P-channel transistor 511, an N-channel transistor 502, and an N-channel transistor 512. The gate and drain of the P-channel transistor 501, the gate and drain of the N-channel transistor 502, and the gate of the N-channel transistor 512 are connected. A high power supply potential VDD is applied to the source of the P-channel transistor 501 and the source of the P-channel transistor 511. A low power supply potential (GND in the drawing) is applied to the source of the N-channel transistor 502 and the source of the N-channel transistor 512. The P-channel transistor 511 is diode-connected and connected in series with the N-channel transistor 512. The drain voltage of the P-channel transistor 511 is input to the gate of the second transistor 303 as the third voltage BIAS.

This embodiment mode can be implemented freely combining with Embodiment Modes 1 to 3.
(Embodiment 5)

  In this embodiment, frequency characteristics of the VCO circuit of the present invention will be described.

  First, FIG. 6 shows an ideal frequency characteristic of the VCO circuit. Even when the power supply voltage changes to VDD ′, VDD (> VDD ′), VDD ″ (> VDD ″), the desired output frequency Fo can be obtained when the control voltage Vin is half of the power supply voltage. If it is possible. In the adjustment circuit 205 illustrated in FIG. 4, when the current I ″ flowing through the second transistor 303 increases, the frequency of the output signal of the VCO circuit 113 increases. For this reason, when the power supply voltage decreases from VDD to VDD ′, the control voltage Vin for obtaining the output frequency Fo decreases from VDD / 2 to VDD ′ / 2 when the current I ″ increases.

  FIG. 7 shows the characteristics of the current I of the VCO circuit of the present invention using the adjustment circuit 205. When the current I is 35 μA, the desired output frequency Fo is set. In the case of the power supply voltage of 3.30V, the current I flows at 35 μA at the input voltage of 1.65V is the characteristic of 2). In order to obtain a desired output frequency Fo when the power supply voltage becomes 3.00 V, it must have the characteristic 1). Therefore, by increasing the constant current I ″, the characteristics of the VCO circuit are adjusted from 2) to 1). The same applies to the adjustment from 3) to 2) and from 3) to 1).

This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 4.
(Embodiment 6)

  In this embodiment, a more specific circuit configuration of the VCO circuit 113 will be described with reference to FIG. The VCO circuit 113 shown in FIG. 5 is one specific example of the circuit in the block diagram of FIG.

  The configuration of the control unit 204 is the same as the configuration described with reference to FIG.

  In the oscillation circuit 201, an N-channel transistor 141 and a P-channel transistor 131 are connected in series, and the gates of the N-channel transistor 141 and the P-channel transistor 131 are connected. A plurality of sets (inverter circuits) of such N-channel transistors and P-channel transistors are included (N-channel transistor 141 and P-channel transistor 131, N-channel transistor 142 and P-channel transistor). Transistor 132, N-channel transistor 143 and P-channel transistor 133, N-channel transistor 144 and P-channel transistor 134, N-channel transistor 145 and P-channel transistor 135). In FIG. 5, the oscillation circuit 201 has a configuration in which five inverter circuits are connected in series, but is not limited to this. The plurality of inverters have a loop structure in which an input and an output are connected, and an output of the final stage is connected to an input of the first stage. The number of inverters in this loop must be an odd number for the oscillation circuit 201 to oscillate.

  The current source unit 206 includes a circuit 202 configured with a P-channel transistor and a circuit 203 configured with an N-channel transistor. A circuit 202 including P-channel transistors includes a P-channel transistor 101, a P-channel transistor 102, a P-channel transistor 103, a P-channel transistor 104, a P-channel transistor 105, and a P-channel transistor. A transistor 161, a P-channel transistor 162, a P-channel transistor 163, a P-channel transistor 164, and a P-channel transistor 165. The circuit 203 including N-channel transistors includes an N-channel transistor 151, an N-channel transistor 152, an N-channel transistor 153, an N-channel transistor 154, an N-channel transistor 155, and an N-channel transistor. A transistor 171, an N-channel transistor 172, an N-channel transistor 173, an N-channel transistor 174, and an N-channel transistor 175.

  The first stage 181 is configured by the N-channel transistor 141, the P-channel transistor 131, the P-channel transistor 101, the P-channel transistor 161, the N-channel transistor 151, and the N-channel transistor 171. The Similarly, the second stage 182 includes an N-channel transistor 142 and a P-channel transistor 132, a P-channel transistor 102, a P-channel transistor 162, an N-channel transistor 152, and an N-channel transistor 172. Is configured. The third stage 183 includes the N-channel transistor 143, the P-channel transistor 133, the P-channel transistor 103, the P-channel transistor 163, the N-channel transistor 153, and the N-channel transistor 173. The The fourth stage 184 is configured by the N-channel transistor 144, the P-channel transistor 134, the P-channel transistor 104, the P-channel transistor 164, the N-channel transistor 154, and the N-channel transistor 174. The The fifth stage 185 is configured by the N-channel transistor 145, the P-channel transistor 135, the P-channel transistor 105, the P-channel transistor 165, the N-channel transistor 155, and the N-channel transistor 175. The In FIG. 5, the combined portion of the oscillation circuit 201, the circuit 202, and the circuit 203 has a structure in which a first stage 181 to a fifth stage 185 are connected in series.

  Since the connection relationship of each transistor in each stage is the same, the first stage 181 will be described as a representative. Each of the P-channel transistor 101 and the P-channel transistor 161 is connected in series with the P-channel transistor 131. Each of the N-channel transistor 151 and the N-channel transistor 171 is connected in series with the N-channel transistor 141. The second voltage Vin2 is input to the gate of the P-channel transistor 101, and the second voltage Vin2 'is input to the gate of the N-channel transistor 151. The gate of the P-channel transistor 161 is connected to the gate of the N-channel transistor 151, and the gate of the N-channel transistor 171 is connected to the drain of the P-channel transistor 101.

In FIG. 5, the combined portion of the oscillation circuit 201, the circuit 202, and the circuit 203 has a structure in which the first stage 181 to the fifth stage 185 are connected in series; however, the present invention is not limited to this. Further, a plurality of stages may be provided. Note that the number of stages must be an odd number.

This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 5.
(Embodiment 7)

  In this embodiment, an example in which the VCO circuit having the configuration shown in FIG. 5 in Embodiment 6 is actually manufactured will be described. FIG. 8 shows a mask drawing of the VCO circuit.

  8 that are the same as those in FIG. 5 are denoted by the same reference numerals, and description thereof is omitted. In FIG. 8, VSS is a low power supply potential and corresponds to GND in FIG.

This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 6.
(Embodiment 8)

  In this embodiment mode, a structure of a PLL circuit including the VCO circuit 113 of the present invention will be described with reference to FIG.

  The phase-locked loop circuit (PLL circuit 115) can include a VCO circuit 113, a frequency divider 114, a phase comparator 111, and a loop filter 112. The VCO circuit 113 can have the structure described in any of Embodiments 1 to 7.

  The phase comparator 111 receives a reference signal of frequency Fs (indicated as INPUT in FIG. 9) and the output of the frequency divider 114, and the phase difference between the reference signal INPUT and the output signal of the frequency divider 114 (in FIG. 9). , PD). The output of the phase comparator 111 is input to the loop filter 112, and the high frequency component of the input signal is removed and output. The output signal Vin of the loop filter 112 is input to the VCO circuit 113. The output of the VCO circuit 113 (frequency is expressed as Fo in FIG. 9) is input to the frequency divider 114, and the frequency of the input signal is multiplied by 1 / N (N is an arbitrary natural number) and output (FIG. 9 shows the frequency as Fo / N).

  The phase comparator 111, the loop filter 112, and the frequency divider 114 are provided in a timely manner according to the application.

  Since the phase comparator 111 is a multiplier in principle, it should be replaced with an analog phase comparator (DBM (Double Balanced Mixer), etc.) or a digital phase comparator (XOR, RD flip-flop, or current output type). Can do.

  Similarly, the loop filter 112 only needs to play a role of removing high-frequency components, and can be replaced with a passive loop filter (low-pass filter, lag-lead filter) or an active loop filter.

  Further, if a prescaler (fixed frequency divider) with a high operating frequency is inserted in the frequency divider 114, a high frequency Fo can be obtained. If the frequency divider 114 is provided with a programmable frequency divider, an arbitrary frequency Fo can be obtained.

  In the present embodiment, the frequency Fs of the reference signal INPUT may be input using a crystal oscillator. Alternatively, the frequency Fs of the reference signal INPUT may be input by an LC resonance circuit. By providing the LC resonance circuit, the PLL circuit 115 can be downsized. Thus, the semiconductor device provided with the PLL circuit 115 can be reduced in size.

  Further, the PLL circuit 115 according to the present embodiment may include other components, and may include, for example, a swallow counter. For example, if a swallow counter is provided, an arbitrary frequency Fo can be obtained.

This embodiment mode can be implemented by being freely combined with Embodiment Modes 1 to 7.
(Embodiment 9)

  The present invention can provide a semiconductor device including a phase-locked loop circuit (PLL circuit). For example, the semiconductor device can be applied to a semiconductor device that transmits and receives information wirelessly. As such a semiconductor device, a wireless chip (also referred to as a wireless tag, an IC tag, an IC chip, an RF (Radio Frequency) tag, an RFID tag, an electronic tag, or a transponder), a mobile phone, a cordless phone, a wireless LAN, or the like can be given. .

  The structure of the wireless chip 1000 of the present invention will be described with reference to FIG. The wireless chip 1000 includes an antenna 1001, a bandpass filter 1002, a power supply circuit 1003, a demodulation circuit 1004, a modulation circuit 1005, a PLL circuit 1006, a code recognition and determination circuit 1007, a memory 1008, and an encoding circuit 1009. Etc. As the PLL circuit 1006, the circuit having the structure described in Embodiment 8 can be used.

  The antenna 1001 transmits and receives radio signals. The radio signal received by the antenna 1001 is subjected to noise removal by the band filter 1002 and input to the power supply circuit 1003 and the demodulation circuit 1004. The power supply circuit 1003 generates a DC power supply voltage for a circuit in the wireless chip 1000 using the input signal. The demodulation circuit 1004 demodulates the input wireless signal. The demodulated signal is input to the PLL circuit 1006 and the code recognition and determination circuit 1007. The PLL circuit 1006 generates a clock having a predetermined frequency from the input signal. The code recognition and determination circuit 1007 analyzes the code of the demodulated signal based on the clock output from the PLL circuit 1006, and obtains corresponding information. Information is exchanged with the memory 1008 in accordance with the analyzed information. Information output from the memory 1008 is encoded by the encoding circuit 1009. The encoded signal is converted into a radio signal by the modulation circuit 1005 and transmitted from the antenna 1001.

  In the present invention, the reliability of the PLL circuit 1006 can be increased and the size can be reduced. Thus, the reliability of the wireless chip 1000 including the PLL circuit 1006 can be increased and the size can be reduced.

  This embodiment mode can be implemented freely combining with Embodiment Modes 1 to 9.

  In this embodiment, a specific structure of the semiconductor device of the present invention will be described with reference to FIGS.

  Configuration examples of the antenna 1001 in the semiconductor device of the present invention are shown in FIGS. There are two ways to provide the antenna 1001, and one of them (hereinafter referred to as a first antenna installation method) is shown in FIGS. 11A and 11C. The other (hereinafter referred to as the second antenna installation method) is shown in FIGS. 11B and 11D. FIG. 11C corresponds to a cross-sectional view taken along lines A to A ′ in FIG. 11A, and FIG. 11D corresponds to a cross-sectional view taken along lines B to B ′ in FIG.

  In the first antenna installation method, an antenna 1001 is provided over a substrate 600 over which a plurality of elements (hereinafter referred to as an element group 601) is provided (see FIGS. 11A and 11C). The element group 601 forms a circuit other than the antenna of the semiconductor device of the present invention. The element group 601 includes a plurality of thin film transistors. In the structure illustrated, the conductive film functioning as the antenna 1001 is provided in the same layer as the wiring connected to the source and drain of the thin film transistor included in the element group 601. However, the conductive film functioning as the antenna 1001 may be provided in the same layer as the gate electrode 664 of the thin film transistor included in the element group 601, or an insulating film is further provided over the insulating film so as to cover the element group 601. Also good.

  In the second antenna installation method, the terminal portion 602 is provided on the substrate 600 provided with the element group 601. Then, an antenna 1001 provided over a substrate 610 different from the substrate 600 is connected so as to be connected to the terminal portion 602 (see FIGS. 11B and 11D). In the structure shown in the drawing, part of the wiring connected to the source and drain of the thin film transistor included in the element group 601 is used as the terminal portion 602. Then, the substrate 600 and the substrate 610 provided with the antenna 1001 are attached so as to be connected to the terminal portion 602. Conductive particles 603 and a resin 604 are provided between the substrate 600 and the substrate 610. The antenna 1001 and the terminal portion 602 are electrically connected by the conductive particles 603.

  A structure and a manufacturing method of the element group 601 will be described. If a plurality of element groups 601 are formed on a large-area substrate and then completed by being divided, an inexpensive device can be provided. As the substrate 600, for example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a semiconductor substrate having an insulating film formed on the surface thereof may be used. A substrate made of a synthetic resin having flexibility such as plastic may be used. The surface of the substrate may be planarized by polishing such as CMP. Further, a glass substrate, a quartz substrate, or a substrate obtained by polishing and thinning a semiconductor substrate may be used.

  As the base layer 661 provided over the substrate 600, an insulating film such as silicon oxide, silicon nitride, or silicon nitride oxide can be used. The base layer 661 can prevent alkali metal or alkaline earth metal such as Na contained in the substrate 600 from diffusing into the semiconductor layer 662 and adversely affecting the characteristics of the thin film transistor. In FIG. 11, the base layer 661 has a single-layer structure, but it may be formed of two or more layers. Note that the base layer 661 is not necessarily provided when diffusion of impurities such as a quartz substrate does not cause any problem.

Note that the surface of the substrate 600 may be directly processed by high-density plasma. The high density plasma is generated by using microwaves, for example 2.45 GHz. As the high density plasma, one having an electron density of 10 ¹¹ to 10 ¹³ / cm ³ , an electron temperature of 2 eV or less, and an ion energy of 5 eV or less is used. As described above, high-density plasma characterized by low electron temperature has low kinetic energy of active species, and thus can form a film with less plasma damage and fewer defects than conventional plasma treatment. Plasma generation can be performed using a microwave-excited plasma processing apparatus using a radial slot antenna. The distance from the antenna that generates the microwave to the substrate 600 is 20 to 80 mm (preferably 20 to 60 mm).

A nitriding atmosphere such as nitrogen (N) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere, nitrogen, hydrogen (H), a rare gas atmosphere, or ammonia (NH ₃ ) In the rare gas atmosphere, the surface of the substrate 600 can be nitrided by performing the high-density plasma treatment. When glass, quartz, silicon wafer, or the like is used as the substrate 600, the nitride layer formed on the surface of the substrate 600 contains silicon nitride as a main component, so that it can be used as a blocking layer for impurities diffused from the substrate 600 side. can do. A silicon oxide film or a silicon oxynitride film may be formed over the nitride layer by a plasma CVD method to form the base layer 661.

  Further, by performing similar high-density plasma treatment on the surface of the base layer 661 made of silicon oxide, silicon oxynitride, or the like, nitridation treatment with a depth of 1 to 10 nm can be performed from the surface and the surface. This extremely thin silicon nitride layer is preferable because it functions as a blocking layer and is less affected by stress on the semiconductor layer 662 formed thereon.

  As the semiconductor layer 662, an island-shaped crystalline semiconductor film or an amorphous semiconductor film can be used. Further, an organic semiconductor film may be used. The crystalline semiconductor film can be obtained by crystallizing an amorphous semiconductor film. As a crystallization method, a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or the like can be used. The semiconductor layer 662 includes a channel formation region 662a and a pair of impurity regions 662b to which an impurity element imparting a conductivity type is added. Note that although the structure including the low-concentration impurity region 662c to which the impurity element is added at a lower concentration than the impurity region 662b is shown between the channel formation region 662a and the pair of impurity regions 662b, the invention is not limited thereto. A structure in which the low concentration impurity region 662c is not provided may be employed.

  Note that the wiring formed at the same time as the semiconductor layer 662 is preferably led so that corners are rounded when viewed from a direction perpendicular to the top surface of the substrate 600. The wiring routing method is schematically shown in FIG. A wiring formed simultaneously with the semiconductor layer is indicated by a wiring a in the figure. FIG. 13A shows a conventional wiring routing method. FIG. 13B shows a wiring routing method according to the present invention. The corner 1202a is round with respect to the conventional corner 1201a. By rounding the corner, it is possible to prevent dust and the like from remaining at the corner of the wiring. Thus, defects due to dust in the semiconductor device can be reduced and the yield can be increased.

  An impurity element imparting a conductivity type may be added to the channel formation region 662a of the thin film transistor. Thus, the threshold voltage of the thin film transistor can be controlled.

The first insulating layer 663 can be formed using silicon oxide, silicon nitride, silicon nitride oxide, or the like by stacking a single layer or a plurality of films. In this case, the surface of the first insulating layer 663 may be densified by treatment with high-density plasma in an oxidizing atmosphere or a nitriding atmosphere, and oxidizing or nitriding treatment. The high density plasma is generated by using a microwave, for example, 2.45 GHz, as described above. As the high density plasma, one having an electron density of 10 ¹¹ to 10 ¹³ / cm ³ , an electron temperature of 2 eV or less, and an ion energy of 5 eV or less is used. Plasma generation can be performed using a microwave-excited plasma processing apparatus using a radial slot antenna. In the apparatus for generating high-density plasma, the distance from the antenna that generates microwaves to the substrate 600 is set to 20 to 80 mm (preferably 20 to 60 mm).

  Note that before the first insulating layer 663 is formed, the surface of the semiconductor layer 662 may be oxidized or nitrided by performing the above high-density plasma treatment. At this time, by performing treatment in an oxidizing atmosphere or a nitriding atmosphere at a temperature of the substrate 600 of 300 to 450 ° C., a favorable interface can be formed with the first insulating layer 663 deposited thereon.

The nitriding atmosphere may be a nitrogen (N) and rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere, a nitrogen and hydrogen (H) and rare gas atmosphere, or ammonia (NH ₃ ) And a noble gas atmosphere. As the oxidizing atmosphere, an oxygen (O) and rare gas atmosphere, an oxygen and hydrogen (H) and rare gas atmosphere, or a dinitrogen monoxide (N 2 O) and rare gas atmosphere can be used.

  As the gate electrode 664, a single layer or a stacked structure including one kind of element selected from Ta, W, Ti, Mo, Al, Cu, Cr, and Nd, or an alloy or compound containing a plurality of such elements can be used. In the figure, a gate electrode 664 having a two-layer structure is shown. Note that the gate electrode 664 and the wiring formed at the same time as the gate electrode 664 are preferably led so that corners are rounded when viewed from a direction perpendicular to the top surface of the substrate 600. The routing method can be the same as the method shown in FIG. A wiring formed simultaneously with the gate electrode 664 and the gate electrode 664 is indicated by a wiring b in the figure. By rounding the corner portion like the corner portion 1202b with respect to the corner portion 1201b, dust or the like can be prevented from remaining in the corner portion of the wiring. Thus, defects due to dust in the semiconductor device can be reduced and the yield can be increased.

  The thin film transistor includes a semiconductor layer 662, a gate electrode 664, and a first insulating layer 663 that functions as a gate insulating film between the semiconductor layer 662 and the gate electrode 664. In this embodiment, the thin film transistor is shown as a top gate type transistor, but it may be a bottom gate type transistor having a gate electrode below the semiconductor layer, or a dual gate type having gate electrodes above and below the semiconductor layer. This transistor may be used.

The second insulating layer 667 is preferably a barrier insulating film that blocks ionic impurities, such as a silicon nitride film. The second insulating layer 667 is formed using silicon nitride or silicon oxynitride. The second insulating layer 667 functions as a protective film that prevents contamination of the semiconductor layer 662. After the second insulating layer 667 is deposited, the second insulating layer 667 may be hydrogenated by introducing hydrogen gas and performing high-density plasma treatment as described above. Alternatively, the second insulating layer 667 may be nitrided and hydrogenated by introducing ammonia (NH ₃ ) gas. Alternatively, oxynitriding treatment and hydrogenation treatment may be performed by introducing oxygen, dinitrogen monoxide (N ₂ O) gas, or the like and hydrogen gas. By this method, the surface of the second insulating layer 667 can be densified by performing nitriding treatment, oxidation treatment, or oxynitridation treatment. Thus, the function of the second insulating layer 667 as a protective film can be enhanced. The hydrogen introduced into the second insulating layer 667 is then released by heat treatment at 400 to 450 ° C., so that the semiconductor layer 662 can be hydrogenated. Note that this hydrogenation treatment may be combined with a hydrogenation treatment using the first insulating layer 663.

  As the third insulating layer 665, a single layer or a stacked structure of an inorganic insulating film or an organic insulating film can be used. As the inorganic insulating film, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method, or the like can be used. As an organic insulating film, polyimide, polyamide, BCB (benzoic acid) is used. A film such as cyclobutene), acrylic or positive photosensitive organic resin, or negative photosensitive organic resin can be used.

  Alternatively, the third insulating layer 665 can be formed using a material having a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent of this material, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  As the wiring 666, a single layer or a stacked structure including one kind of element selected from Al, Ni, W, Mo, Ti, Pt, Cu, Ta, Au, and Mn or an alloy containing a plurality of such elements can be used. . In the figure, an example of a single layer structure is shown. Note that the wiring 666 is preferably led so that corners are rounded when viewed from a direction perpendicular to the top surface of the substrate 600. The routing method can be the same as the method shown in FIG. A wiring 666 is indicated by a wiring c in the figure. By rounding the corner portion like the corner portion 1202c with respect to the corner portion 1201c, dust or the like can be prevented from remaining at the corner portion of the wiring. Thus, defects due to dust in the semiconductor device can be reduced and the yield can be increased. In the structures illustrated in FIGS. 11A and 11C, the wiring 666 serves as an antenna 1001 as well as a wiring connected to the source and drain of the thin film transistor. In the structures illustrated in FIGS. 11B and 11D, the wiring 666 serves as a terminal connected to the source and drain of the thin film transistor and serves as a terminal portion 602.

  Note that the antenna 1001 can also be formed by a droplet discharge method using a conductive paste containing nanoparticles such as Au, Ag, or Cu. The droplet discharge method is a general term for a method of forming a pattern by discharging droplets, such as an inkjet method or a dispenser method, and has advantages such as improvement in material utilization efficiency.

  In the structure illustrated in FIGS. 11A and 11C, a fourth insulating layer 668 is formed over the wiring 666. As the fourth insulating layer 668, a single layer or a stacked structure of an inorganic insulating film or an organic insulating film can be used. The fourth insulating layer 668 functions as a protective layer of the antenna 1001.

  Further, the element group 601 formed over the substrate 600 (see FIG. 12A) may be used as it is, but the element group 601 on the substrate 600 is peeled off (see FIG. 12B), The element group 601 may be attached to the flexible substrate 701 (see FIG. 12C). The flexible substrate 701 has flexibility, and for example, a plastic substrate such as polycarbonate, polyarylate, or polyether sulfone, or a ceramic substrate can be used.

  Peeling of the element group 601 from the substrate 600 can be performed by (A) providing a peeling layer between the substrate 600 and the element group 601 in advance and removing the peeling layer with an etching agent, or (B) The peeling layer is partially removed with an etchant, and then the substrate 600 and the element group 601 are physically peeled, or (C) the highly heat-resistant substrate 600 on which the element group 601 is formed is mechanically formed. A method of separating the element group 601 can be used by deleting or removing by etching with a solution or gas. It should be noted that peeling by physical means means peeling by applying stress from the outside, for example, peeling by applying stress from the wind pressure of a gas blown from a nozzle or ultrasonic waves. .

  As a more specific method of the above (A) or (B), a metal oxide film is provided between the substrate 600 having high heat resistance and the element group 601, and the metal oxide film is weakened by crystallization, whereby the element A method of peeling the group 601 or an amorphous silicon film containing hydrogen between the highly heat-resistant substrate 600 and the element group 601 and removing the amorphous silicon film by laser light irradiation or etching. Thus, a method of peeling the element group 601 can be used.

  The peeled element group 601 may be attached to the flexible substrate 701 using a commercially available adhesive, for example, an adhesive such as an epoxy resin adhesive or a resin additive.

  When the element group 601 is attached to a flexible substrate 701 on which an antenna is formed and is electrically connected to the antenna, the semiconductor device is completed which is thin, light, and difficult to break even when dropped (FIG. 12C). reference). When an inexpensive flexible substrate 701 is used, an inexpensive semiconductor device can be provided. Further, since the flexible substrate 701 has flexibility, the flexible substrate 701 can be bonded onto a curved surface or an irregular shape, thereby realizing a wide variety of uses. For example, the wireless chip 1000 which is one embodiment of the semiconductor device of the present invention can be tightly attached to a curved surface such as a medicine bottle (see FIG. 12D). Further, when the substrate 600 is reused, a semiconductor device can be manufactured at low cost.

  The element group 601 can be sealed by covering it with a film. The surface of the film may be coated with silicon dioxide (silica) powder. The coating can maintain waterproofness even in a high temperature and high humidity environment. That is, it can have a moisture resistance function. Further, the surface of the film may have an antistatic function. The surface of the film may be coated with a material containing carbon as a main component (for example, diamond-like carbon). The coating increases the strength and can suppress deterioration and destruction of the semiconductor device. The film may be formed of a material obtained by mixing a base material (for example, resin) with silicon dioxide, a conductive material, or a material containing carbon as a main component. Further, an antistatic function can be provided by applying a surfactant to the surface of the film or by directly kneading the surfactant.

  This embodiment can be freely combined with the above embodiment modes.

  In this embodiment, an example in which the semiconductor device of the present invention is configured to be flexible will be described. FIG. 14 is used for the description. 14A, a semiconductor device of the present invention includes a flexible protective layer 901, a flexible protective layer 903 including an antenna 902 (corresponding to the antenna 1001), an element formed by a peeling process or thinning of a substrate. A group 904. The element group 904 can have a structure similar to the structure shown as the element group 601 in the first embodiment. An antenna 902 formed over the protective layer 903 is electrically connected to the element group 904. In FIG. 14, the antenna 902 is formed only on the protective layer 903; however, the present invention is not limited to this structure, and the antenna 902 may also be formed on the protective layer 901. Note that a barrier film formed of a silicon nitride film or the like is preferably formed between the element group 904 and the protective layer 901 and the protective layer 903. Then, a semiconductor device with improved reliability can be provided without the element group 904 being contaminated.

  The antenna 902 can be formed of Ag, Cu, or a metal plated with them. The element group 904 and the antenna 902 can be connected by performing an ultraviolet treatment or an ultrasonic treatment using an anisotropic conductive film. Note that the element group 904 and the antenna 902 may be bonded using a conductive paste or the like.

  A semiconductor device is completed by sandwiching the element group 904 between the protective layer 901 and the protective layer 903 (see arrows in FIG. 14A).

A cross-sectional structure of the semiconductor device thus formed is shown in FIG. The thickness of the sandwiched element group 904 is 5 μm or less, preferably 0.1 μm to 3 μm. Further, when the thickness when the protective layer 901 and the protective layer 903 are overlapped is d, the thickness of the protective layer 901 and the protective layer 903 is preferably (d / 2) ± 30 μm, more preferably (d / 2) Set to ± 10 μm. The thickness of the protective layer 901 and the protective layer 903 is preferably 10 μm to 200 μm. Further, the area of the element group 904 is 10 mm square (100 mm ² ) or less, and preferably 0.3 mm square to 4 mm square (0.09 mm ^{2 to} 16 mm ² ).

  Since the protective layer 901 and the protective layer 903 are made of an organic resin material, they have a strong characteristic against bending. In addition, the element group 904 itself formed by a peeling process or thinning of the substrate also has a strong characteristic against bending compared to a single crystal semiconductor. Since the element group 904 and the protective layer 901 and the protective layer 903 can be in close contact with each other so that there is no gap, the completed semiconductor device itself has a strong characteristic against bending. The element group 904 surrounded by the protective layer 901 and the protective layer 903 may be arranged on the surface or inside of another solid object, or may be embedded in paper.

  A case where a semiconductor device including the element group 904 is attached to a substrate having a curved surface will be described. FIG. 14C is used for the description. In the drawing, one transistor 981 selected from the element group 904 is shown. The transistor 981 flows current from one of the source and drain 905 to the other of the source and drain 906 in accordance with the potential of the gate electrode 907. The transistor 981 is arranged so that the direction in which the current of the transistor 981 flows (carrier movement direction) and the direction in which the substrate 980 draws an arc are orthogonal to each other. With such an arrangement, even when the substrate 980 is bent so as to draw an arc, the influence of stress applied to the transistor 981 is small, and variation in characteristics of the transistor 981 included in the element group 904 can be suppressed.

  This embodiment can be freely combined with the above embodiment mode and Embodiment 1.

  In this embodiment, a structural example of a transistor included in a circuit included in the semiconductor device of the present invention is shown. In addition to a MOS transistor formed on a single crystal substrate, the transistor can be a thin film transistor (TFT). FIG. 17 is a diagram showing a cross-sectional structure of transistors constituting these circuits. FIG. 17 illustrates an N-channel transistor 2001, an N-channel transistor 2002, a capacitor element 2004, a resistor element 2005, and a P-channel transistor 2003. Each transistor includes a semiconductor layer 4405, an insulating layer 4408, and a gate electrode 4409. The gate electrode 4409 has a stacked structure of a first conductive layer 4403 and a second conductive layer 4402. 18A to 18D are top views corresponding to the transistor, the capacitor, and the resistor illustrated in FIG. 17 and can be referred to.

  In FIG. 17, an N-channel transistor 2001 includes lightly doped drain (LDD) regions on both sides of a region overlapping with the gate electrode in the semiconductor layer 4405. The lightly doped drain (LDD) region is an impurity region 4407, which is doped with an impurity imparting N-type at a lower concentration than the impurity concentration of the source region and the drain region (impurity region 4406) that form a contact with the wiring 4404. Yes. In the case where the N-channel transistor 2001 is formed, phosphorus or the like is added to the impurity region 4406 and the impurity region 4407 as an impurity imparting N-type conductivity. The LDD region is formed as a means for suppressing hot electron degradation and the short channel effect.

  As shown in FIG. 18A, in the gate electrode 4409 of the N-channel transistor 2001, the first conductive layer 4403 is formed so as to spread on both sides of the second conductive layer 4402. In this case, the first conductive layer 4403 is thinner than the second conductive layer 4402. The first conductive layer 4403 is formed to have a thickness that allows ionic species accelerated by an electric field of 10 to 100 kV to pass therethrough. The impurity region 4407 is formed so as to overlap with the first conductive layer 4403 of the gate electrode 4409. That is, an LDD region overlapping with the gate electrode 4409 is formed. In this structure, an impurity region 4407 is formed in a self-aligned manner in the gate electrode 4409 by adding an impurity of one conductivity type through the first conductive layer 4403 using the second conductive layer 4402 as a mask. That is, the LDD region overlapping with the gate electrode is formed in a self-aligning manner.

  A transistor having an LDD on both sides of a region overlapping with a gate electrode in a semiconductor layer is applied to a transistor forming a transmission gate (also referred to as an analog switch) or a transistor used in a rectifier circuit in the power supply circuit 1003 in FIG. . In these transistors, since both positive and negative voltages are applied to the source electrode and the drain electrode, it is preferable to provide LDDs on both sides of a region overlapping with the gate electrode in the semiconductor layer.

  In FIG. 17, an N-channel transistor 2002 includes an impurity region 4407 in which an impurity element imparting a conductivity type is doped at a lower concentration than the impurity concentration of the impurity region 4406 on one side of a region overlapping with the gate electrode in the semiconductor layer 4405. Is formed. As shown in FIG. 18B, in the gate electrode 4409 of the N-channel transistor 2002, the first conductive layer 4403 is formed so as to spread on one side of the second conductive layer 4402. In this case as well, an LDD can be formed in a self-aligned manner by adding an impurity of one conductivity type through the first conductive layer 4403 using the second conductive layer 4402 as a mask.

  A transistor having an LDD on one side of a region overlapping with a gate electrode in a semiconductor layer may be applied to a transistor to which only a positive voltage or only a negative voltage is applied between a source electrode and a drain electrode. Specifically, it may be applied to a transistor constituting a logic gate such as an inverter circuit, a NAND circuit, a NOR circuit, or a latch circuit, or a transistor constituting an analog circuit such as a sense amplifier, a constant voltage generation circuit, or a VCO.

  In FIG. 17, the capacitor element 2004 is formed by sandwiching an insulating layer 4408 between a first conductive layer 4403 and a semiconductor layer 4405. A semiconductor layer 4405 that forms the capacitor 2004 includes an impurity region 4410 and an impurity region 4411. The impurity region 4411 is formed in the semiconductor layer 4405 so as to overlap with the first conductive layer 4403. In addition, the impurity region 4410 forms a contact with the wiring 4404. Since the impurity region 4411 can be doped with one conductivity type impurity through the first conductive layer 4403, the impurity concentration in the impurity region 4410 and the impurity region 4411 can be the same or can be different. It is. In any case, since the semiconductor layer 4405 functions as an electrode in the capacitor 2004, it is preferable to reduce the resistance by adding an impurity of one conductivity type. In addition, as shown in FIG. 18C, the first conductive layer 4403 can function sufficiently as an electrode by using the second conductive layer 4402 as an auxiliary electrode. In this manner, by using a composite electrode structure in which the first conductive layer 4403 and the second conductive layer 4402 are combined, the capacitor element 2004 can be formed in a self-aligning manner.

  The capacitor 2004 can be used as a storage capacitor of the power supply circuit 1003 illustrated in FIG. 10, a resonance capacitor provided in parallel with the antenna 1001, or a capacitor included in the demodulation circuit 1004. In particular, since both positive and negative voltages are applied between the two terminals of the capacitive element, the resonant capacitor needs to function as a capacitor regardless of whether the voltage between the two terminals is positive or negative.

  In FIG. 17, the resistance element 2005 is formed of the first conductive layer 4403 (see also FIG. 18D). Since the first conductive layer 4403 is formed to a thickness of about 30 to 150 nm, a resistance element can be configured by appropriately setting the width and length thereof.

  The resistance element can be used as a resistance load included in the modulation circuit 1005 illustrated in FIG. Further, it can also be used as a resistance element included in the demodulation circuit 1004 shown in FIG. Further, it may be used as a load when current is controlled by a VCO circuit or the like. The resistance element may be formed using a semiconductor layer containing an impurity element at a high concentration or a thin metal layer. In contrast to a semiconductor layer whose resistance value depends on the film thickness, film quality, impurity concentration, activation rate, and the like, a metal layer is preferable because the resistance value is determined by the film thickness and film quality, so that variation is small.

  In FIG. 17, a P-channel transistor 2003 includes an impurity region 4412 in a semiconductor layer 4405. This impurity region 4412 functions as a source region and a drain region that form a contact with the wiring 4404. The gate electrode 4409 has a structure in which the first conductive layer 4403 and the second conductive layer 4402 overlap with each other (see also FIG. 18E). The P-channel transistor 2003 is a single drain transistor without an LDD. In the case of forming the P-channel transistor 2003, boron or the like is added to the impurity region 4412 as an impurity imparting P-type conductivity. On the other hand, when phosphorus is added to the impurity region 4412, an N-channel transistor having a single drain structure can be obtained.

  One or both of the semiconductor layer 4405 and the gate insulating layer 4408 may be oxidized or nitrided by high density plasma treatment. This process can be performed in the same manner as in the first embodiment.

  Through the above treatment, the defect level at the interface between the semiconductor layer 4405 and the gate insulating layer 4408 can be reduced. By performing this treatment on the gate insulating layer 4408, the insulating layer can be densified. That is, generation of charged defects can be suppressed and fluctuations in the threshold voltage of the transistor can be suppressed. In the case where the transistor is driven with a voltage of 3 V or lower, an insulating layer oxidized or nitrided by this plasma treatment can be used as the gate insulating layer 4408. In the case where the driving voltage of the transistor is 3 V or more, a gate is formed by combining an insulating layer formed on the surface of the semiconductor layer 4405 by this plasma treatment and an insulating layer deposited by a CVD method (plasma CVD method or thermal CVD method). An insulating layer 4408 can be formed. Similarly, this insulating layer can also be used as a dielectric layer of the capacitor element 2004. In this case, since the insulating layer formed by this plasma treatment is formed with a thickness of 1 to 10 nm and is a dense film, a capacitor having a large charge capacity can be formed.

  As described with reference to FIGS. 17 and 18, elements having various structures can be formed by combining conductive layers having different thicknesses. The region where only the first conductive layer is formed and the region where the first conductive layer and the second conductive layer are laminated are a photo provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It can be formed using a mask or a reticle. That is, in the photolithography process, when the photoresist is exposed, the amount of light transmitted through the photomask is adjusted to vary the thickness of the resist mask to be developed. In this case, a resist having a complicated shape may be formed by providing a slit having a resolution limit or less in a photomask or a reticle. Alternatively, the mask pattern formed of the photoresist material may be deformed by baking at about 200 ° C. after development.

  Further, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film, a region where only the first conductive layer is formed, the first conductive layer and the second conductive layer A region where the conductive layer is stacked can be formed continuously. As shown in FIG. 18A, a region where only the first conductive layer is formed can be selectively formed over the semiconductor layer. Such a region is effective on the semiconductor layer, but is not necessary in other regions (a wiring region continuous with the gate electrode). By using this photomask or reticle, it is not necessary to form a region of only the first conductive layer in the wiring portion, so that the wiring density can be substantially increased.

  17 and 18, the first conductive layer is a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or a refractory metal. An alloy or a compound mainly composed of is formed with a thickness of 30 to 50 nm. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. To a thickness of 300 to 600 nm. For example, different conductive materials are used for the first conductive layer and the second conductive layer, and a difference in etching rate is caused in an etching process performed later. As an example, TaN can be used as the first conductive layer, and a tungsten film can be used as the second conductive layer.

  In this embodiment, transistors, capacitors, and resistors having different electrode structures are formed by the same process using a photomask or reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film. It shows that it can be divided. Thus, elements having different forms can be formed and integrated without increasing the number of steps in accordance with circuit characteristics.

  This embodiment can be freely combined with the above embodiment mode, Embodiment 1 and Embodiment 2.

  In this embodiment, an example of a static RAM (SRAM) that can be used as a memory (such as MROM_UNIT 305 in FIG. 3) of the semiconductor device of the present invention will be described with reference to FIGS.

  The semiconductor layer 10 and the semiconductor layer 11 illustrated in FIG. 19A are preferably formed using silicon or a crystalline semiconductor containing silicon as a component. For example, polycrystalline silicon or single crystal silicon obtained by crystallizing a silicon film by laser annealing or the like is applied. In addition, a metal oxide semiconductor, amorphous silicon, or an organic semiconductor that exhibits semiconductor characteristics can be used.

  In any case, the semiconductor layer to be formed first is formed over the entire surface or part of the substrate having an insulating surface (a region having a larger area than that determined as a semiconductor region of the transistor). Then, a mask pattern is formed on the semiconductor layer by photolithography. By etching the semiconductor layer using the mask pattern, island-shaped semiconductor layers 10 and 11 having a specific shape including a source region and a drain region of the transistor and a channel formation region are formed. The semiconductor layer 10 and the semiconductor layer 11 are determined in consideration of appropriate layout.

  A photomask for forming the semiconductor layer 10 and the semiconductor layer 11 shown in FIG. 19A includes a mask pattern 2000 shown in FIG. The mask pattern 2000 differs depending on whether the resist used in the photolithography process is a positive type or a negative type. When a positive resist is used, the mask pattern 2000 shown in FIG. 19B is manufactured as a light shielding portion. The mask pattern 2000 has a shape obtained by deleting the top A of the polygon. The photomask pattern is chamfered so as to cut out a right triangle having a side of 10 μm or less at a corner, for example. Further, the bent portion B has a shape that bends so that the corner portion does not become a right angle. When the bend B is enlarged, the shape is bent over a plurality of steps.

  The shape of the mask pattern 2000 shown in FIG. 19B is reflected in the semiconductor layers 10 and 11 shown in FIG. In that case, a shape similar to the mask pattern 2000 may be transferred, but it may be transferred so that the corners of the mask pattern 2000 are further rounded. That is, you may provide the round part which made the pattern shape smoother than the mask pattern 2000 further.

  An insulating layer containing at least part of silicon oxide or silicon nitride is formed over the semiconductor layer 10 and the semiconductor layer 11. One purpose of forming this insulating layer is a gate insulating layer. Then, as illustrated in FIG. 20A, the gate wiring 12, the gate wiring 13, and the gate wiring 14 are formed so as to partially overlap the semiconductor layer. The gate wiring 12 is formed corresponding to the semiconductor layer 10. The gate wiring 13 is formed corresponding to the semiconductor layer 10 and the semiconductor layer 11. The gate wiring 14 is formed corresponding to the semiconductor layer 10 and the semiconductor layer 11. For the gate wiring, a metal layer or a highly conductive semiconductor layer is formed, and its shape is formed on the insulating layer by a photolithography technique.

  A photomask for forming this gate wiring is provided with a mask pattern 2100 shown in FIG. This mask pattern 2100 is each corner portion bent in an L shape, and one side of a right triangle is 10 μm or less, or 1/2 or less of the line width of the wiring and has a size of 1/5 or more of the line width. Remove the corners and give the corners a rounded pattern. That is, the outer periphery of the mask pattern 2100 at the corner portion viewed from the upper surface forms a curve. Specifically, in order to round the outer peripheral edge of the corner portion, two first straight lines that are perpendicular to each other across the corner portion and one second straight line that forms an angle of about 45 degrees with the two first straight lines. Then, a part of the mask pattern 2100 corresponding to the isosceles right triangle formed by the step is removed. When removed, two obtuse angle portions are newly formed in the mask pattern 2100. By appropriately setting the mask design and etching conditions, each obtuse angle portion has a curve in contact with both the first line and the second line. The mask pattern 2100 is preferably etched so as to be formed. The length of two equal sides of the right-angled isosceles triangle is set to 1/5 or more and 1/2 or less of the wiring width. Also, the inner periphery of the corner portion is formed so that the inner periphery is rounded along the outer periphery of the corner portion. The shape of the mask pattern 2100 illustrated in FIG. 20B is reflected in the gate wiring 12, the gate wiring 13, and the gate wiring 14 illustrated in FIG. In that case, a shape similar to the mask pattern 2100 may be transferred, or the corner of the mask pattern 2100 may be transferred so as to be further rounded. That is, a rounded portion having a smoother pattern shape than the mask pattern 2100 may be provided. That is, the corners of the gate wiring 12, the gate wiring 13, and the gate wiring 14 are rounded at the corners that are 1/2 or less of the line width and 1/5 or more. The convex part suppresses the generation of fine powder due to abnormal discharge during dry etching by plasma, and the concave part significantly improves the yield as a result of washing away the fine powder generated at the time of cleaning, which tends to collect at the corner. It has the effect that it can be expected.

  The interlayer insulating layer is a layer formed next to the gate wiring 12, the gate wiring 13, and the gate wiring 14. The interlayer insulating layer is formed using an inorganic insulating material such as silicon oxide or an organic insulating material such as polyimide or acrylic resin. An insulating layer such as silicon nitride or silicon nitride oxide may be interposed between the interlayer insulating layer and the gate wiring 12, the gate wiring 13, and the gate wiring 14. An insulating layer such as silicon nitride or silicon nitride oxide may be provided over the interlayer insulating layer. This insulating layer can prevent the semiconductor layer and the gate insulating layer from being contaminated by impurities that are not good for the TFT, such as exogenous metal ions and moisture.

  An opening is formed at a predetermined position in the interlayer insulating layer. For example, it is provided corresponding to the gate wiring or semiconductor layer in the lower layer. A wiring layer formed of one or more layers of metal or metal compound is formed with a mask pattern by a photolithography technique and formed into a predetermined pattern by etching. Then, as illustrated in FIG. 21A, the wiring 15, the wiring 16, the wiring 17, the wiring 18, the wiring 19, and the wiring 20 are formed so as to partially overlap the semiconductor layer 10 and the semiconductor layer 11. A wiring connects between specific elements. The wiring does not connect a specific element with a straight line, but includes a bent portion due to layout restrictions. In addition, the wiring width changes in the contact portion and other regions. In the contact portion, when the contact hole is equal to or larger than the wiring width, the wiring width is changed to widen at that portion.

  A photomask for forming the wirings 15 to 20 includes a mask pattern 2200 shown in FIG. Also in this case, the wiring is a corner portion bent in an L shape, and one side of a right triangle is 10 μm or less, or 1/2 or less of the line width of the wiring and has a length of 1/5 or more of the line width. Remove the corners and give the corners a rounded pattern. That is, the outer periphery of the wiring at the corner portion viewed from the upper surface forms a curve. Specifically, in order to round the outer peripheral edge of the corner portion, two first straight lines that are perpendicular to each other sandwiching the corner portion, and one second straight line that forms an angle of about 45 degrees with the two first straight lines. Then, a part of the wiring corresponding to the right isosceles triangular portion formed by is removed. When removed, two obtuse angle parts are newly formed on the wiring. By appropriately setting the mask design and etching conditions, a curve that touches both the first straight line and the second straight line is formed at each obtuse angle part. It is preferable to etch the wiring so that the The length of two equal sides of the right-angled isosceles triangle is set to 1/5 or more and 1/2 or less of the wiring width. Also, the inner periphery of the corner portion is formed so that the inner periphery is rounded along the outer periphery of the corner portion. In such wiring, the convex part suppresses the generation of fine powder due to abnormal discharge during dry etching by plasma, and the concave part is washed away even if it is fine powder produced at the time of cleaning. As a result, the yield can be expected to be greatly improved. It can be expected that the corner portion of the wiring is electrically conducted by taking a round. In addition, a large number of parallel wires are very convenient for washing away dust.

  FIG. 21A shows an N-channel transistor 21, an N-channel transistor 22, an N-channel transistor 23, an N-channel transistor 24, a P-channel transistor 25, and a P-channel transistor 26. Is formed. The N-channel transistor 23 and the P-channel transistor 25, and the N-channel transistor 24 and the P-channel transistor 26 constitute an inverter 27 and an inverter 28, respectively. The circuit including these six transistors forms an SRAM. An insulating layer such as silicon nitride or silicon oxide may be formed over these transistors.

  This embodiment can be freely combined with the above embodiment mode and Embodiments 1 to 3.

  One embodiment of the semiconductor device of the present invention is shown in FIG. 22A is a development view of the semiconductor device, and FIG. 22B is a cross-sectional view taken along line AB of FIG. 22A. In this embodiment, a structure of a semiconductor device including a plurality of antennas, particularly an antenna formed over a layer including a thin film transistor and a patch antenna will be described.

  In a manner similar to the method for manufacturing the element group 601 described in Embodiment 1, a layer 7102 including a thin film transistor is formed over the insulating substrate 7101. An interlayer insulating layer 7182 is formed over the layer 7102 having a thin film transistor. A first antenna 7181 is formed over the interlayer insulating layer 7182. An insulating layer 7183 is formed over the first antenna 7181, and a connection terminal 7184 is formed on the surface of the insulating layer 7183.

  An insulating layer 7183 in which the connection terminal 7184 is partially exposed and a patch antenna 7103 which is a second antenna are fixed by an anisotropic conductive adhesive 7104. Further, the connection terminal 7184 and the power supply layer 7113 of the patch antenna are electrically connected with conductive particles dispersed in the anisotropic conductive adhesive. The connection terminal 7184 and the first thin film transistor 7185 formed in the thin film transistor layer 7102 are electrically connected. In addition, the second thin film transistor 7186 formed in the layer 7102 having a thin film transistor is connected to the first antenna 7181. Note that a conductive layer obtained by curing a conductive paste may be used instead of the anisotropic conductive adhesive.

  The first antenna 7181 is formed using a metal material containing aluminum, copper, or silver. For example, a copper or silver paste composition can be formed by screen printing, offset printing, or an ink jet printing method. Alternatively, an aluminum film may be formed by sputtering or the like and formed by etching. In addition, you may form using an electroplating method and an electroless-plating method.

  The patch antenna 7103 includes a dielectric layer 7110, a first conductive layer 7111 formed on one surface of the dielectric layer, and faces the first conductive layer 7111 with the dielectric layer interposed therebetween. A second conductive layer 7112 and a power feeding layer 7113 are formed on the other surface. The first conductive layer 7111 functions as a reflector. The second conductive layer 7112 functions as a grounding body. The power feeding layer 7113 is provided so as not to contact the first conductive layer 7111 and the second conductive layer 7112.

  Note that the first antenna 7181 can be omitted.

  Here, the shape of the first antenna 7181 is a rectangular coil shape as shown in FIG.

  The shape of the first antenna 7181 will be described with reference to FIG. FIG. 23 is a top view showing the interlayer insulating layer 7182 and the antenna formed thereon. In this embodiment, as shown in FIGS. 22A and 23A, the first antenna 7181 has a rectangular coil shape 7181a, but is not limited to this shape. It may be a circular coil. Further, as shown in FIG. 23B, a square loop 7181b antenna can be obtained. Moreover, it can be set as a circular loop antenna. Further, as shown in FIG. 23C, a linear dipole-shaped antenna 7181c can be obtained. Moreover, it can be set as a curved dipole antenna.

  By providing a plurality of antennas in this manner, a multiband-compatible semiconductor device capable of receiving a large number of radio waves with one semiconductor device can be formed.

  This embodiment can be freely combined with the above embodiment mode and Embodiments 1 to 4.

  In this embodiment, an application of the semiconductor device of the present invention (corresponding to the wireless chip 1000 in FIG. 10) will be described with reference to FIGS. The wireless chip 1000 includes, for example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident card, etc., see FIG. 16A), packaging containers (wrapping paper, bottles, etc. (B)), DVD software, recording media such as CDs and video tapes (see FIG. 16C), vehicles such as cars, motorcycles and bicycles (see FIG. 16D), personal belongings such as bags and glasses It can be used in a product (see FIG. 16E), food, clothing, daily necessities, electronic equipment, or the like. Electronic devices refer to liquid crystal display devices, EL (electroluminescence) display devices, television devices (also simply referred to as televisions or television receivers), cellular phones, and the like.

  The wireless chip 1000 can be fixed to an article by being attached to the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin. Forgery can be prevented by providing the wireless chip 1000 on bills, coins, securities, bearer bonds, certificates, and the like. Further, by providing the wireless chip 1000 in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., it is possible to improve the efficiency of inspection systems and rental store systems. . Forgery and theft can be prevented by providing the wireless chip 1000 in vehicles. Moreover, by embedding it in creatures such as animals, it is possible to easily identify individual creatures. For example, by burying a wireless tag in a living creature such as livestock, it is possible to easily identify the year of birth, sex, type, or the like.

  As described above, the wireless chip 1000 of the present invention can be provided and used for any article (including a living thing).

  The wireless chip 1000 has various advantages such as that it can transmit and receive data by wireless communication, can be processed into various shapes, and has a wide directivity and wide recognition range depending on the selected frequency. .

  Next, one mode of a system using the wireless chip 1000 is described with reference to FIG. A reader / writer 9520 is provided on the side surface of the portable terminal including the display portion 9521, the semiconductor device 9523 of the present invention (the wireless chip 1000 in FIG. 10) is provided on the side surface of the article A 9522, and the upper surface of the article B 9532 A semiconductor device 9531 of the present invention is provided (see FIG. 15A). When the reader / writer 9520 is held over the semiconductor device 9523 included in the article A 9522, information about the article such as the raw material and origin of the article A 9522, the inspection result for each production process, the history of distribution process, and the explanation of the article is displayed on the display unit 9521. The When the reader / writer 9520 is held over the semiconductor device 9531 included in the article B 9532, information on the product such as the raw material and the place of origin of the article B 9532, the inspection result for each production process, the history of the distribution process, and the description of the product is displayed on the display unit 9521. The

  An example of a business model using the system shown in FIG. The flowchart in FIG. 15B is used for the description. In the portable terminal, allergy information is input (step 1). The allergy information is information on pharmaceuticals or components thereof that cause a predetermined person to cause an allergic reaction. Information on the article A 9522 is acquired as described above by the reader / writer 9520 provided in the portable terminal (step 2). Here, it is assumed that the article A 9522 is a medicine. Information on the article A 9522 includes information such as a component of the article A 9522. The allergy information is compared with the information such as the component of the acquired article A9522 to determine whether or not they match (step 3). If they match, it is determined that the predetermined person has a risk of causing an allergic reaction to the article A, and the user of the portable terminal is cautioned (step 4). If they do not match, it is determined that the predetermined person is less likely to cause an allergic reaction to the article A, and the user of the portable terminal is notified of this fact (safe) (step 5). In step 4 or step 5, the method of notifying the user of the mobile terminal of information may be a method of displaying on the display unit 9521 of the mobile terminal or a method of sounding an alarm of the mobile terminal. .

  As another example of the business model, information on a combination of dangerous drugs that are used at the same time or a combination of ingredients that are dangerous when used at the same time (hereinafter referred to as combination information) is input to the terminal (step 1). Information on the article A is acquired by the reader / writer provided in the terminal as described above (step 2). Here, it is assumed that the article A is a medicine. The information on the article A includes information such as the components of the article A. Next, the information of the article B is acquired as described above by the reader / writer provided in the terminal (step 2 '). Here, it is assumed that the article B is also a medicine. The information on the article B includes information such as the component of the article B. Thus, information on a plurality of medicines is acquired. The combination information is compared with the acquired information of the plurality of articles, and it is determined whether or not they match, that is, whether or not there is a combination of components of pharmaceuticals that are dangerous when used at the same time (step 3). If they match, the terminal user is alerted (step 4). If they do not match, the terminal user is informed of that fact (safe) (step 5). In step 4 or step 5, the method of notifying the user of the terminal may be a method of displaying on the display unit of the terminal, or a method of sounding an alarm of the portable terminal.

  In this manner, by utilizing the semiconductor device of the present invention for the system, information can be easily acquired, and a system that realizes high functionality and high added value can be provided.

  This embodiment can be freely combined with the above embodiment mode and Embodiments 1 to 5.

  In this embodiment, an example different from the example shown in Embodiment 6 of the system using the wireless chip 1000 will be described.

  For example, a membership card with a wireless chip 1000 is distributed, and the wireless chip 1000 is also attached to products arranged in the store. Assume that a customer has a membership card with a wireless chip 1000 and at the same time carries a product with the wireless chip 1000 and walks in the store. A plurality of readers / writers arranged in the store communicate with the two wireless chips 1000 and acquire information held by the two wireless chips 1000. In this way, optimal information is provided to the customer for the combination of information of the two wireless chips 1000.

  The provision of information is not limited by audio or video. Further, the number of wireless chips to communicate with is not limited to two.

  For example, when a customer has multiple patterns of purchasing products, it is possible to incentivize purchasing by inferring the products to be purchased from information that has one or more products and providing information. .

  By grasping the patrol pattern of customers from a plurality of readers / writers installed in the store, information can be provided according to the location in the store.

  For a certain person (thing), the thing (person) with the wireless chip becomes the key (condition), or the time / place information becomes the key (condition), and the reader / writer responds in various ways. The best service can be performed.

  In this manner, by utilizing the semiconductor device of the present invention for the system, information can be easily acquired, and a system that realizes high functionality and high added value can be provided.

  This embodiment can be freely combined with the above embodiment modes and Embodiments 1 to 6.

FIG. 3 illustrates a configuration of Embodiment 1; FIG. 6 illustrates a configuration of a second embodiment. FIG. 6 illustrates a configuration of a third embodiment. FIG. 6 illustrates a configuration of a fourth embodiment. FIG. 10 shows a configuration of a sixth embodiment. FIG. 6 shows Embodiment 5. FIG. 6 shows Embodiment 5. FIG. 10 shows a structure of a seventh embodiment. FIG. 10 shows a configuration of an eighth embodiment. FIG. 10 shows a structure of Embodiment 9; FIG. 3 is a diagram illustrating Example 1; FIG. 3 is a diagram illustrating Example 1; FIG. 3 is a diagram illustrating Example 1; FIG. FIG. 6 shows a sixth embodiment. FIG. 6 shows a sixth embodiment. FIG. FIG. FIG. FIG. FIG. FIG. 6 shows a fifth embodiment. FIG. 6 shows a fifth embodiment.

Explanation of symbols

10 semiconductor layer 11 semiconductor layer 12 gate wiring 13 gate wiring 14 gate wiring 15 wiring 16 wiring 17 wiring 18 wiring 19 wiring 20 wiring 21 N-channel transistor 22 N-channel transistor 23 N-channel transistor 24 N-channel transistor 24 Transistor 25 P-channel transistor 26 P-channel transistor 27 Inverter 28 Inverter 101 P-channel transistor 102 P-channel transistor 103 P-channel transistor 104 P-channel transistor 105 P-channel transistor 111 Phase comparison 112 Loop filter 113 VCO circuit 114 Frequency divider 115 PLL circuit 131 P channel transistor 132 P channel transistor 133 P channel Transistor 134 P-channel transistor 135 P-channel transistor 141 N-channel transistor 142 N-channel transistor 143 N-channel transistor 144 N-channel transistor 145 N-channel transistor 151 N-channel transistor 152 N-channel transistor 153 N-channel transistor 154 N-channel transistor 155 N-channel transistor 161 P-channel transistor 162 P-channel transistor 163 P-channel transistor 164 P-channel transistor 165 P N-channel transistor 171 N-channel transistor 172 N-channel transistor 173 N-channel transistor 174 N-channel transistor 175 N-channel transistor 181 First stage 182 Second stage 183 Third stage 184 Fourth stage 185 Fifth stage 201 Oscillation circuit 202 Circuit 203 Circuit 204 Control unit 205 Adjustment circuit 206 Current source unit 207 Voltage controlled current source 301 Third transistor 302 First transistor 303 Second transistor 311 Fourth transistor 312 Fifth transistor 401 Fifth transistor 402 Fourth transistor 403 Second transistor 411 First transistor 412 Third transistor 421 Seventh transistor 422 Sixth transistor 500 Monitor circuit 501 P-channel transistor 502 N-channel transistor 511 P-channel transistor 512 N-channel Type transistor 600 Substrate 601 Element group 602 Terminal portion 603 Conductive particle 604 Resin 610 Substrate 661 Underlayer 662 Semiconductor layer 662a Channel formation region 662b Impurity region 662c Low-concentration impurity region 663 First insulating layer 664 Gate electrode 665 Third Insulating layer 666 Wiring 667 Second insulating layer 668 Fourth insulating layer 701 Flexible substrate 901 Protective layer 902 Antenna 903 Protective layer 904 Element group 905 One of source and drain 906 The other of source and drain 907 Gate electrode 980 Substrate 981 Transistor 1000 Wireless chip 1001 Antenna 1002 Bandpass filter 1003 Power supply circuit 1004 Demodulation circuit 1005 Modulation circuit 1006 PLL circuit 1007 Code recognition and determination circuit 1008 Memory 1009 Coding circuit 120 a corner 1201b of conventional wiring a corner 1201c of conventional wiring b corner 1202a of conventional wiring c corner 1202b of wiring a of the present invention corner 1202c of wiring b of the present invention corner of wiring c of the present invention Part 2000 Mask pattern 2001 N-channel transistor 2002 N-channel transistor 2003 P-channel transistor 2004 Capacitor element 2005 Resistor element 2100 Mask pattern 2200 Mask pattern 4402 Second conductive layer 4403 First conductive layer 4404 Wiring 4405 Semiconductor layer 4406 Impurity region 4407 Impurity region 4408 Insulating layer 4409 Gate electrode 4410 Impurity region 4411 Impurity region 4412 Impurity region 7101 Insulating substrate 7102 Layer 7103 Patch antenna 7104 Anisotropic conductive adhesive 7110 Dielectric layer 7 11 First conductive layer 7112 Second conductive layer 7113 Feeder layer 7181 First antenna 7181a Square coil shape 7181b Square loop shape 7181c Linear dipole shape 7182 Interlayer insulating layer 7183 Insulating layer 7184 Connection terminal 7185 First thin film transistor 7186 Second thin film transistor 9520 Reader / writer 9521 Display portion 9522 Article A
9523 Semiconductor device 9531 Semiconductor device 9532 Article B

Claims (16)

A control unit that outputs a second voltage corresponding to the first voltage by inputting the first voltage;
A current source unit that outputs a current corresponding to the second voltage by inputting the second voltage;
An oscillation circuit that outputs a signal having a frequency corresponding to the current when the current is input;
The control unit has an adjustment circuit;
The voltage control oscillation circuit, wherein the adjustment circuit changes the second voltage in accordance with a change in power supply voltage. In claim 1,
The voltage-controlled oscillation circuit, wherein the adjustment circuit decreases the second voltage when the power supply voltage increases, and increases the second voltage when the power supply voltage decreases. In claim 1 or claim 2,
The control unit includes a first transistor, a second transistor, and a third transistor connected in series to the first transistor,
The adjustment circuit includes the second transistor;
The third transistor is diode-connected;
The drain current of the third transistor is the sum of the drain current of the first transistor and the drain current of the second transistor,
The first voltage is input to the gate of the first transistor;
The second voltage is output from the drain of the first transistor,
A third voltage is input to the gate of the second transistor,
The voltage controlled oscillation circuit, wherein the third voltage changes in accordance with a change in the power supply voltage. In claim 3,
The voltage-controlled oscillation circuit, wherein the second transistor constitutes a constant current source that allows a constant current to flow according to the third voltage. In claim 3 or claim 4,
Both the first transistor and the second transistor are N-channel transistors,
3. The voltage controlled oscillation circuit according to claim 1, wherein when the power supply voltage increases, the third voltage decreases, and when the power supply voltage decreases, the third voltage increases. In claim 3 or claim 4,
The third voltage changes to decrease the drain current of the second transistor when the power supply voltage increases, and changes to increase the drain current of the second transistor when the power supply voltage decreases. A voltage-controlled oscillation circuit characterized by that. In any one of Claims 3 thru | or 6,
A voltage controlled oscillation circuit, wherein a current gain of the voltage controlled oscillation circuit is adjusted by changing a ratio of a drain current of the second transistor to a drain current of the first transistor. In claim 1,
The control unit is connected in series with the first transistor, the second transistor, the third transistor connected in series with the first transistor, the fourth transistor, and the fourth transistor. A fifth transistor,
The adjustment circuit includes the second transistor;
The third transistor is diode-connected;
The fifth transistor is diode-connected;
The first transistor and the fifth transistor constitute a current mirror circuit,
The drain current of the third transistor is the sum of the drain current of the first transistor and the drain current of the second transistor,
The first voltage is input to the gate of the fourth transistor,
The second voltage is output from the drain of the first transistor,
A third voltage is input to the gate of the second transistor,
The voltage-controlled oscillation circuit, wherein the third voltage changes in conjunction with fluctuations in the power supply voltage. In claim 8,
The voltage-controlled oscillation circuit, wherein the second transistor constitutes a constant current source that allows a constant current to flow according to the third voltage. In claim 8 or claim 9,
The first transistor and the second transistor are both P-channel transistors,
3. The voltage controlled oscillation circuit according to claim 1, wherein the third voltage increases when the power supply voltage increases, and the third voltage decreases when the power supply voltage decreases. In claim 8 or claim 9,
The third voltage changes to decrease the drain current of the second transistor when the power supply voltage increases, and changes to increase the drain current of the second transistor when the power supply voltage decreases. A voltage-controlled oscillation circuit characterized by that. In any one of Claims 8 thru | or 11,
A voltage controlled oscillation circuit, wherein a current gain of the voltage controlled oscillation circuit is adjusted by changing a ratio of a drain current of the second transistor to a drain current of the first transistor.   A phase-locked loop circuit using the voltage-controlled oscillation circuit according to claim 1. The voltage controlled oscillation circuit according to any one of claims 1 to 12, a frequency divider, a phase comparator, and a loop filter,
The phase comparator receives a reference signal and the output of the divider,
Output the phase difference between the reference signal and the output signal of the divider,
The output of the phase comparator is input to the loop filter, and the noise of the input signal is removed and output.
The voltage-controlled oscillation circuit receives an output signal of the loop filter,
An output of the voltage controlled oscillation circuit is input to the frequency divider, and the frequency of the input signal is multiplied by 1 / N (N is an arbitrary natural number), and the phase locked loop circuit is output. .   A semiconductor device comprising the phase-locked loop circuit according to claim 14.   16. The semiconductor device according to claim 15, wherein the semiconductor device is a wireless chip that transmits and receives information wirelessly, a mobile phone, a cordless phone, or a wireless LAN.

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