JPH0661801A - Oscillator - Google Patents

Abstract

PURPOSE:To obtain an oscillator whose oscillating frequency is independent of a power supply voltage. CONSTITUTION:An amplitude of an output signal of an inverter comprising transistors(TRs) Q9, Q10 is controlled by TRs Q7, Q9 in a 1st delay circuit C1. An output current of the said inverter is controlled by TRs Q5, Q6. A change in a signal delay time due to a change in an output current of the inverter attended with a voltage fluctuation of a power supply 1 is cancelled by varying a gate voltage of the TRs Q9, Q10 in response to a power supply voltage. Thus, the signal delay time of delay circuits C1-C7 is kept constant independently of the fluctuation of the power supply voltage to reduce the voltage dependency of the oscillating frequency of the ring oscillator.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator formed by connecting inverters in multiple stages, and more particularly to an oscillator in which the power supply voltage dependence of the oscillation frequency is reduced.

[0002]

2. Description of the Related Art Generally, an internal operation clock of an LSI is often generated by using an external crystal oscillator. However, if the on-chip oscillator has sufficient accuracy and the required accuracy is satisfied, it is advantageous to use the on-chip oscillator in terms of cost and mounting density.

FIG. 3 is a diagram showing a conventional on-chip oscillator. In the figure, 1 is a power supply, 2 is ground, 3 is a constant voltage source for outputting a reference voltage V1, A1 is an operational amplifier for inputting the reference voltage V1 to a non-inverting input terminal, 4 is one end grounded, and the other end is A resistor connected to the inverting input terminal of the operational amplifier A1, Q1 is an NMOS transistor whose source is connected to one end of the resistor 4 and whose output receives the output of the operational amplifier A1. Constant voltage source 3, operational amplifier A1, resistor 4 and N
This part composed of the MOS transistor Q1 is NM
A constant current I passes through the OS transistor Q1 and the resistor 4.
It works as a constant current source that flows 1.

The source of the Q2 is connected to the power source 1, and the NMOS
The drain of the transistor Q1 is connected to the gate and drain of the PMOS transistor, and the source Q3 is connected to the power source 1, and the gate of the PMOS transistor Q2 is connected to the gate of the PMOS transistor. The PMOS transistors Q2 and Q3 form a current mirror circuit. Therefore, a current I2 having the same magnitude as the current I1 flowing through the PMOS transistor Q2 is generated.
It also flows between the source and gate of 3.

Q4 has a source connected to ground 2 and a PMOS
This is an NMOS transistor in which the gate and drain are connected to the drain of the transistor Q3. Q6 is an NMOS transistor whose source is connected to the ground 2 and whose gate is connected to the gate of the NMOS transistor Q4. And
The gate-source voltage of the NMOS transistor Q4 determined by the current I2 is applied to the gate of the NMOS transistor Q6 as a bias voltage. Q5 is a PMOS transistor whose source is connected to the power supply 1 and whose gate is connected to the gate of the PMOS transistor Q2. And
The gate-source voltage of the PMOS transistor Q2 determined by the current I1 is applied to the gate of the PMOS transistor Q5 as a bias voltage.

Q7 is a node N1 in which the source is connected to the drain of the PMOS transistor Q5, the drain is connected to the ground 2, and the potential V _DD / 2 which is between the power supply potential V _DD and the ground potential GND is input to the gate. It is a transistor. The potential of the node N1 is given by the PMOS transistor Q7 and has a value obtained by adding the gate-source voltage of the PMOS transistor Q7 to the gate potential of the PMOS transistor Q7. Also, at node N2, Q8 is an NMOS
Connect the source to the drain of transistor Q6
Is an NMOS transistor in which the drain is connected to and a potential V _DD / 2 intermediate between the power supply potential V _DD and the ground potential GND is input to the gate. The potential of the node N2 is given by the NMOS transistor Q8,
It has a value obtained by adding the gate-source voltage of the NMOS transistor Q8 to the gate potential of.

Q9 is a PM whose source is connected to the node N1.
It is an OS transistor. Q10 is an NMOS transistor in which the source is connected to the node N2, the gate is connected to the gate of the PMOS transistor Q9, and the drain is connected to the drain of the PMOS transistor Q9. PMOS
The transistor Q9 and the NMOS transistor Q10 form an inverter. The PMOS transistor Q5 and the NMOS transistor Q6 are transistors for controlling the drain currents of the transistors Q9 and Q10 that form the inverter. The PMOS transistor Q7 and the NMOS transistor Q8 are transistors for controlling the amplitude of the inverter formed by the transistors Q9 and Q10.

C1 is a first delay circuit composed of transistors Q5 to Q10. C2 to C7 are second to seventh delay circuits having the same configuration as the first delay circuit C1.
~ The seventh delay circuits C1 to C7 are connected in series to form a ring oscillator.

Next, the operation will be described. The oscillation frequency of the ring oscillator including the first to seventh delay circuits C1 to C7 is the input capacitance of each of the delay circuits C1 to C7 and the delay circuit C1.
Of the PMOS transistor Q5 and the NMOS transistor Q6, which flow the bias currents I3 and I4, and the delay circuits C2 to C7 equivalent to the transistors Q5 and Q6.
Is determined by the driving force of the transistor, the amplitude of the inverter of each delay circuit C1 to C7, and the like. Of these, the bias current largely depends on the power supply voltage.

First, the input signal I to the first delay circuit C1
When N changes from “H” to “L”, the PMOS transistor Q9 turns on and the current I3 changes to the PMOS transistor 1
Through 0 to the input of the second delay circuit C2. The current I3 charges the input capacitance of the second delay circuit, and the potential of the output terminal of the first delay circuit rises. The potential of the output terminal is equal to the potential of the node N1, and when the potential of the node N1 becomes higher than the potential of the gate of the PMOS transistor Q7 and exceeds the threshold voltage of the PMOS transistor Q7, the PMOS transistor Q7 turns on. And PMOS
When the transistor Q7 turns on, the current I3 is all PMO
Since it flows through the S transistor Q7, the potential of the node N1 no longer rises, that is, the output voltage of the inverter does not rise above that value.

Next, the input signal IN to the first delay circuit C1
Is changed from "L" to "H", the NMOS transistor Q10 is turned on and the current I4 changes to the NMOS transistor Q.
It flows out from the input of the second delay circuit C2 through 10.
This current I4 discharges the input capacitance of the second delay circuit and lowers the potential of the output terminal of the first delay circuit. The potential of the output terminal is equal to the potential of the node N2, the potential of the node N2 becomes lower than the gate potential of the NMOS transistor Q8, and when the threshold voltage of the NMOS transistor Q8 is exceeded, the NMOS transistor Q8 turns on. And NMO
When the S transistor Q8 is turned on, the current I4 is all NMO.
It flows from the power supply 1 through the S-transistor Q8, and the potential of the node N2 does not drop further, that is, the output voltage of the inverter does not fall below that value.

As described above, the amplitude of the inverter is PMOS
It is a value obtained by adjusting the threshold voltages of the PMOS transistor Q7 and the NMOS transistor Q8 around V _DD / 2 which is the gate potential of the transistor Q7 and the NMOS transistor Q8. Therefore, the transistors Q7 and Q8
It is determined by the gate-source voltage of and is constant regardless of the power supply voltage.

On the other hand, the PMOS transistors Q5 and NM
The OS transistor Q6 controls the bias currents I3 and I4, but when the voltage of the power supply 1 changes, the transistor Q6
Since the source-drain voltage of Q5 and Q6 changes, the bias currents I3 and I4 change. For example, when the bias current becomes large, the time to charge the input capacitance of the next stage becomes short, and the signal delay time of each delay circuit C1 to C7 becomes long,
The oscillation frequency of the oscillator becomes high. This state is shown in FIG. As shown in FIG. 4, although there is some variation depending on the value of the reference voltage V1, the oscillation frequency also increases to 200 to 350 MHz as the power supply voltage V _DD increases to 2 to 4V.

[0014]

Since the conventional oscillator is constructed as described above, there is a problem that the oscillation frequency fluctuates with the fluctuation of the power supply voltage.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain an oscillator whose oscillation frequency is constant even if the power supply voltage changes.

[0016]

An oscillator according to the present invention is connected to a bias voltage generating circuit for inputting a reference voltage and outputting first and second bias voltages, and the bias voltage generating circuit. , A plurality of delay circuits connected in a ring shape and operated by the first and second bias voltages, each delay circuit having one electrode connected to a first power supply and being connected to the bias voltage generating circuit. A first transistor for connecting a control electrode to input the first bias voltage to the control electrode, one electrode connected to the other electrode of the first transistor, and the other electrode connected to a second power supply. A third transistor is connected to the second transistor and the second power source, and the control electrode is connected to the bias voltage generating circuit to input the second bias voltage to the control electrode. A fourth transistor in which one electrode is connected to the other electrode of the third transistor and the other electrode is connected to the first power supply, and the other electrode of the first transistor and the third transistor are connected. An inverter connected to the other electrode and using the potential difference between the other electrodes of the first and third transistors as an operating voltage, and dividing the potential difference between the first and second power supplies to different potentials. Are applied to the control electrodes of the second and fourth transistors, respectively.

[0017]

In the second and fourth transistors of the present invention, since the potential difference between the first and second power supplies is divided and different potentials are given to each, the potential difference between the first and second power supplies is reduced. When changed, the difference between the respective control electrode potentials changes according to the change in the potential difference between the first and second power supplies.
On the other hand, the output currents of the first and third transistors change as the potential difference between the first and second power supplies changes. First
And the first and the third with the variation of the potential difference between the second and the second power supplies.
When the output current of the first transistor changes, the difference between the control electrode potentials of the second and fourth transistors is changed to change the amplitude of the inverter, and the influence of the change of the output currents of the first and third transistors is affected. It can be canceled so that the signal delay time of the delay circuit does not change.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, R1 is a resistor having one end connected to the power supply 1, R2 is a resistor having one end connected to the other end of the resistor R1 at a node N3, and R3 is one resistor connected to the other end of the resistor R2 at a node N4. It is resistance. Other reference numerals that are the same as those in FIG. 3 indicate the same or corresponding portions as in FIG. The gates of the PMOS transistors Q and 7 of the first delay circuit C1 are connected to the node N4. Also, NMOS transistor Q8
Has its gate connected to the node N3. Therefore, P
The gate voltage of the MOS transistor Q7 is resistors R2 and R3.
And the gate voltage of the NMOS transistor Q8 depends on the value of the resistor R3.

For example, assume that the ratio of the resistance values of the resistors R1 to R3 is 9: 2: 9. When the power supply voltage V _DD is 4V, the voltage between the ground 2 and the node 3 is 2.2V, and the voltage between the ground 2 and the node 4 is 1.8V. When the threshold voltage of the transistors Q7 and Q8 is 0.7V, the inverter amplitude is 1.8V _PP . And the power supply voltage V
_{When DD} reaches 2V, the voltage between ground 2 and node 3 is 1.
1V, voltage between ground 2 and node 4 is 0.9V
Therefore, the amplitude of the inverter becomes as small as 1.6 V _PP . By reducing the amplitude of the inverter, the bias currents I3 and I4 are reduced, the delay time of the delay circuit is lengthened, and the oscillation frequency is prevented from lowering. FIG. 2 is a graph showing the power supply voltage dependence of the oscillation frequency when the resistance ratio of the resistors R1 to R3 is set to 9: 2: 9.

By selecting a resistance ratio such that the oscillation frequency does not depend on the power supply voltage _VDD as shown in FIG. 2 by simulation or the like, an oscillator having a stable oscillation frequency can be obtained even if the power supply voltage changes.

In the above embodiment, the oscillator was constructed using MOS transistors, but the transistors are MOS transistors.
Not only the transistor but also another transistor may be used, and the same effect as that of the above-described embodiment is obtained. Further, in the above-mentioned embodiment, the inverter is composed of the CMOS, but the inverter may have another structure, and the same effect as that of the above-mentioned embodiment is obtained.

[0022]

As described above, according to the oscillator of the invention, each delay circuit has the second electrode in which the other electrode of the first transistor is connected to the other electrode and the second electrode is connected to the other electrode. And a fourth transistor in which one electrode is connected to the other electrode of the third transistor and the other electrode is connected to the first power source, and the first and second transistors are provided.
The potential difference between the power supplies of the
And the control electrode of the fourth transistor, the signal delay time of the delay circuit can be kept constant irrespective of the first and second power supply voltages, and the oscillation frequency of the oscillator is highly dependent on the power supply voltage. The effect is that it can be made smaller.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an oscillator according to an embodiment of the present invention.

FIG. 2 is a diagram showing the power supply voltage dependency of the oscillation frequency of the oscillator shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a conventional oscillator.

FIG. 4 is a diagram showing a power supply voltage dependency of an oscillation frequency of a conventional oscillator.

[Explanation of symbols]

 1 Power Supply 2 Grounding 3 Constant Voltage Source 4 Resistance A1 Operational Amplifier Q1 to Q10 Transistors R1 to R3 Resistance

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[Procedure amendment]

[Submission date] February 22, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

On the other hand, the PMOS transistors Q5 and NM
The OS transistor Q6 controls the bias currents I3 and I4, but when the voltage of the power supply 1 changes, the transistor Q6
Since the source-drain voltage of Q5 and Q6 changes, the bias currents I3 and I4 change. For example, when the bias current becomes large, the time for charging the input capacitance of the next stage becomes short, and the signal delay time of each delay circuit C1 to C7 becomes short ,
The oscillation frequency of the oscillator becomes high. This state is shown in FIG. As shown in FIG. 4, although there is some variation depending on the value of the reference voltage V1, the oscillation frequency also increases to 200 to 350 MHz as the power supply voltage V _DD increases to 2 to 4V.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction content]

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, R1 is a resistor having one end connected to the power supply 1, R2 is a resistor having one end connected to the other end of the resistor R1 at a node N3, and R3 is one resistor connected to the other end of the resistor R2 at a node N4. It is resistance. Other reference numerals that are the same as those in FIG. 3 indicate the same or corresponding portions as in FIG. The gate of the PMOS transistor Q7 of the first delay circuit C1 is the node N
4 is connected. The gate of the NMOS transistor Q8 is connected to the node N3. Therefore, PM
The gate voltage of the OS transistor Q7 is determined by the values of the resistors R2 and R3, and the gate voltage of the NMOS transistor Q8 is determined by the value of the resistor R3.

Claims (1)

[Claims] 1. A first voltage and a second voltage are input by inputting a reference voltage.
A bias voltage generating circuit for outputting the bias voltage of, and a plurality of delay circuits each connected to the bias voltage generating circuit, connected in a ring shape, and operated by the first and second bias voltages. The delay circuit includes a first transistor having one electrode connected to a first power supply and a control electrode connected to the bias voltage generation circuit to input the first bias voltage to the control electrode; A second transistor in which one electrode is connected to the other electrode of the transistor and the other electrode is connected to a second power source, and one electrode is connected to the second power source and a control electrode is connected to the bias voltage generating circuit. A third transistor for inputting the second bias voltage to the control electrode, and one electrode connected to the other electrode of the third transistor and the other to the first power source. A fourth transistor having an electrode connected to it is connected between the other electrode of the first transistor and the other electrode of the third transistor to operate a potential difference between the other electrodes of the first and third transistors. An oscillator having a voltage inverter, wherein the potential difference between the first and second power supplies is divided to apply different potentials to the control electrodes of the second and fourth transistors, respectively.