JP2546847B2 - Digital DLL circuit - Google Patents

Description

The present invention relates to a digital duty locked loop (DLL) that provides a polyphase output signal synchronized with an input signal.
Regarding the circuit, especially in the duty cycle guarantee in the ultra high frequency range,
The present invention relates to a digital DLL circuit that can suppress the effects of periodic fluctuations and fluctuations in element characteristics.

[Prior Art] Conventionally, a digital DLL circuit of this type has been configured to generate a multi-phase clock by dividing a sufficiently high harmonic with respect to a fundamental frequency.

[Problems to be Solved by the Invention] However, such a conventional DLL circuit is configured to generate a multi-phase clock by dividing a sufficiently high harmonic with respect to the fundamental frequency as described above. Because
There is a drawback that the frequency limit that can be processed becomes low due to the frequency limit on the circuit side that can process this harmonic and the generation limit of the harmonic.

Therefore, in view of the above-mentioned conventional drawbacks, an object of the present invention is to provide a digital DLL circuit which provides a multi-phase output signal, which is capable of guaranteeing a duty in an ultra-high frequency region and suppressing the influence of frequency variation and element characteristic variation. .

[Means for Solving Problems] In order to achieve the above object, a digital DL according to the present invention is provided.
The L circuit is (a) a divide-by-two circuit that inputs a reference clock signal with a constant period and generates a reference double period clock signal with a period twice that of this clock signal, and (b) each is a delay circuit M A delay circuit which is composed of a plurality of buffer gates, and which outputs a delayed double cycle clock signal sequentially delayed by the delay amount of the buffer gate with respect to the reference double cycle clock signal, and (c) each of the delayed double cycle clock signals. And a latch circuit composed of M flip-flops for latching with a clock signal having a phase opposite to that of the reference double cycle clock signal, and (d) inputting the reverse polarity output of the M latch outputs from these latch circuits. And a priority selection circuit that selects the youngest number K among the input signals in the active state, and (e) when this is divided into J equal parts with respect to this youngest number K. Let Ne be the number of the second division point, and select J-1 integer values that satisfy ((e · k) / J) −0.5 <Ne ≦ ((e · k) / J) +0.5, A J equal division number generation section for outputting the number of J-1 division points, and (f) a signal selection for selectively outputting the delayed double cycle clock signal for these designated J-1 division point numbers. And (g) the selected and output J−1 pieces of the delayed double cycle clock signals, the reference double cycle clock signal, and the anti-phase reference double cycle clock signal. It is composed of an exclusive OR circuit which takes an exclusive OR of double-cycle clock signals delayed by 1 / J of the basic cycle and outputs a J-phase multi-phase clock signal.

According to the digital DLL circuit of the present invention configured as described above, the reference clock signal is input to the M-stage buffer gate delay circuit, which is sequentially delayed to generate the delayed doubled clock, and these are used as the reference. To measure the input period,
Further, based on this, the priority selection circuit and the equal division control unit for J generate delay-multiplied cycle clocks delayed by 1 / J of the input basic cycle, whereby J-phase multiphase clocks having the same basic cycle can be generated. I can. Therefore, the duty of the J-phase clock can be guaranteed in the ultrahigh frequency range, and it can be followed even if the frequency of the input signal fluctuates.

[Embodiment] Next, an embodiment of a digital DLL circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a schematic circuit configuration diagram showing an embodiment of a digital DLL circuit according to the present invention.

The flip-flop 11 inputs a reference clock CI having a constant cycle to its input terminal 12, and outputs a reference double cycle clock signal Cx having a doubled cycle from its output terminal 13 to a delay circuit 14. On the other hand, the reverse-phase reference double-cycle clock signal having the opposite phase to the reference double-cycle clock signal Cx is output from the output terminal 15 to the latch circuit 16 in the subsequent stage. The other input terminal 17 of the flip-flop 11 is directly connected to the output terminal 15.

The delay circuit 14 is composed of M flip-flops and delays the reference double-cycle clock signal Cx one stage at a time to generate delay signals (C _{1 to} C _m ).
14-M, an input of the first-stage buffer gate 14-1 of this buffer gate group and an input connected to the input of the flip-flop 11 described above, and the reference double cycle clock signal Cx from the flip-flop 11 is input. A buffer gate 18 for outputting the reference double period clock signal Co to the exclusive OR (ExOR) gate 27 in the subsequent stage, and an input to the output terminal 15 of the flip-flop 11 are connected to input the reverse phase reference double period clock signal, It is composed of a buffer gate 20 which outputs this to an exclusive OR gate 27.

The latch circuit 16 receives the delay double cycle clock signals C _{1 to} C _m from the delay circuit 14 at its input terminal 20 and also receives the antiphase reference double cycle clock signal from the flip-flop 11 as a terminal.
21 and latches the delay double cycle clock signals C _{1 to} C _m ,
The reverse polarity latch output ( ₁ to _m ) is output to the priority endorder 22 in the next stage. The priority encoder 22 enters the smallest number K (E ₁ ~E _L) from the active signal to the next stage of J equal division number generating unit 23 defines, as in the following the latch output _{(1 ~ m)} . That is, the latch 16 latches at the falling point of the C ₀ signal in FIG. 2, but if the active level is set to the “H” state, C _{0 to} C _K-1 are “H” and C _{K to} C _m are to "L", the latch output is a side, Q ₀ ~Q _K-1 is "L", Q _K to Q _m becomes "H", Q _K becomes number Saiwaka. It should be noted that E _{1 to} E _L are a group of encode output signal lines of number K.

The equal division number generating unit 23 for J inputs the encoded output value (E _{1 to} E _L ) of the youngest number K and outputs the number of each division point of 1 / J, 2 / J, ..., J−1 / J. Is calculated by division to generate J-1 division point numbers. The contents to be generated at this time are such that the value of the e-th division number Ne satisfies ((e · k) / J) −0.5 <Ne ≦ ((e · k) / J) +0.5, J−1 Encoding number groups are generated.

The signal selection section 24 is composed of J-1 M-1 selectors, and each reference frequency-divided clock signal C ₁ to C ₁ to J 1 / J, 2 / J, ... It outputs _J-1 selection result signals C _{S1 to} C _{S (J-1)} from C _m .

Here, when J = 4, the selected signal output groups C _{S1 to} C
_The signal output group corresponding to _{S (J-1)} is C _{K / 4} shown in FIG.
C _{2K / 4} and C _{3K / 4} .

The exclusive OR unit 27 is composed of J exclusive OR units 27-1, 27-2, ..., 27-J, and one terminal of 27-1 of them is a reference double cycle clock signal Co.
In response, the other input terminal is connected to one terminal of the second stage 27-2, and similarly one terminal is connected to the other input terminal, and terminals 28-1, 28-2, .. 28- (J-
1) to sequentially receive the delayed doubled clock signals (C _{S1 to} C _{S (J-1)} ) from the signal selecting section 24, and further to the remaining unconnected input terminals of 27-J It receives an anti-phase reference double cycle clock signal, takes exclusive OR of these clock signals delayed by 1 / J of the basic cycle, and outputs the J-phase multi-phase clock signals CO _{1 to} CO _J at its output terminals. Output from 29-1, 29-2, ..., 29-J.

FIG. 2 is a timing diagram of clock signals in various parts of the above embodiment.

CI is a reference clock signal having a constant cycle input to the input terminal 12 of the flip-flop 11, Co is a reference frequency doubled clock signal from the buffer gate 18 of the delay circuit 14, and C _{1 to} C _m are 1 from the delay circuit 14. shows a delayed signal C ₁ -C _m which is stepped by one delay.

The latch circuit 16 of the flip-flop latches at the rising edge of the reference clock signal CI, so that the youngest number K is obtained as the priority encoded value of the output of the latch 16.

FIG. 3 is a timing chart of signals of respective parts when the partner J = 4 of the multiphase clock signal. In the figure, CI and CO are the same as the signals shown in FIG. 2, and Co is an antiphase signal of Co. In the case of the division number _{J = 4, C K / 4} , C 2K / 4, C 3K / 4 selects the signal at each division point _{of, Co, C K / 4,} C 2K / 4, C 3K / 4
It is shown that the four or more equal phase multiphase clock signals of CQ ₁ , CQ ₂ , CQ ₃ and CQ ₄ can be generated by sequentially taking the exclusive OR from each of the signals.

[Effects of the Invention] As described above, according to the present invention, a clock based on the buffer gate delay time is used to measure the input period, and the J-phase clock is generated from the result. Therefore, the following effects are obtained, which is very useful in practice.

(1) The duty of the J-phase clock can be guaranteed within the error range of 1/2 of the buffer gate delay time.

(2) It is possible to continuously follow the frequency fluctuation of the input signal.

(3) No high frequency signal input other than the input signal is required.

(4) If the delay time of M buffer gates is uniform,
It can be realized with the same circuit configuration regardless of the length of the buffer gate delay time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a digital DLL circuit of the present invention. 2 and 3 are timing charts for explaining the operation of this circuit. 11 …… Flip-flop, 14 …… Delay circuit, 16 …… Latch circuit, 22 …… Priority encoder, 23 …… J Equal division number generation section, 24 …… Signal selection section, 27 …… Exclusive OR section

Claims (1)

(57) [Claims] 1. A divide-by-2 circuit for inputting a reference clock signal having a constant period and generating a reference double period clock signal having a period twice that of the clock signal, and M buffer gates each forming a delay circuit. A delay circuit configured to output a delayed double cycle clock signal sequentially delayed by the delay amount of the buffer gate with respect to the reference double cycle clock signal; and each of the delayed double cycle clock signals as the reference double cycle clock signal. M that is latched with a clock signal of opposite phase
Number of flip-flops and a priority selection circuit that receives the reverse polarity output of M latch outputs from these latch circuits and selects the youngest number K among the input signals in the active state. Then, the number of the e-th division point when this is divided into J equal parts with respect to this youngest number K is Ne, and ((e · k) / J) −0.5 <Ne ≦ ((e · k) / J) J equal division number generation unit that selects J-1 integer values that satisfy +0.5 and outputs the number of J-1 division points, and these J-1 divisions that are designated. A signal selecting section for selectively outputting the delayed double cycle clock signal corresponding to the point number, the J-1 pieces of the delayed double cycle clock signals selectively output, the reference double cycle clock signal and the anti-phase reference double cycle. Including the clock signal, in order from the reference double cycle clock signal A digital DLL circuit comprising: an exclusive OR circuit that takes an exclusive OR of double-cycle clock signals delayed by 1 / J of this cycle and outputs a J-phase multi-phase clock signal. .