JPH05129913A - Phase comparator circuit - Google Patents

Abstract

PURPOSE:To provide the phase comparator circuit whose scale is small. CONSTITUTION:A 1st pulse signal 'IN1' inputted to a D flip-flop 1 is latched by a 2nd pulse signal 'IN2' and a 1st latch signal 'Q1' is outputted. A 1st pulse signal 'IN1' inputted to a D flip-flop 2 is latched by the inverse of the 2nd pulse signal 'IN2' and a 2nd latch signal 'Q2' is outputted. A 1st phase difference signal 'U' from an exclusive circuit 4, and a 2nd phase difference signal 'D' from an exclusive circuit 5 are respectively outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a PLL (Phase Locked).
Loop) circuit and the like for a phase comparison circuit.

[0002]

2. Description of the Related Art As a phase comparison circuit used in a PLL circuit or the like, for example, there is one described in Japanese Patent Publication No. 2-49573. FIG. 3 shows the phase comparison circuit described in that publication. According to this, the first pulse signal “IN1” (for example, EFM signal) and the second pulse signal “IN2” (for example, VCO (voltage controlled oscillator))
From the first phase difference signal (U bar) (for example, a signal for increasing the frequency of the VCO) and the second phase difference signal "D" (for example, the VCO).
Signal for lowering the frequency). The first phase difference signal "U bar" and the second phase difference signal "D" are input to the charge pump circuit, for example.

[0003]

In the above conventional circuit,
Since four D-type flip-flops are required, there is a problem that the circuit scale becomes large.

An object of the present invention is to provide a phase comparison circuit having a small circuit scale.

[0005]

A phase comparison circuit according to the present invention comprises a first latch circuit for latching a first pulse signal using a second pulse signal as a clock signal and outputting the first latch signal, and a second pulse signal for the second pulse signal. A second latch circuit that latches the first latch signal and outputs the second latch signal by using the inverted signal as a clock signal, and a first phase difference signal that is generated by exclusive OR of the first pulse signal and the first latch signal. It is characterized by having one logic circuit and a second logic circuit which generates a second phase difference signal by an exclusive OR of the first latch signal and the second latch signal.

[0006]

EXAMPLE FIG. 1 is an electric circuit diagram showing an example,
3 illustrates a phase comparison circuit used in a PLL circuit or the like.

The D-type flip-flop 1 constitutes a first latch circuit, and has a first pulse signal "IN1".
(For example, a bi-phase signal or EFM signal used for an audio interface) and a second pulse signal "I"
N2 "(for example, a control pulse signal from a VCO (voltage controlled oscillator)) is input and a first latch signal" Q1 "is output. The D-type flip-flop 2 constitutes a second latch circuit. And the first latch signal "Q1"
Also, a signal obtained by inverting the second pulse signal "IN2" by the inverter 3 is input and the second latch signal "Q2" is output. The exclusive-six or circuit 4 constitutes a first logic circuit, and has a first pulse signal “IN1”.
The first latch signal "Q1" is input and the first phase difference signal "U" (for example, a VCO frequency increasing signal) is output. Exclusive-sive or circuit 5 is the second
The first latch signal "Q
1 "and the second latch signal" Q2 "are input, and the second phase difference signal" D "(for example, the VCO frequency decreasing signal) is output. Each of these components is the same. It is formed in an integrated circuit.

Next, the operation of the phase comparison circuit shown in FIG. 1 will be described with reference to the time chart shown in FIG.

Input terminal "D" of the D flip-flop 1.
The first pulse signal “IN1” input to the first latch signal “Q1” is latched at the rising edge of the second pulse signal “IN2” input to the clock terminal “C”, and the first latch signal “Q1” is output from the output terminal “Q”. Is output. The first latch signal “Q1” input to the input terminal “D” of the D-type flip-flop 2 is input to the clock terminal “C” of the second latch signal “Q1”.
It is latched at the rising edge of the inverted signal of the pulse signal “IN2”, and the second latch signal “Q” is output from its output terminal “Q”.
2 "is output. In the EXCLUSIVE-SIVOR circuit 4,
First pulse signal “IN1” and first latch signal “Q
1 ”is input, and the exclusive OR of these signals is output as the first phase difference signal“ U ”. The exclusive-sequor circuit 5 has the first latch signal“ Q1 ”and the second latch signal“ Q2. "Is input and the exclusive OR of these signals is output as the second phase difference signal" D ". These first phase difference signal" U "and second phase difference signal" D "are
For example, it is input to the charge pump circuit.

As described above, in the phase comparison circuit shown in this embodiment, the same input / output relationship as that of the conventional example shown in FIG. 3 (input signals are "IN1" and "IN2", output signal is "U"). And "D") are obtained.

[0011]

According to the present invention, a phase comparison circuit having a small circuit scale can be obtained.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram showing an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of FIG.

FIG. 3 is an electric circuit diagram showing a conventional example.

[Explanation of symbols]

 1 ... D-type flip-flop (first latch circuit) 2 ... D-type flip-flop (second latch circuit) 4 ... Exclusive-OR circuit (first logic circuit) 5 ... EXCLUSIVE-OR circuit (second logic) circuit)

Claims (1)

[Claims] 1. A phase comparison circuit for generating a phase difference signal corresponding to a phase difference between a first pulse signal and a second pulse signal, wherein the first pulse signal is latched by using the second pulse signal as a clock signal and latched. A first latch circuit that outputs the latched first latch signal, and a second latch circuit that latches the first latch signal using the inverted signal of the second pulse signal as a clock signal and outputs the latched second latch signal And a first logic circuit that generates a first phase difference signal by an exclusive OR of the first pulse signal and the first latch signal, and an exclusive OR of the first latch signal and the second latch signal And a second logic circuit for generating a second phase difference signal according to the above.