JP3601884B2 - Timing control circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention provides a timing control circuit.On the roadIn particular, the present invention relates to a timing control circuit that controls the timing by changing the phase of a signal in an electronic circuit.
In recent years, for example, with an increase in the speed of a CPU clock in a computer system or an increase in the processing speed of various other electronic circuits, it is necessary to increase the speed of, for example, an interface portion. There is a need for a timing control circuit that appropriately controls the timing of the control signal in accordance with the cycle of the control signal to be used.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, for example, a clock access time in a synchronous memory (an example of the fastest point in a memory) is mainly defined by delay times such as a delay of an input buffer, a wiring delay by a long wiring, and a delay of an output buffer. ing. Since these delay times cannot be reduced unless the chip size is reduced or the transistor characteristics are significantly improved, for example, it is difficult to increase the speed of the synchronous memory.
[0003]
By the way, the chip size of recent LSIs is increasing, and only 1 nsec. As a result, the clock access time is not limited to 5 nsec. The fact is that LSIs that cannot be reduced to the following are increasing. This means that the operating frequency of about 100 MHz is a limit when considering the case where clock access is continued.
[0004]
On the other hand, by performing the pipeline configuration and the parallel-serial conversion, the switching frequency of the signal inside the chip can be extremely increased, and the output circuit cannot keep up with the characteristics inside the chip. .
FIG. 22 is a diagram for explaining an example of a conventional timing control circuit. FIG. 22A shows, for example, an input buffer (delay due to the input buffer) defining a clock access time, a wiring delay, and , Output buffer (delay due to output buffer). Specifically, for example, in the synchronous memory, when the clock signal CLK supplied to the clock input IN rises (see FIGS. 22C and 22D), after a predetermined clock access time, the data is output from the output OUT. Is output (see FIG. 22B).
[0005]
In recent years, when the external clock CLK used changes from an external clock as shown in FIG. 22 (c) to a high-speed external clock as shown in FIG. 22 (d), it is not after one clock cycle time has elapsed. In some cases, the output may not be determined.
FIG. 23 is a block diagram schematically showing an example of a circuit configuration to which the timing control circuit is applied. In the figure, reference numeral 221 denotes a clock buffer, 222, 223, and 224 denote LSIs (functional blocks), and 225, 226, and 227 denote registers.
[0006]
In the circuit shown in FIG. 23, a clock CLK is supplied to registers 225, 226, and 227 provided at the outputs of the LSIs 222, 223, and 224 via a clock buffer 221. It is output every cycle time. That is, after three clock times from the clock supplied to the input IN of the LSI 222, data subjected to predetermined processing is transmitted from the output OUT. Here, the LSIs 222, 223, and 224 may be functional blocks (internal circuits) in one chip. The timing control circuit is provided in the clock buffer 221 or in each of the LSIs 222, 223, and 224.
As described above, the tining control circuit can be applied to various electronic circuits including a plurality of LSIs or various chips including a plurality of functional blocks (internal circuits).
[0007]
FIG. 24 is a diagram for explaining another example of the conventional timing control circuit, and shows a timing control circuit for a circuit to which the pipeline system is applied.
In the timing control circuit to which the pipeline method shown in FIG. 24 is applied, in each pipeline processing, a clock access is started by a clock three cycles before to absorb a delay by an input buffer, a wiring delay, and a delay by an output buffer. The clock access time and the three clock cycle times are used in synchronization. That is, by starting a clock access by a clock one cycle or more earlier, the operation is performed with a margin in the internal transmission time.
[0008]
However, in a case where the clock access is started by a clock one cycle or more before (for example, three cycles before), if the frequency of the external clock CLK is changed, the specifications regarding the output determination time will not be satisfied. That is, normally, it is necessary to determine the output for a certain time before and after the rising edge of the external clock. However, if the frequency of the external clock CLK is changed, the clock cycle and the timing of determining the output will be out of synchronization, resulting in an incorrect operation. Will not be able to do.
[0009]
[Problems to be solved by the invention]
In order to solve the above-mentioned problem, a delay circuit (delay circuit: timing control circuit) having a variable delay time according to the clock cycle time, or ｛(clock cycle time) × 2− (clock access time) ) A circuit (timing control circuit) for shifting the phase of the clock by-／ output determination time｝ is required. However, a delay circuit using a simple gate array cannot generate the above-described delay time. As such a circuit, a PLL (Phase-Locked Loop) circuit is known. However, since it is an analog circuit, it is susceptible to power supply noise, and the circuit scale is increased and the current consumption is increased. There is not practical.
[0010]
The present invention has been made in view of the above-mentioned problems of the conventional timing control circuit, and has as its object to provide a timing control circuit that appropriately controls the timing of the control signal according to the cycle of the control signal to be used.
[0011]
[Means for Solving the Problems]
According to the present invention,A first delay circuit for receiving a clock signal, a variable delay circuit for receiving the clock signal and a clock signal from the first delay circuit, and delaying a clock signal from the first delay circuit; A variable delay circuit having a delay time obtained by multiplying a time difference between the input of the clock signal from the first delay circuit and the transition of the clock signal by N times (N is an integer of 2 or more); the first delay circuit; A second delay circuit connected in series with the variable delay circuit to generate a control clock signal having a fixed time difference from the clock signal;A timing control circuit is provided.
[0013]
[Action]
According to the timing control circuit of the present invention, both the first circuit 1 having the first delay time IB-1 and the second circuit 2 having the second delay time IB-2 are provided by the time difference expansion circuit 3. The time difference τ between the switching timing of the first signal A passing through the first circuit 1 and the switching timing of the second signal B (C) passing only through the first circuit 1 is α times (α is 1 or more: for example, α = 2.0). Then, it is possible to obtain an output that switches at a certain time difference from the input control signal CLK.
[0014]
FIG. 1 is a diagram showing a principle configuration of a timing control circuit according to the present invention.
As described in the above-mentioned prior art, setting the delay time to {(clock cycle time) × 2− (clock access time) −1/2 output fixed time} requires a delay circuit using a simple gate array. Is difficult.
Therefore, in the present invention, as shown in FIG. 1, the switching time difference τ1 between the first signal and the second signal is reproduced at the position of τ2. In order to simplify the description, the description will be made on the assumption that the output timing is synchronized with the rising edge of the clock.
[0015]
In order to obtain the output confirmation time, the output switching needs to be faster than two clock cycles. However, if the second input buffer delay time is omitted in the above time distribution, the output switching is made faster by that amount. be able to. Further, even when the delay time of the first output buffer is increased, output switching can be accelerated by that much.
[0016]
As described above, by realizing a circuit that reproduces the time difference between the switching of the two signals, the control according to the cycle of the control signal to be used can be performed without using a PLL having problems in noise resistance performance and power consumption. A timing control circuit that appropriately controls signal timing can be configured.
For example, by using the timing control circuit of the present invention, which can appropriately control the timing of the control signal according to the cycle of the control signal to be used, a previous clock can be used for an arbitrary clock frequency. The clock access can be output by the clock signal and the operating frequency of the circuit can be increased.
[0019]
【Example】
Hereinafter, embodiments of the timing control circuit according to the present invention will be described with reference to the accompanying drawings.
FIG. 2 is a diagram for explaining a first embodiment of the timing control circuit of the present invention. In the figure, reference numeral 1 denotes an input buffer circuit (delay time: IB-1), reference numeral 2 denotes a delay circuit (delay time: IB-2), and reference numeral 3 denotes a switching time difference (τ) of two signals described later. A time difference expansion circuit (delay time: Q) for doubling is shown.
[0020]
A clock signal (control signal) CLK is input to the input buffer circuit 1, and the delay circuit 2 has substantially the same delay time as the input buffer circuit 1. As shown in FIG. 2, a clock signal having a delay time (IB-1) + (IB-2) output via the input buffer circuit 1 and the delay circuit 2 becomes the first signal A, The clock signal having the delay time (IB-1) by the buffer circuit 1 becomes the internal clock signal C (second signal), and the signal obtained by doubling the cycle of the internal clock signal is the signal B (second signal). It becomes.
[0021]
As is apparent from FIG. 2, the time difference extending circuit 3 generates the internal clock from the rising timing of the first signal A to the falling timing of the signal B, or one cycle after the rising timing of the first signal A. There is a delay time (Q) that doubles the switching time difference τ between the two signals until the rising timing of C. As a result, an output (a phase-controlled clock signal: OUT) that switches at the same phase as the external clock CLK supplied to the input IN can be obtained.
[0022]
Here, the time difference extending circuit 3 is not limited to the one that doubles the time difference τ between two signals, and may be configured to extend the time difference τ by N times (N is an integer of 2 or more). . That is, in the timing control circuit of the present invention, the time difference expansion circuit 3 is configured so that the delay time of the time difference expansion circuit is N times the time difference τ, and has the same phase as the external clock CLK supplied to the input IN. The switching output may be obtained.
[0023]
In the above-described first embodiment of the present invention and each of the following embodiments, the delay time of a circuit that changes according to the cycle time of a clock is digitally set according to the clock. This means that a circuit (delay circuit: timing control circuit) that digitally and accurately multiplies the time difference between two signals that change according to the clock by N (N is an integer of 2 or more, specifically, for example, 2). It can be realized by configuring. In the first embodiment of the present invention and each of the following embodiments, for simplicity of description, the output timing is assumed to be at the same time as the rising edge of the clock. In the case of using, the signal of the required timing can be obtained by simply adding a predetermined delay to the output timing at the same time as the rise of the clock.
[0024]
FIG. 3 is a diagram for explaining a second embodiment of the timing control circuit of the present invention. In the second embodiment, the second circuit 2 includes two delay circuits 21 and 22. The first delay circuit (long wiring delay portion) 21 is provided with a delay time R of the signal transmission unit 4 until the output signal (phase-controlled clock signal) is supplied from the time difference expansion circuit 3 to the next stage circuit. The second delay circuit 22 has substantially the same delay time, and the second delay circuit 22 corresponds to the delay circuit 2 having substantially the same delay time (IB-2) as the input buffer circuit 1 in the first embodiment. . Here, the second delay circuit 22 is configured by, for example, a dummy wiring pattern similar to that of the signal transmission unit 4, whereby the second delay circuit 22 corresponds to the delay time R of the signal transmission unit 4. It has a delay time P.
[0025]
Therefore, the time difference expansion circuit 3 switches the first signal A passing through the input buffer circuit 1, the first delay circuit 21 and the second delay circuit 22, and the second signal passing only through the input buffer circuit 1. The time difference τ from the switching timing of the signal B (C) is extended twice (N times) to obtain an output that switches at the same phase as the clock signal CLK.
[0026]
FIG. 4 is a diagram for explaining a third embodiment of the timing control circuit of the present invention. In the third embodiment, the internal circuits (the first circuit 1 and the second circuit) are the input buffer circuit 1. , A long wiring delay section 21, an output buffer circuit 23, and a delay circuit 22.
In the third embodiment, the clock signal (control signal) CLK input in the Mth cycle passes through the internal circuits (the input buffer circuit 1, the long wiring delay portion 21, the output buffer circuit 23, and the delay circuit 22). The signal A (first signal) after this and the signal B (second signal) after the clock signal CLK input in the [M + 1] cycle has passed only part of the internal circuit (input buffer circuit 1) ) Is input to the time difference expansion circuit 3. The time difference extending circuit 3 doubles the switching time difference (τ) between two signals (N times) as in the first embodiment described above.
[0027]
In the third embodiment, the output of the time difference expansion circuit is delayed by the signal transmission unit 4 (delay time R) and output. Note that the delay time P of the long wiring delay portion 21 corresponds to the delay time R in the signal transmission unit 4. As a result, a clock signal (internal clock signal) with a timing earlier by the delay time of the output buffer circuit 23 can be output.
[0028]
FIG. 5 is a diagram for explaining a fourth embodiment of the timing control circuit of the present invention. In the fourth embodiment, the internal circuits include an input buffer circuit 1, a long wiring delay section 21, an output buffer circuit 23, And delay circuits 24 and 22. The signal from the time difference expansion circuit 3 is output via the long wiring delay section (signal transmission section) 4 and the output buffer circuit 5. Here, the delay time P of the long wiring delay section (first delay circuit) 21 corresponds to the delay time R of the long wiring delay section (signal transmission section) 4 and the delay time S of the output buffer circuit 23. Corresponds to the delay time U of the output buffer circuit 5.
[0029]
As described above, in the fourth embodiment, the clock signal CLK input in the Mth cycle is supplied to the first internal circuit (the input buffer circuit 1, the long wiring delay portion 21, the output buffer circuit 23, and the delay circuit 24, 22) and the second signal after the clock signal CLK input in the [M + 1] cycle has passed only a part of the first internal circuit (input buffer circuit 1). The signal B is input to the time difference expansion circuit 3. Further, the output of the time difference expansion circuit 3 is output to the second internal circuit having a delay time (R, U) substantially equal to the delay time (P, S) of the predetermined portion (the long wiring delay portion 21, the output buffer circuit 23). The second internal circuit (the long wiring delay portion 4 and the output buffer circuit 5) is passed through the second internal circuit to make the output of the second internal circuit a phase-controlled signal.
[0030]
As a result, it is possible to output a clock signal (internal clock signal) at a timing earlier by the delay time T of the delay circuit 24.
FIG. 6 is a diagram for explaining a fifth embodiment of the timing control circuit of the present invention, and shows a specific application example of the fourth embodiment.
The fifth embodiment shown in FIG. 6 uses the delay circuit 24 having the delay time T in the fourth embodiment to determine the output at a predetermined timing. That is, in the present embodiment, the timing at which the output changes is advanced by the delay time T of the delay circuit (output determination time setting circuit) 24, so that the timing before the rising (falling) timing of the clock signal (control signal) CLK is reached. At a predetermined period before and after the rising (falling) timing of the clock signal CLK. As a result, it is possible to prevent the data from being erroneously taken in and to ensure the correct operation of the circuit.
[0031]
FIG. 7 is a diagram for explaining a sixth embodiment of the timing control circuit of the present invention, and shows the relationship between signals in the above-mentioned respective drawings.
That is, the time difference expansion circuit 3 doubles the switching time difference τ between the two signals (N times). Specifically, the delay time output via the input buffer circuit 1 and the delay circuit 2 The switching time difference τ between the first signal A having (IB-1) + (IB-2) and the signal B (second signal) having only the delay time (IB-1) by the input buffer circuit 1 is doubled. It is to be. Here, the signal B has a cycle twice as long as the clock signal CLK. Note that the switching time difference τ can be defined using an internal clock signal C (second signal) instead of the signal B.
[0032]
Specifically, the switching time difference τ is 2 from the rising timing of the first signal A to the falling timing of the signal B or the rising timing of the internal clock C one cycle after the rising timing of the first signal A. It corresponds to the switching time of two signals. The switching time difference τ is doubled (N times: delay time Q) by the time difference expansion circuit 3, and as a result, an output (a phase-controlled clock signal) that switches at the same phase as the external clock CLK supplied to the input IN : OUT) can be obtained.
[0033]
FIGS. 8 to 16 are diagrams for explaining the seventh to fifteenth embodiments of the timing control circuit according to the present invention. In particular, the time difference extension circuit 3 for extending the time difference τ by two times, FIG. 9 is a diagram illustrating a specific configuration of a delay circuit (3) that doubles a delay time (N times).
In the seventh embodiment shown in FIG. 8, reference numeral AA is a first gate row, BB is a second gate row, A1 to An are gate circuits constituting the first gate row, and B1 to Bn are first gate rows. A gate circuit constituting a gate column, X indicates a first control signal, and Y indicates a second control signal.
[0034]
The first gate row AA includes a plurality of series-connected gate circuits A1, A2, A3,... That propagate a signal in a first direction (a direction from the gate circuit A1 to An), and a first control signal X controls the activation of at least a part of the first gate row AA. Further, the second gate row BB includes a plurality of serially connected gate circuits B1, B2, which propagate signals in a second direction (a direction from the gate circuit Bm toward B1) opposite to the first direction. , And the activation of at least a part of the second gate row BB is controlled by the second control signal Y.
[0035]
The first control signal X is supplied to each of the gate circuits A1 to An of the first gate row AA via the control signal line SLA. The second control signal Y is supplied to the second gate row AA. Each of the gate circuits B1 to Bm of BB is supplied via a control signal line SLB.
The outputs of the gate circuits A1, A2,..., An-1 in the first gate row AA are connected to the inputs of the gate circuits B1, B2,. I have. Here, it is not necessary to short-circuit the input and output of each gate circuit in the first and second gate columns for all the gate circuits. In the embodiment shown in FIG. 8, the gate circuits (A1, A2, A3,..., An) of the first gate row AA and the gate circuits (B1, B2, B3,. ) Are configured to have the same number of stages (ie, n = m). The number of stages of the gate circuit is three or more.
[0036]
Further, the first control signal X and the second control signal Y are generated from the same basic control signal (clock signal CLK), the first control signal X corresponds to the clock signal CLK, and the second control signal Y Correspond to the inverted-level clock signal CLK. When the clock signal CLK is at a high level "H", the first gate row AA is activated to inactivate the second gate row BB, and when the clock signal CLK is at a low level "L", the first gate row AA is deactivated. The first gate row AA is deactivated and the second gate row BB is activated.
[0037]
Then, for example, during the time τ during which the clock signal CLK becomes high level “H” and the first gate row AA is activated (the second gate BB is inactive), the first gate row AA Is "11010", when the clock signal CLK becomes low level "L", the second gate row BB is activated (the first gate AA is inactivated) and the input data is inverted. The data “01011” is reproduced at the time τ and is output from the second gate row BB.
[0038]
In the eighth embodiment shown in FIG. 9, control signal lines SLA and SLB are connected via inverters (buffer circuits) IA and IB provided for a predetermined number of gate circuits (for example, A1 to A3; B1 to B3). It is connected to each gate circuit. Here, in the present embodiment, the buffer circuit is constituted by inverters IA and IB, and control signal lines SLA and SLB via inverters IA and IB are constituted so as to be control signal lines of gate columns on opposite sides. Have been. Here, if a buffer circuit that outputs a signal of a positive logic is used instead of the inverters IA and IB, it is not necessary to replace the control signal lines between the gate rows AA and BB.
[0039]
In the ninth embodiment shown in FIG. 10, the final output terminal OUT (AA) of the first gate array AA is set to a high impedance state, and the input terminal IN (BB) of the second gate array BB is set to a low level potential (the 1 potential) is fixed at “L”. Then, the last input signal of the high-level potential (second potential) “H” supplied when the first gate row AA is activated (when the clock signal CLK is at the high level “H”) When the second gate row BB is activated, the second gate row BB is made to proceed in the reverse direction, and when the low-level "L" data appears from the output terminal OUT (BB) of the second gate row BB, the first gate row BB is activated. The switching time difference τ between the input signal to the column AA and the first control signal X (CLK) is reproduced by the switching time difference τ between the second control signal Y (/ CLK) and the output signal of the second gate line BB. It is supposed to. Thereby, for example, the time difference expansion circuit 3 that doubles the switching time difference τ between the two signals in FIGS. 2 to 6 can be configured.
[0040]
In the tenth embodiment shown in FIG. 11, the gate circuits A1 to An in the first gate row AA and the gate circuits B1 to Bm in the second gate row BB are configured as inverters, and the gate circuits AA and BB Each gate circuit is configured to have the same number of stages (2N stages: even-numbered stages). Here, the sizes of the transistors forming the gate circuits (inverters) A1 to An forming the first gate row AA, and the gate circuits (inverters) B1 to Bm (Bn) forming the second gate row BB are formed. The input signal to the first gate row AA can be inverted by a predetermined multiple in time according to the size ratio of the transistor. That is, by changing the size of the transistors constituting each gate circuit in the gate rows AA and BB, the switching time difference τ between the two signals is increased by a factor (for example, 1.5 times) corresponding to the size ratio of the transistors. Can be Thereby, for example, it is possible to perform control so as to determine the output during a certain period before and after the rising timing regardless of the cycle of the control signal (clock signal).
[0041]
In FIG. 11, the first control signal X generates the clock signal CLK via the two-stage inverters I1 and I2, and the second control signal Y generates the clock signal CLK via the one-stage inverter I1. Is generated. Further, an inverter constituted by an N-channel MOS transistor TR0 and a P-channel MOS transistor TR00 is provided at the input terminal IN (AA) of the first gate row AA. That is, the input terminal IN (AA) of the first gate row AA is input to the gates of the N-channel MOS transistor TR0 and the P-channel MOS transistor TR00, and the output of the inverter by the transistors TR0 and TR00 is applied to the gate circuit (inverter). ) A1.
[0042]
Further, in the tenth embodiment shown in FIG. 11, the final output terminal OUT (AA) of the first gate array AA is in a high impedance state (Open), and the input terminal IN (BB) of the second gate array BB is It is fixed at a high level “H”. The output terminal OUT (BB) of the second gate row BB is connected to an output (output of a delay circuit) OUT via an inverter I0, so that an output signal having a stable level is taken out.
[0043]
In the eleventh embodiment shown in FIG. 12, the gate circuits A1 to An and B1 to Bm in the gate arrays AA and BB in the above-described tenth embodiment are configured as inverters having power control transistors. Specifically, for example, the first-stage inverter A1 of the gate row AA includes a P-channel MOS transistor TR11 controlled by a control signal X (/ CLK) and an N-channel MOS transistor controlled by a control signal Y (CLK). TR12 is provided, and activation / inactivation is controlled in accordance with the level of clock signal CLK.
[0044]
Here, the transistor TR1 controlled by the control signal Y is provided also for the source of the transistor TR0 provided at the input terminal IN (AA) of the gate row AA. The control signal X generates the clock signal CLK via the three-stage inverters I1, I2 and I3, and the control signal Y generates the clock signal CLK via the two-stage inverters I1 and I4. It has become. As described above, by providing the power supply control transistors (TR11, TR12) for the respective gate circuits A1 to An and B1 to Bm, the load of the transistor that supplies the power supply voltage to each gate circuit is distributed. ing.
[0045]
In the twelfth embodiment shown in FIG. 13, basically, an output buffer circuit OB is provided instead of the inverter I0 provided at the output terminal OUT (BB) of the gate row BB in the eleventh embodiment described above. Things.
The output buffer circuit OB includes delay units D1 and D2 each composed of an odd number of inverters, a latch unit LA for eliminating an uncertain output state, a NAND gate ND, and transistors TR101, TR102 and TR103. I have. Here, the signal is supplied to the first-stage gate circuit A1 only when the signal supplied to the input terminal IN (AA) is at the high level "H". In this output buffer circuit OB, the final output terminal (OUT (BB)) of the second gate row BB is from low level “L” to high level “H” (or from high level “H” to low level “L”). Only the edge that switches to is captured and output.
[0046]
Further, in FIG. 13, a low-level potential (first potential) “L” or a high-level potential (second potential) “H” is applied to the input terminal IN (AA) of the first gate row AA. One-way driving means TR0 for driving only one side is provided. That is, the input terminal IN (AA) of the first gate row AA is input to the gate of the N-channel MOS transistor TR0. Thus, an output signal from which unnecessary switching is eliminated can be obtained.
[0047]
In the thirteenth embodiment shown in FIG. 14, for example, a control means for controlling the activation of a gate row by a control signal is divided by 1 / N (N is an integer of 2 or more) into an input clock signal. In the case of a configuration in which a signal having a period N times as large as that of the first gate row AA and the second gate row is shown (in the circuit examples of FIGS. It is necessary to provide N sets of circuits corresponding to BB. However, an output buffer circuit OB ′ for superimposing outputs of the N sets of circuits (outputs OUT (BB1) to OUT (BBN) of the respective second gate arrays). 14 illustrates a circuit example (corresponding to the output buffer circuit OB in FIG. 13).
[0048]
As is clear from the comparison between FIG. 13 and FIG. 14, in the thirteenth embodiment, the outputs OUT (BB1) to OUT (BBN) of the N sets of circuits include the transistor TR112 corresponding to the transistors TR102 and TR103 in FIG. , TR113 to TR1N2, TR1N3 (switch means) are provided, and the drains of the transistors TR112 to TR1N2 are commonly connected to take out the superimposed output OUT. Here, the superimposed output OUT is a signal having the same frequency and a different phase as the clock signal CLK. The outputs of the N sets may be configured to be reset to a predetermined level by a common output signal level control circuit after a predetermined time.
[0049]
FIG. 15 is a diagram for explaining a fourteenth embodiment of the timing control circuit of the present invention. In the thirteenth embodiment, the input signal is frequency-divided by ３ and the cycle three times as long as the input signal is set. FIG. 5 shows a case where three control signals are generated.
As shown in FIG. 15, each of the control signals 1 to 3 has three times the cycle of the input signal (clock signal CLK). Then, the outputs (output signals 1 to 3) of the three sets of circuits composed of the first gate row and the second gate row corresponding to each of the three control signals are superimposed as shown in FIG. An output signal is obtained by the output buffer circuit OB '. The superimposed output signal (OUT) is a signal having the same frequency as that of the input signal and having a different phase, without depending on the frequency of the input signal (CLK).
[0050]
FIG. 16 is a diagram for explaining an application example of the timing control circuit (delay circuit, phase shift circuit) of the present invention. In the figure, reference numeral 61 denotes a timing control circuit, 62 denotes an arbitrary circuit (other circuit), and 63 denotes an output buffer circuit.
As shown in FIG. 16, the timing control circuit 61 changes the phase of a clock signal (first clock signal) CLK supplied from the outside to generate an internal clock signal (second clock signal). Further, the internal clock signal is supplied to an output buffer circuit 63 to which an output of an arbitrary circuit 62 is input, and an output synchronized with the internal clock signal is obtained from the output buffer circuit 63. It is needless to say that the above-described timing control circuit (delay circuit) according to the present invention is not limited to the circuit configuration of FIG. 16 and can be applied to various circuits.
[0051]
17 to 19 are circuit diagrams showing an example of a clock generation circuit to which the timing control circuit according to the present invention is applied. 17 to 19, reference numeral 71 denotes a delay circuit (programmable delay circuit), 72 denotes a dummy wiring section (long wiring delay section), and 73 denotes a frequency dividing circuit (1/2 frequency dividing circuit). .
20 and 21 are timing charts showing signals of the clock generation circuit shown in FIGS. 20 and 21, reference numeral CLK is a clock signal input to the clock signal generation circuit, X and Y (signal Y is a signal / X at an inverted level of signal X) are control signals, and A, B, and C are clock signals. The signals in each part of the generation circuit are shown. Further, reference numerals E1 to E31 and the like indicate output signals of gate circuits (inverters) in each gate row of the clock generation circuit.
[0052]
In the clock signal generating circuits shown in FIGS. 17 to 19, the clock signal CLK input to the frequency dividing circuit 73 is divided by １ ／ and a signal having a cycle twice as long as the clock signal CLK (corresponding to the control signals X and Y). ). As described above, when a signal obtained by dividing the input signal by と し て is used as the control signals X and Y, as described above, two sets of circuits having the first gate row and the second gate row are used. (AA1, BB1; AA2, BB2) 74 and 75 are provided. Then, the combination output OUT (G) is extracted via the output buffer circuit (OB ′) in which the outputs OUT (BB1) and OUT (BB2) of the two sets of circuits described with reference to FIGS. It is. Here, in the clock signal generation circuits shown in FIGS. 17 to 19, the combination output OUT (G) is supplied to the read control circuit 70 as an output control clock, and the combination with the read control signal (/ RE) is taken. The read data D (1) to D (8) are read.
[0053]
As shown in FIGS. 17 to 19, each common node in the first gate row AA1, AA2 and the second gate row BB1, BB2 in each set is provided with capacitance means CL, and the signal propagation time Is made longer. The value of the capacitance means CL is set larger as going from the input side IN (AA1) (IN (AA2)) of the first gate row AA1 (AA2) to the output side OUT (AA1) (OUT (AA2)). Thus, the delay time in each gate circuit (inverter) increases as going to the output side. Specifically, for example, in the first portion of each set (portion on the input side IN (AA1) (IN (AA2)) of the first gate row AA1 (AA2)), no capacitance means is provided and each gate circuit Is configured to have a small delay time. Then, for example, in the vicinity of the 41st stage, the value of the capacitance means CL is equal to the capacitance C_INAnd around the 51st stage, the value of the capacitance means CL is equal to the capacitance C of the input section._INIs set to be 12 times as large as
[0054]
Further, for example, in the clock signal generation circuits shown in FIGS. 17 to 19, the control signal lines for supplying the control signals X and Y are provided with inverters (buffer circuits) IA and IB for every ten stages of gate circuits. The control signal line via these inverters IA and IB is configured to be the control signal line of the gate row on the opposite side. The configuration of the superimposed output buffer circuit OB ', the levels of the output terminals OUT (AA1) and OUT (AA2) of the first gate arrays AA1 and AA2, and the input terminals IN (BB1) of the second gate arrays BB1 and BB2. , IN (BB2) are the same as those in the above-described embodiments, and a description thereof will be omitted.
[0055]
Then, as shown in FIGS. 20 and 21, according to the clock signal generation circuits shown in FIGS. 17 to 19, two sets of circuits (AA1, BB1) having a first gate row and a second gate row are provided. AA2, BB2) The superimposed output OUT (G) obtained by superimposing the outputs of 74 and 75 can be obtained as a signal having the same frequency as the clock signal CLK and different phases. As a result, for example, regardless of the cycle of the clock signal CLK, it is possible to perform control so as to determine the output during a certain period before and after the rising timing.
[0056]
Hereinafter, embodiments of the delay circuit according to the present invention will be described in detail in comparison with the related art.
FIG. 25 is a block diagram showing an example of a conventional delay circuit. 25, reference numeral 300 denotes a unit delay circuit (UD), 301 denotes a multiplexer (MUX), 302 denotes a phase detection circuit, and 303 and 304 denote RC delay circuits.
[0057]
The delay circuit shown in FIG. 25 has a predetermined delay from the input clock signal CLK by selecting each output of a multi-stage delay line (in which unit delay circuits 300 are connected in series) with a multiplexer 301. An output signal CLK 'is output. That is, the multiplexer 301 detects the signal fed back via the RC delay circuit 304 by the phase detection circuit 302, compares the phase with the clock signal CLK, and sets a predetermined delay time according to the output of the phase detection circuit 302. The output of the delay line is selected. Note that the RC delay circuits 303 and 304 show a delay circuit using a resistor (R) and a capacitor (C), and an output signal CLK ′ is output via the RC delay circuit 303.
[0058]
Therefore, in the delay circuit shown in FIG. 25, it is necessary to drive a large number of unit delay circuits 300, and thus there is a problem in power consumption.
FIG. 26 is a block diagram showing another example of the conventional delay circuit. 26, reference numeral 305 denotes a driver circuit, 306 denotes a multiplexer (MUX), and 307 denotes a capacitor array.
[0059]
The delay circuit shown in FIG. 26 selects the output load (capacitance by the capacitor array 307) of the driver circuit 305 by the multiplexer 306, so that the rise time (Rise-Time) and the fall time (Fall-Time) of the node are provided. , That is, using the rounding of the signal waveform to output an output signal CLK ′ having a predetermined delay from the input clock signal CLK. The multiplexer 306 detects a signal fed back via the RC delay circuit 304 by the phase detection circuit 302, compares the phase with the clock signal CLK, and determines a predetermined value of the capacitor array 307 according to the output of the phase detection circuit 302. The output load (capacity) is selected. The output signal CLK 'is also output via the RC delay circuit 303.
[0060]
Therefore, in the delay circuit shown in FIG. 26, since the delay time is specified by using the rounding of the signal waveform, the delay circuit is susceptible to noise and has a problem in accuracy.
FIG. 27 is a block diagram showing an example of a conventional PLL circuit. In FIG. 27, reference numeral 310 indicates an oscillator, 320 indicates a phase comparator, and 330 indicates a control circuit.
[0061]
In general, an oscillator whose phase can be controlled by a control signal (CTRL) is called a PLL (Phase-Locked-Loop). In many cases, the PLL circuit controls the delay value of a gate constituting an oscillator (ring oscillator) by voltage, and is usually configured as an analog circuit. When the delay value is controlled by a gate load, a transistor size, the number of gate stages, or the like, it is also referred to as a digital PLL.
[0062]
As shown in FIG. 27, the PLL circuit obtains clocks having various phases (30 degrees, 90 degrees, 120 degrees, etc.) depending on which gate stage of the ring oscillator (oscillator) 310 takes the output. Therefore, a clock having a double cycle, a triple cycle, or the like can be generated.
However, this PLL circuit basically includes the oscillator 310, the phase comparator 320, and the control circuit 330. The phase comparison and the control of the delay value depend on fluctuations in the power supply voltage and temperature (such as noise). And change. Further, since a ring oscillator is usually used as the oscillator 310, there is also a problem in terms of power consumption.
[0063]
Also, conventionally, a case in which an open gate array is used while a PLL uses a ring oscillator is generally referred to as a DLL (Delay-Line-Lock). The delay circuit of the present invention described below can be applied to a digital DLL circuit that can greatly reduce power consumption, is resistant to noise, has low power consumption (less standby current), and is stable at high speed. It is suitable for a circuit for generating a clock signal or the like of a high-speed general-purpose memory (such as a DRAM) requiring such a signal.
[0064]
FIG. 28 is a block diagram showing a basic configuration of a DLL circuit to which the present invention is applied. 28, reference numeral 411 denotes a first conversion circuit (CA), 412 denotes a gate stage number information conversion circuit (CD), 413 denotes a second conversion circuit (CB), and 410 denotes a phase comparator 420 and a control circuit. 430 shows a fine adjustment circuit constituted by 430.
FIG. 29 is a block diagram showing a principle configuration of a delay circuit to which the present invention is applied. As shown in FIGS. 29A and 29B, the first conversion circuit CA includes a plurality of unit circuits (first unit circuits) UA connected in cascade (array). The second conversion circuit CB includes a plurality of unit circuits (second unit circuits) UB connected in cascade (arranged in an array).
[0065]
The first conversion circuit CA converts a first switching time difference τ at which the first input signal CLK-A and the second input signal CLK-B are switched into corresponding first gate stage number information (N bits). . The second conversion circuit CB converts the second gate stage number information (N 'bit) determined according to the first gate stage number information (N bits) into a second switching time difference τ'. Then, the delay circuits shown in FIGS. 29A and 29B delay the third input signal IN input to the second conversion circuit CB by the second switching time difference τ ′ and output the delayed signal (FIG. 29A). OUT).
[0066]
The first conversion circuit CA has an array structure in which at least two or more first unit circuits UA are regularly repeated, and converts the first input signal CLK-A into the first unit circuit UA in the array of the first unit circuit UA. In the direction D1. Further, the second conversion circuit CB has an array structure in which at least two or more circuits UB of the second unit for reproducing the delay time per stage of the first unit circuit UA are regularly repeated. The input signal IN is propagated in the second conversion circuit (CB) in a second direction (D2) opposite to the first direction D1.
[0067]
In FIG. 29 (b), reference numeral CE indicates a reset unit including a plurality of reset circuits RST. The reset section CE resets input / output signals of each stage of the array of the second unit circuit UB in the second conversion circuit CB immediately before the third input signal IN is input.
30 is a waveform diagram showing an example of a circuit for generating a clock signal in the delay circuit of FIG. 29 and its operation. FIG. 30A is a circuit for generating the first input signal CLK-A, and FIG. A circuit for generating the second input signal CLK-B, and FIG. 9C is a waveform diagram showing the operation of these generators.
[0068]
As shown in FIGS. 30A and 30B, the clock signals (the first input signal CLK-A and the second input signal CLK-B) use a predetermined signal as it is. Not only that, for example, a clock signal generation circuit is composed of P-channel and N-channel MOS transistors whose gates receive two control signals CLK-A1 (CLK-B1) and CLK-A2 (CLK-B2), and two inverters. The clock signal generation circuit may be configured as a latch circuit, and the output of the clock signal generation circuit may be used as the first input signal CLK-A and the second input signal CLK-B. Thereby, as shown in FIG. 30C, a first input signal CLK-A and a second input signal CLK-B having a switching time difference (first switching time difference) τ are generated.
[0069]
Here, in the clock signal generation circuit shown in FIGS. 30A and 30B, as is apparent from FIG. 30C, the first input signal CLK-A and the second input signal CLK-B The switching time difference (first switching time difference τ) is the time from when the first input signal CLK-A rises to when the second input signal CLK-B falls, and the first input signal CLK-A. And the time from when the second input signal CLK-B rises until the second input signal CLK-B rises.
[0070]
FIG. 31 is a circuit diagram showing a first embodiment of the delay circuit of the present invention, and FIG. 32 is a waveform diagram showing the operation of the delay circuit shown in FIG. In FIG. 31, reference numeral CA indicates a first conversion circuit, CB1 and CB2 indicate second conversion circuits, CD1 and CD2 indicate gate stage number information conversion circuits, and RA indicates a latch circuit.
As shown in FIG. 31, the first embodiment of the delay circuit of the present invention includes one first conversion circuit (τ to N conversion circuit) CA and two gate stage number information conversion circuits (N to N ′ conversion circuit). ) CD1, CD2, and two second conversion circuits (N ′ to τ ′ conversion circuits) CB1, CB2, and a latch circuit RA.
[0071]
In the first conversion circuit CA, each unit circuit (first unit circuit) UA is configured by a NOR gate or a NAND gate. Specifically, in the first unit circuit UA, the even-numbered stages are configured by NOR gates, and the odd-numbered stages are configured by NAND gates. That is, the first unit circuit UA includes an inverting gate circuit having an inverting function, and performs conversion using a delay time per one stage of each gate of the inverting gate circuit as a unit time. Here, in the first unit circuit UA, the even-numbered stage may be constituted by a NAND gate, and the odd-numbered stage may be constituted by a NOR gate.
[0072]
Further, in the second conversion circuit CB (CB1, CB2), each unit circuit (second unit circuit) UB is configured by two NOR gates or two NAND gates. Specifically, in one second conversion circuit CB1, an even-numbered stage is formed by a NOR gate, an odd-numbered stage is formed by a NAND gate, and in the other second conversion circuit CB2, The even-numbered stages are constituted by NAND gates, and the odd-numbered stages are constituted by NOR gates. That is, the second unit circuit UB also includes an inverting gate circuit having an inverting function, and performs conversion using a delay time per one stage of each gate of the inverting gate circuit as a unit time. Here, in each of the second unit circuits UB, only one of the two gate circuits is used and the other is not used, because the symmetry of the circuit is maintained and the delay time of each unit circuit is accurately defined. To do that.
[0073]
In the latch circuit RA, each unit circuit is composed of two NOR gates or two NAND gates. In the gate stage number information conversion circuit CD (CD1, CD2), each unit circuit UD is a NOR gate or a NAND gate. It is composed of a gate. Further, a latch circuit RA is provided corresponding to each first unit circuit UA of the first conversion circuit CA, and the latch circuit (each latch unit of the latch circuit RA) is provided for each of the first unit circuits UA. The data to be output to is stored.
[0074]
The first switching time difference τ at which the first input signal CLK-A and the second input signal CLK-B are switched is converted into the corresponding first gate stage number information (N bits) in the first conversion circuit CA. You. That is, the signal change is transmitted to the N-bit unit circuit UA (gate of a predetermined number of stages) corresponding to the first switching time difference τ, and the data is held in the latch circuit RA. Then, the data of the latch circuit RA (in the first conversion circuit CA, the output of the gate next to the gate to which the signal has been transmitted) is passed through the gate stage number information conversion circuits CD1 and CD2, respectively, to the second conversion circuit CB1 And CB2, and the signals are propagated toward the output (OUT) side in the second conversion circuits CB1 and CB2.
[0075]
Here, in the first embodiment, the gate stage number information conversion circuits CD1 and CD2 supply the first gate stage number information (N bits) as they are to the second conversion circuits CB1 and CB2. , N to N conversion, and the second switching time difference τ ′ becomes the same as the first switching time difference τ by the conversion by the second conversion circuits CB1 and CB2.
[0076]
Therefore, as shown in FIG. 32, the delay at the nodes (1) and (2) becomes τ, and as a result, the input signal (third input signal) IN is delayed from the output (OUT) by the time τ. The output signal OUT is taken out. The pulse width TW0 of the signals at the nodes (1) and (2) is generated by the latch circuit LA0 and the delay line DL0 provided at the output (OUT). That is, the signals at the nodes (1) and (2) are reset so that the output (OUT) is kept in a high impedance state after the level change of the pulse width TW0.
[0077]
Here, the first gate stage number information (N bits) corresponds to a collection of all or a part of data output for each first unit circuit UA, and the second gate stage number information (N bit). The 'bit' corresponds to a collection of all or a part of data input for each second unit circuit UB. In the first embodiment, the second gate stage number information corresponds to a collection of all data input for each second unit circuit UB. That is, a signal synchronized with the signal of each bit of the first gate stage number information (N bits) is directly input to the second conversion circuit (CB1, CB2) as the second gate stage number information (N 'bit). It has become. Further, the gate stage number information (second gate stage number information) directly input to the second conversion circuit may be an in-phase signal with the signal of each bit of the first gate stage number information (N bits). Of course, it may be a signal.
[0078]
FIGS. 33 and 34 are circuit diagrams showing a second embodiment of the delay circuit of the present invention, and FIG. 35 is a waveform diagram showing the operation of the delay circuit shown in FIGS.
As shown in FIGS. 33 and 34, in the second embodiment, a latch circuit RB is provided in addition to the above-described latch circuit RA. The latch circuit RB is provided corresponding to each second unit circuit (UB) of the second conversion circuits CB1 and CB2 (CB), and is input to the latch circuit RB for each second unit circuit. Data to be stored. The latch circuit RB supplies stable data without signal flutter to the second conversion circuits CB1 and CB2.
[0079]
Here, in the second embodiment shown in FIGS. 33 and 34, reference numeral WR is a write control circuit, and the data of the first latch circuit RA is transferred to the second latch circuit RB in accordance with the operation of the write control circuit WR. Is written to.
FIGS. 36A and 36B are diagrams showing an example of a unit circuit applied to the delay circuit of the present invention. FIGS. 36A and 36B show a configuration example of the unit circuit, and FIG. It is a waveform diagram.
[0080]
As shown in FIGS. 36A and 36B, each unit circuit (UA, UB) has an inverter circuit (an inverting gate circuit having an inverting function), and a delay time per one gate of the inverter circuit. Is used as a unit time, a time difference (a first switching time difference at which the first input signal CLK-A and the second input signal CLK-B are switched) τ is converted into corresponding first gate stage number information (N bits). It has become.
[0081]
Here, in the unit circuits shown in FIGS. 36 (a) and (B), as shown in FIG. 36 (c), when the second input signal CLK-B is at the high level "H", When the switching of the input signal CLK-A is started, the output of the gate at the time when the second input signal CLK-B is set to the low level “L” is changed to the first gate corresponding to the first switching time difference τ. It remains as stage number information (N bits).
[0082]
FIG. 37 is a diagram showing another example of the unit circuit applied to the delay circuit of the present invention. As shown in FIGS. 37A and 37B, each unit circuit (UA, UB) has a reset signal input terminal (RESET), and a signal dependent on the first input signal CLK-A passes therethrough. The previous output is set to the opposite of the expected value. Further, each of the unit circuits (UA, UB) includes a data acquisition circuit (CI), and acquires data when the second input signal CLK-B is switched in the unit circuit.
[0083]
FIG. 38 is a diagram showing still another example of the unit circuit applied to the delay circuit of the present invention. As shown in FIGS. 38 (a) and (B), in each unit circuit (UA, UB), the delay time on the side for propagating a signal dependent on the first input signal CLK-1 is increased. The input thresholds of the first conversion circuit CA and the second conversion circuit CB are biased. That is, in the unit circuit (NAND type) shown in FIG. 38A, the transistor size of the P-channel MOS transistor is reduced, and the transistor size of the N-channel MOS transistor is increased. In the unit circuit (NOR type) shown in (1), the transistor size of the P-channel MOS transistor is increased, and the transistor size of the N-channel MOS transistor is reduced. As a result, the delay time (quantized speed) of each unit circuit can be shortened, and the delay time can be controlled with high accuracy.
[0084]
FIG. 39 is a diagram showing still another example of the unit circuit applied to the delay circuit of the present invention. As shown in FIGS. 39A and 39B, each unit circuit (UA, UB) is provided with a delay time adjusting capacitor CC. A capacity corresponding to the input capacity of the circuit CI is added. The capacitance CC shown in FIGS. 39A and 39B is composed of two transistors (CMOS transistors).
[0085]
Further, the unit circuit shown in FIGS. 39A and 39B includes a reset signal input terminal (RESET), and sets the output immediately before the signal dependent on the third input signal IN to pass the opposite of the expected value. It is supposed to.
FIG. 40 is a circuit diagram showing a third embodiment of the delay circuit of the present invention, and FIG. 41 is a waveform diagram showing the operation of the delay circuit shown in FIG.
[0086]
As shown in FIG. 40, the delay circuit according to the third embodiment includes two first conversion circuits CA1 and CA2 and two second conversion circuits CB1 and CB2. The gate stage number information output of each unit circuit UA of the conversion circuit CA1 (CA2) is directly supplied to the gate stage number information input of each unit circuit UB of the second conversion circuit CB1 (CB2), and the second conversion circuit CB1 The delay time of (CB2) is made equal to the delay time of the first conversion circuit CA1 (CA2).
[0087]
Here, one second conversion circuit CB1 starts an array from a unit circuit UB having a NAND type delay circuit, and the other second conversion circuit CB2 starts an array from a unit circuit UB having a NOR type delay circuit. Starting, the first stage unit circuit fixes the input level so as to be an inverter type delay circuit. As shown in FIG. 41, in the third embodiment of FIG. 40, an output signal OUT having a delay time 2τ twice the time difference τ is obtained from the input signal IN.
[0088]
42 and 43 are circuit diagrams showing a fourth embodiment of the delay circuit of the present invention, and FIG. 44 is a waveform diagram showing the operation of the delay circuit shown in FIGS. 42 and 43.
As shown in FIGS. 42 and 43, in the delay circuit of the fourth embodiment, the gate stage number information conversion circuit CD1 (CD2) includes the first conversion circuit CA1 (CA2) and the second conversion circuit CB1 (CB2). And is provided between them. That is, the gate stage number information conversion circuit CD1 (CD2) is a gate for every M stages (in this embodiment, every three stages, that is, every other stage) of each unit circuit UA of the first conversion circuit CA1 (CA2). The stage number information output is supplied to the gate stage number information input of each unit circuit UB of the second conversion circuit CB1 (CB2), and the delay time (τ) of the second conversion circuit CB1 (CB2) is converted to the first conversion time. The delay time is set to 1 / M (1/3 in this embodiment) of the delay time of the circuit CA1 (CA2).
[0089]
Specifically, in the fourth embodiment, one unit circuit UD in the gate stage number information conversion circuit CD2 is provided for the three unit circuits UA1 to UA3 in the first conversion circuit CA2 in FIG. As shown in FIG. 44, an output signal OUT having a delay time τ / 3 of の of the time difference τ is obtained from the input signal IN. As described above, according to the delay circuit of the present embodiment, it is possible to obtain an output signal having a required delay time.
[0090]
FIGS. 45 and 46 are circuit diagrams showing a fifth embodiment of the delay circuit of the present invention, and FIG. 47 is a waveform diagram showing the operation of the delay circuit shown in FIGS. 45 and 46.
As is apparent from a comparison between the fifth embodiment shown in FIGS. 45 and 46 and the fourth embodiment shown in FIGS. 42 and 43, in the fifth embodiment, the first conversion circuit CA1 (CA2) The gate stage number information output of every M stages (every two stages in this embodiment, ie, every other stage) of each unit circuit UA is output via a predetermined number of stages (one stage in this embodiment) of the inverter circuit II. The phase is matched to the required phase and supplied to the gate stage number information input of each unit circuit UB of the second conversion circuit CB1 (CB2). Specifically, the inverter II is inserted at every other stage of the gate output (every other stage gate output) taken out from the first conversion circuit CA1.
[0091]
As shown in FIGS. 45 and 46, in the fifth embodiment, two first conversion circuits (CA) (CA1 and CA2) are provided, and the first input circuit in the first conversion circuit (CA1) is provided. The delay time at the rise of the signal CLK-A and the delay time at the fall of the first input signal CLK-A in the first conversion circuit (CA2) are separately set.
[0092]
As a result, as shown in FIG. 47, the time difference τ when the first input signal CLK-A falls to the high level “H” and the second input signal CLK-B falls to the low level “L”.₁And a time difference τ when the first input signal CLK-A rises to a low level “L” and the second input signal CLK-B rises to a high level “H”.₂In contrast, a signal having a delay time of 1 / M (1/2 in this embodiment) can be obtained. In the present embodiment, the level of the output signal OUT is inverted with respect to the input signal IN. However, it goes without saying that any necessary signal can be generated depending on the configuration of the gate circuit. .
[0093]
Further, the gate stage number information conversion circuit CD, the gate stage number information output of one unit circuit UA of the first conversion circuit CA, and the gate stage number information input of the M-stage unit circuit UB of the second conversion circuit CB are input. And the delay time of the second conversion circuit CB can be set to M times the delay time of the first conversion circuit CA.
48 and 49 are circuit diagrams showing a sixth embodiment of the delay circuit of the present invention, and FIG. 50 is a waveform diagram showing the operation of the delay circuit shown in FIGS.
[0094]
As shown in FIGS. 48 and 49, in the sixth embodiment, the NAND type unit circuit and the NOR type unit are alternately arranged at the even and odd stages of the two first conversion circuits CA1 and CA2. The circuits are arranged repeatedly in an array, and the unit circuits for generating the delay time at the rise and the unit circuits for generating the delay time at the fall in the two second conversion circuits CB1 and CB2 are also provided. Similarly, NAND-type unit circuits and NOR-type unit circuits are alternately arranged in an array at the even and odd stages. Then, at the time of rising (the time difference τ when the second input signal CLK-B rises to the high level “H”).₂) And the time difference τ at the time of the fall (when the second input signal CLK-B falls to a low level “L”)₁In the delay time generation unit circuit of (1), the arrangement of the NAND type and the NOR type is reversed. Further, the outputs of the first conversion circuits CA1 and CA2 are temporarily latched and output by the latch circuits RA1 and RA2.
[0095]
Thereby, the delay time (rising time difference) τ when the output OUT rises with respect to the input signal IN as shown in FIG.₂And the delay time when falling (falling time difference) τ₁(Output signal OUT).
FIGS. 51 and 52 are circuit diagrams showing a seventh embodiment of the delay circuit of the present invention, and FIG. 53 is a waveform diagram showing the operation of the delay circuit shown in FIGS. 51 and 52.
[0096]
In the seventh embodiment shown in FIGS. 51 and 52, a plurality of (four: CB1 to CB4) second conversion circuits (CB) are provided, and the second input circuit in the second conversion circuits CB1 to CB4. The delay time at the rise of the signal CLK-B and the delay time at the fall of the second input signal CLK-B in the second conversion circuits CB1 to CB4 are set separately and in plural types. It has become.
[0097]
Then, as shown in FIG. 53, the logic of the output (node (1) to node (4)) of each of the second conversion circuits CB1 to CB4 is taken to oscillate the input signal (third input signal) IN. The frequency is changed (in this embodiment, the frequency is changed four times (constant times)). In the seventh embodiment, the output signal OUT is extracted by giving a delay time of half (τ / 2) of the time difference τ to the input signal IN.
[0098]
FIG. 54 is a circuit diagram showing an example of an array structure applied to the delay circuit of the present invention, and FIG. 55 is a circuit diagram showing another example of the array structure applied to the delay circuit of the present invention. The array structure shown in FIGS. 54 and 55 shows a configuration example of the first conversion circuit CA.
As shown in FIG. 54, the first input signal CLK-A is supplied to the first stage of the array of unit circuits UA in the first conversion circuit CA, and signal propagation is started.
[0099]
As is clear from the comparison between the unit circuits described with reference to FIGS. 55 and 38, the first input signal CLK-A is supplied to the unit circuit UA in the first conversion circuit CA by the reset signal. (RESET), and the delay generation gate in each unit circuit UA may be controlled to be in a reset state or an inverted state. In the array structure shown in FIG. 55, the input of the first-stage unit circuit UA in the first conversion circuit CA is set to a fixed level (high level “H”), and the first input signal CLK-A is inverted. When instructed, signal propagation of the array in the first conversion circuit CA is started.
[0100]
FIG. 56 is a circuit diagram showing still another example of the array structure applied to the delay circuit of the present invention, and FIG. 57 is a circuit diagram showing still another example of the array structure applied to the delay circuit of the present invention. It is. The array structure shown in FIGS. 56 and 57 shows a configuration example of the second conversion circuit CB.
As shown in FIGS. 56 and 57, the second conversion circuit CB receives the second gate stage number information (N ′ bit), gives the corresponding delay time (τ ′) to the input signal, and outputs the output signal. OUT, and includes N ′ unit circuits UB corresponding to the second gate stage number information.
[0101]
As shown in FIGS. 31 to 35 and FIGS. 40 to 53 described above, the first stage unit circuit (UB) in the second conversion circuit CB is configured as a unit circuit including an inverter type delay circuit. Further, when a long switching time difference (τ) exceeding the delay time in the first conversion circuit CA is input to the input of the first stage of the array of the unit circuits UB in the second conversion circuit CB, the gate stage number information ( N ′) may be clamped on the side to be inverted. Further, at the first stage of the array of the unit circuits UB in the second conversion circuit CB, the input may be clamped on the side where the delay circuit in the first unit circuit UB operates as an inverter.
[0102]
Further, the first and second input signals (CLK-A, CLK-B) to the first conversion circuit CA are periodically changed only once every M (for example, 8 or 16) clock switching. Then, the second gate stage number information (N ′ bit) may be regenerated. As a result, even when the master clock fluctuates, it is possible to follow the master clock. Further, if the regenerated second gate stage number information N ′ is configured to be reset when the second conversion circuit CB is not propagating the third input signal IN, other operations are not hindered. , The second gate stage number information (N ′ bit) can be regenerated.
[0103]
FIGS. 58 and 59 are circuit diagrams showing an eighth embodiment of the delay circuit of the present invention, and FIG. 60 is a waveform diagram showing the operation of the delay circuit shown in FIGS. 58 and 59.
In the eighth embodiment shown in FIGS. 58 and 59, the above-mentioned second gate stage number information N 'is regenerated by a delay time variation control circuit CD' provided between latch circuit RA and latch circuit RB. The change of the value of the second gate stage number information (N ') between the old and new at the time is reduced. That is, the logic of the output of the first and second unit circuits (UA) is taken by the delay time variation control circuit CD ', and the change in the value of the regenerated second gate stage number information (N') is gradually changed. It has become. FIG. 60 shows a state in which the second gate stage number information N ′ is regenerated and an output signal (OUT) delayed from the input signal (IN) by a time (τ) is output.
[0104]
FIGS. 61 and 62 are circuit diagrams showing a ninth embodiment of the delay circuit of the present invention, and FIG. 63 is a waveform diagram showing the operation of the delay circuit shown in FIGS. 61 and 62. The ninth embodiment shown in FIGS. 61 and 62 is a modification of the seventh embodiment shown in FIGS. 51 and 52 described above.
As shown in FIGS. 61 and 62, in the ninth embodiment, a plurality of pairs (two pairs) of second conversion circuits CB1, CB2; CB3, CB4 are provided. Of the output OUT is delayed by the conversion circuits CB1 and CB3, and the fall timing of the output OUT is delayed by the other second conversion circuits CB2 and CB4. Then, the output switching timing of the opposite output OUT is determined by another output switching timing generating means, and the outputs in the second conversion circuits CB1, CB2; CB3, CB4 and other output switching timings are generated. The output of the means is bus-connected to a composite output node. Here, the second conversion circuits CB1 and CB3 receive one gate stage number information output for two stages of each unit circuit UA of the first conversion circuit CA.
[0105]
Thereby, as shown in FIG. 63, the logic of the output (node (1) to node (4)) of each of the second conversion circuits CB1 to CB4 is taken and the input signal (third input signal) IN is obtained. A signal in which the vibration frequency is doubled is obtained. In the ninth embodiment, a delay time of half (τ / 2) of the time difference τ is given to the input signal IN, and the output signal OUT is extracted by inverting the input signal IN. I have.
[0106]
FIGS. 64 and 65 are circuit diagrams showing a tenth embodiment of the delay circuit of the present invention, and FIG. 66 is a waveform diagram showing the operation of the delay circuit shown in FIGS. 64 and 65.
As shown in FIGS. 64 and 65, in the tenth embodiment, 2M (four) second conversion circuits (CB) are provided, and as shown in FIG. It is configured to output an output signal having a frequency that is M times (2 times) IN).
[0107]
As shown in each of the embodiments described above, when two second conversion circuits (CB) are provided and the delay at the time of rising of the input and the delay at the time of falling of the input are separately formed, An output in each of the second conversion circuits (CB1 and CB2) is connected to a combined output node by a bus, and a predetermined data is supplied to an output unit in each of the second conversion circuits for a predetermined time after output switching. Is provided, and the output impedance is sufficiently increased during other periods. Specifically, for example, for the output (OUT), the latch circuit LA0 and the delay line DL0 in FIG. 31 are provided to output predetermined data only within a certain time after output switching, and to output during other periods. The high impedance state may be maintained.
[0108]
Further, a delay circuit capable of electrically controlling another type of delay time is provided in the plurality of second conversion circuits (CB), and the delay time of the second conversion circuit is reduced by controlling the delay circuit. It may be adjusted.
Also, an odd number of second conversion circuits (CB) are provided, and the input and output of each of the second conversion circuits are connected so as to form a ring oscillator, and the time set by the first conversion circuit (CA) ( τ) may be configured to have a period L / M times (L and M are integers).
[0109]
67 and 68 are circuit diagrams showing an eleventh embodiment of the delay circuit of the present invention, and FIG. 69 is a waveform diagram showing the operation of the delay circuit shown in FIGS. 67 and 68.
As shown in FIGS. 67 and 68, in the eleventh embodiment, an even number (four) of the second conversion circuits (CB1 to CB4) is provided. An odd number (one) of inverter gates is further provided, and the inputs and outputs of each of the second conversion circuits CB1, CB2; CB3, CB4 are connected to form a ring oscillator via the inverter gates. ing.
[0110]
That is, as shown in FIGS. 67 and 68, the signal OUT1 output from the second conversion circuits CB1 and CB2 is directly supplied as the input signal IN2 of the second conversion circuits CB3 and CB4, and the inverter IFD2 And supplied to the second conversion circuits CB3 and CB4 as the input signal / IN2 of the second conversion circuits CB3 and CB4. Similarly, the signal OUT2 output from the second conversion circuits CB3 and CB4 is directly supplied as the input signal / IN1 to the second conversion circuits CB1 and CB2, and is inverted by the inverter IFD1 to be inverted by the second conversion circuit. The input signals IN1 of CB1 and CB2 are supplied to the second conversion circuits CB1 and CB2. Thereby, as shown in FIG. 69, an output signal OUT (OUT1, OUT2) having a cycle of L / M times (L and M are integers) the time difference τ set by the first conversion circuit CA is obtained. be able to.
[0111]
FIGS. 70 and 71 are circuit diagrams showing a twelfth embodiment of the delay circuit of the present invention. The twelfth embodiment shown in FIGS. 70 and 71 differs from the eleventh embodiment shown in FIGS. 67 and 68 in that a fine adjustment delay circuit DA (DA1, DA2) is provided.
That is, fine adjustment delay circuits DA1 and DA2 are provided immediately before extracting the outputs OUT1 and OUT2 for each of the plurality of second conversion circuits CB1 and CB2 and CB3 and CB4. The fine adjustment delay circuits DA1 and DA2 take out the output signals OUT1 and OUT2 having the timing frequency synchronized with the third input signal IN for each of the second conversion circuits (CB1, CB2; CB3, CB4). ing.
[0112]
Here, a delay circuit capable of electrically controlling another type of delay time is provided in the second conversion circuit (CB), and the switching timing of the output of one of the second conversion circuits is determined by an external clock. The delay time of the delay circuit is controlled so as to synchronize with the signal output switching timing, and the cycle of L / M times (L and M are integers) of the time (τ) set by the first conversion circuit (CA) is set. You may comprise so that it may have. Further, a fixed-time delay circuit is provided in the second conversion circuit (CB) that reflects another type of delay time due to variations in manufacturing conditions, and the output of one of the second conversion circuits (CB) is switched. It is also possible to control the delay time of the delay circuit so that the timing is synchronized with the output switching timing of the external clock signal, and to create an internal clock that switches earlier by the fixed time than the external clock signal. it can.
[0113]
【The invention's effect】
As described above in detail, according to the timing control circuit of the present invention, the time difference τ between the switching timing of the first signal and the switching timing of the second signal is increased by N times (N is 2 or more) in the time difference expansion circuit. (Integer), it is possible to appropriately control the timing of the control signal according to the cycle of the control signal to be used.You.
[Brief description of the drawings]
FIG. 1 is a diagram showing a principle configuration of a timing control circuit according to the present invention.
FIG. 2 is a diagram for explaining a first embodiment of the timing control circuit of the present invention.
FIG. 3 is a diagram for explaining a second embodiment of the timing control circuit of the present invention.
FIG. 4 is a diagram for explaining a third embodiment of the timing control circuit of the present invention.
FIG. 5 is a diagram for explaining a fourth embodiment of the timing control circuit of the present invention.
FIG. 6 is a diagram for explaining a fifth embodiment of the timing control circuit of the present invention.
FIG. 7 is a diagram for explaining a sixth embodiment of the timing control circuit of the present invention.
FIG. 8 is a diagram for explaining a seventh embodiment of the timing control circuit of the present invention.
FIG. 9 is a diagram for explaining an eighth embodiment of the timing control circuit of the present invention.
FIG. 10 is a diagram for explaining a ninth embodiment of the timing control circuit of the present invention.
FIG. 11 is a diagram for explaining a tenth embodiment of the timing control circuit of the present invention.
FIG. 12 is a diagram for explaining an eleventh embodiment of the timing control circuit of the present invention.
FIG. 13 is a diagram for explaining a twelfth embodiment of the timing control circuit of the present invention.
FIG. 14 is a diagram for explaining a thirteenth embodiment of the timing control circuit of the present invention.
FIG. 15 is a diagram for explaining a fourteenth embodiment of the timing control circuit of the present invention.
FIG. 16 is a diagram for explaining an application example of the timing control circuit of the present invention.
FIG. 17 is a circuit diagram (part 1) illustrating an example of a clock generation circuit to which the timing control circuit of the present invention is applied.
FIG. 18 is a circuit diagram (part 2) illustrating an example of a clock generation circuit to which the timing control circuit of the present invention is applied.
FIG. 19 is a circuit diagram (part 3) showing one example of a clock generation circuit to which the timing control circuit of the present invention is applied;
FIG. 20 is a timing chart (1) showing each signal of the clock generation circuit shown in FIGS. 17 to 19;
FIG. 21 is a timing chart (part 2) showing each signal of the clock generation circuit shown in FIGS. 17 to 19;
FIG. 22 is a diagram illustrating an example of a conventional timing control circuit.
FIG. 23 is a block diagram schematically showing an example of a circuit configuration to which a timing control circuit is applied.
FIG. 24 is a diagram for explaining another example of the conventional timing control circuit.
FIG. 25 is a block diagram illustrating an example of a conventional delay circuit.
FIG. 26 is a block diagram showing another example of the conventional delay circuit.
FIG. 27 is a block diagram illustrating an example of a conventional PLL circuit.
FIG. 28 is a block diagram showing a basic configuration of a DLL circuit to which the present invention is applied.
FIG. 29 is a block diagram showing a principle configuration of a delay circuit to which the present invention is applied;
30 is a waveform diagram showing an example of a circuit for generating a clock signal in the delay circuit of FIG. 29 and its operation.
FIG. 31 is a circuit diagram showing a first embodiment of the delay circuit of the present invention.
32 is a waveform chart representing an operation of the delay circuit shown in FIG. 31.
FIG. 33 is a circuit diagram (part 1) showing a second embodiment of the delay circuit of the present invention;
FIG. 34 is a circuit diagram (part 2) showing a second embodiment of the delay circuit of the present invention.
FIG. 35 is a waveform chart representing an operation of the delay circuit shown in FIGS. 33 and 34.
FIG. 36 is a diagram showing an example of a unit circuit applied to the delay circuit of the present invention.
FIG. 37 is a diagram showing another example of the unit circuit applied to the delay circuit of the present invention.
FIG. 38 is a diagram showing still another example of the unit circuit applied to the delay circuit of the present invention.
FIG. 39 is a diagram showing still another example of the unit circuit applied to the delay circuit of the present invention.
FIG. 40 is a circuit diagram showing a third embodiment of the delay circuit of the present invention.
41 is a waveform chart representing an operation of the delay circuit shown in FIG. 40.
FIG. 42 is a circuit diagram (part 1) showing a fourth embodiment of the delay circuit of the present invention;
FIG. 43 is a circuit diagram (part 2) showing a fourth embodiment of the delay circuit of the present invention;
FIG. 44 is a waveform chart representing an operation of the delay circuit shown in FIGS. 42 and 43.
FIG. 45 is a circuit diagram (part 1) showing a fifth embodiment of the delay circuit of the present invention;
FIG. 46 is a circuit diagram (part 2) showing a fifth embodiment of the delay circuit of the present invention;
FIG. 47 is a waveform chart showing an operation of the delay circuit shown in FIGS. 45 and 46.
FIG. 48 is a circuit diagram (part 1) showing a sixth embodiment of the delay circuit of the present invention;
FIG. 49 is a circuit diagram (part 2) showing a sixth embodiment of the delay circuit of the present invention;
FIG. 50 is a waveform chart representing an operation of the delay circuit shown in FIGS. 48 and 49.
FIG. 51 is a circuit diagram (part 1) showing a seventh embodiment of the delay circuit of the present invention;
FIG. 52 is a circuit diagram (part 2) showing a seventh embodiment of the delay circuit of the present invention;
FIG. 53 is a waveform chart representing an operation of the delay circuit shown in FIGS. 51 and 52.
FIG. 54 is a circuit diagram showing an example of an array structure applied to the delay circuit of the present invention.
FIG. 55 is a circuit diagram showing another example of the array structure applied to the delay circuit of the present invention.
FIG. 56 is a circuit diagram showing still another example of the array structure applied to the delay circuit of the present invention.
FIG. 57 is a circuit diagram showing still another example of the array structure applied to the delay circuit of the present invention.
FIG. 58 is a circuit diagram (part 1) showing an eighth embodiment of the delay circuit of the present invention;
FIG. 59 is a circuit diagram (part 2) showing an eighth embodiment of the delay circuit of the present invention;
FIG. 60 is a waveform chart representing an operation of the delay circuit shown in FIGS. 58 and 59.
FIG. 61 is a circuit diagram (part 1) showing a ninth embodiment of the delay circuit of the present invention;
FIG. 62 is a circuit diagram (part 2) showing a ninth embodiment of the delay circuit of the present invention;
FIG. 63 is a waveform chart showing an operation of the delay circuit shown in FIGS. 61 and 62.
FIG. 64 is a circuit diagram (part 1) showing a tenth embodiment of the delay circuit of the present invention;
FIG. 65 is a circuit diagram (part 2) showing a tenth embodiment of the delay circuit of the present invention;
FIG. 66 is a waveform chart representing an operation of the delay circuit shown in FIGS. 64 and 65.
FIG. 67 is a circuit diagram (part 1) showing an eleventh embodiment of the delay circuit of the present invention;
FIG. 68 is a circuit diagram (part 2) showing an eleventh embodiment of the delay circuit of the present invention;
FIG. 69 is a waveform chart representing an operation of the delay circuit shown in FIGS. 67 and 68.
FIG. 70 is a circuit diagram (part 1) of a delay circuit according to a twelfth embodiment of the present invention;
FIG. 71 is a circuit diagram (part 2) showing a twelfth embodiment of the delay circuit of the present invention;
[Explanation of symbols]
1. First circuit (input buffer circuit)
2. Second circuit (delay circuit)
3: Time difference expansion circuit
4: Signal transmission section (long wiring delay)
5 Output buffer
21 ... Delay circuit (long wiring delay)
22 ... Delay circuit
23 ... Output buffer circuit
24 ... Delay circuit (output decision time setting circuit)
AA: First gate row
BB: second gate row
CLK-A: First input signal
CLK-B... Second input signal
CA: first conversion circuit
CB: second conversion circuit
CD: Gate stage number information conversion circuit
IN: third input signal
N: First gate stage number information
N ': second gate stage number information
UA: first unit circuit
UB: second unit circuit
X: first control signal
Y: second control signal
τ: first switching time difference (time difference)
τ ': Second switching time difference

Claims (8)

A first delay circuit for receiving a clock signal;
A variable delay circuit that receives the clock signal and the clock signal from the first delay circuit, and delays the clock signal from the first delay circuit, wherein the clock signal from the first delay circuit is input A variable delay circuit having a delay time obtained by multiplying the time difference between the transition of the clock signal and the transition of the clock signal by N times (N is an integer of 2 or more);
A second delay circuit connected in series with the first delay circuit and the variable delay circuit,
A timing control circuit for generating a control clock signal having a certain time difference from the clock signal. 2. The timing control circuit according to claim 1, wherein said N is 2. 2. The timing control circuit according to claim 1, wherein the delay time of the first delay circuit is equal to the delay time of the second delay circuit. 2. The timing control circuit according to claim 1, wherein the timings of the clock signal and the control clock signal match. 2. The timing control circuit according to claim 1, wherein the first delay circuit has a delay time equal to a sum of delay times of an input buffer, a wiring delay, and an output buffer. 2. The timing control circuit according to claim 1, wherein a delay time of said second delay circuit is shorter than a delay time of said first delay circuit. 2. The timing control circuit according to claim 1, wherein a delay time of said second delay circuit is shorter than a delay time of said first delay circuit by a delay time of an output buffer. An electronic circuit, comprising: an output buffer circuit to which the control clock signal according to claim 1 is supplied, wherein the output buffer circuit outputs a signal in response to the control clock signal.

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