CN106655757B

CN106655757B - Capacitive charge pump

Info

Publication number: CN106655757B
Application number: CN201510746026.5A
Authority: CN
Inventors: 赵海亮; 陶园林; 常祥林; 谢雪松; 孙彪
Original assignee: Shanghai Beiling Co Ltd
Current assignee: Shanghai Beiling Co Ltd
Priority date: 2015-11-04
Filing date: 2015-11-04
Publication date: 2020-06-05
Anticipated expiration: 2035-11-04
Also published as: CN106655757A

Abstract

The invention discloses a capacitive charge pump which comprises a charging capacitor, a first switching device and a switch driving circuit, wherein the input of one end of the first switching device is an input power supply signal, the other end of the first switching device is connected with the charging capacitor, the switch driving circuit further comprises a transconductance linear ring and a current bias circuit, the output signal of the current bias circuit is connected to one end of the transconductance linear ring, the other end of the transconductance linear ring is connected with a NOT gate of the switch driving circuit, and the NOT gate outputs a switch control signal to the first switching device. The capacitor type charge pump provided by the invention is additionally provided with the transconductance linear ring and the current bias circuit, and the low level voltage of the first switching device of the capacitor type charge pump can be controlled not to obviously change along with the change of the input voltage, so that the functions of controlling the driving capability of the capacitor type charge pump and reducing the ripple waves of the output voltage are realized, and the power supply quality of the output voltage of the capacitor type charge pump is further improved.

Description

Capacitive charge pump

Technical Field

The invention belongs to the field of integrated circuit design, and particularly relates to a capacitive charge pump.

Background

The capacitor type charge pump (charge pump) is a DC/DC converter, and when it is operated, it firstly utilizes capacitor device to store energy, then releases the energy under the control of control circuit, and the released charge can be redistributed to implement voltage conversion, and possesses the characteristics of turning over voltage and voltage multiplication. Fig. 1 shows a conventional 2-time voltage capacitive charge pump. The Cbypass capacitor 801, the PMOS tube 1, the PMOS tube 2, the PMOS tube 3, the NMOS tube 4, the Cfly capacitor and the Cload capacitor form a main structure of the capacitance charge pump. K1, K2, K3 and K4 are the grid driving signals of PMOS tube 1, PMOS tube 2, PMOS tube 3 and NMOS tube 4 respectively, when PMOS tube 1 and NMOS tube 4 are conducted and PMOS tube 2 and PMOS tube 3 are disconnected, the input power voltage VIN starts to charge the capacitor Cfly, the potential at the point S1 is VIN, and the potential at the point S2 is 0V. If the PMOS transistor 1 and the NMOS transistor 4 are turned off, the PMOS transistor 2 and the PMOS transistor 3 are turned on, and the potential at the point S2 is raised to VDD, and due to the bootstrap property of the capacitor, the potential at the point S1 is raised. Under the control of the control signal, the switch is continuously closed and opened, the potential of the Vout point continuously rises, and ideally reaches 2VDD, that is, Vout is 2VDD, so that the voltage doubling effect is achieved.

The circuit 300 in fig. 1 is an output voltage Vout detection circuit. The output voltage Vout is divided by resistors R1 and R2, an appropriate voltage is extracted and compared with a reference voltage VBGR by a comparator 301, and the comparison result is sent to the control logic circuit 200. When the extracted voltage is smaller than the reference voltage VBGR, the logic circuit can control the capacitor charge pump to work; when the extracted voltage is equal to or greater than the reference voltage VBGR, the logic circuit controls the capacitor charge pump to stop working, namely the levels of K1, K2, K3 and K4 are kept unchanged; when the pumped voltage drops below the reference voltage VBGR again due to the supply of power to the load, the logic circuit 200 again controls the capacitor charge pump to operate again. The two-phase non-overlap clock circuit 700 is a gate drive generation circuit for charge pump switches that converts the input clock signal into non-overlapping control signals K1, K2, K3, and K4.

In the prior art, the capacitive charge pump has the problem of large output ripple when the input voltage variation range is large and the load current is large, which can seriously reduce the power supply quality of the output voltage of the capacitive charge pump.

Disclosure of Invention

The invention provides a capacitive charge pump with small output ripple, aiming at overcoming the defect that the capacitive charge pump in the prior art has large input voltage variation range and large output voltage ripple when the load current is large.

The invention solves the technical problems through the following technical scheme:

a capacitance type charge pump comprises a charging capacitor 802, a first switch device 1 and a switch driving circuit, wherein an input of one end of the first switch device 1 is an input power signal, and the other end of the first switch device 1 is connected with the charging capacitor 802, and the capacitance type charge pump is characterized by further comprising a transconductance linear loop and a current bias circuit, an output signal of the current bias circuit is connected to one end of the transconductance linear loop, the other end of the transconductance linear loop is connected with a NOT gate of the switch driving circuit, and the NOT gate outputs a switch control signal to the first switch device 1.

In this scheme, the current bias circuit controls the current of the linear transconductance loop to realize that the low-level voltage of the first switching device 1 does not change significantly with the change of the input power supply voltage VIN. That is, in the case that the variation range of the input power supply voltage VIN is large, the amount of charge transferred to the output voltage by the capacitive charge pump per cycle is fixed, that is, the driving capability is fixed, so that only the output voltage ripple is controlled. Without this control mechanism, the driving capability can be strong, but the ripple on the output voltage can be large.

Preferably, the switch driving circuit further includes an input power detection circuit, and an output signal of the input power detection circuit controls the other end of the transconductance linear loop to be grounded.

In this scheme, when the input power supply voltage VIN is lower than a certain threshold, the input power supply detection circuit outputs a signal to ground the other end of the transconductance linear loop, so that the current bias circuit and one end of the transconductance linear loop do not function, that is, the driving capability limitation is released.

Preferably, the transconductance linear loop comprises a first PMOS transistor 17, a second PMOS transistor 11, a first NMOS transistor 12 and a second NMOS transistor 18, a gate and a drain of the first PMOS transistor 17 are connected to a gate of the first NMOS transistor 12, and a source of the first PMOS transistor 17 and a drain of the first NMOS transistor 12 are connected to an input power supply; the source of the first NMOS tube 12 is connected to the gate of the second PMOS tube 11, the drain of the second PMOS tube 11 is grounded, the source of the second PMOS tube 11 is connected to the source of the second NMOS tube 18, and the drain of the second NMOS tube 18 is used to drive the not gate of the switch driving circuit; the output end of the current bias circuit is connected with the grid electrode of the first PMOS tube 17, and the other output end of the current bias circuit is connected with the source electrode of the first NMOS tube 12.

In this embodiment, the relationship is | VGS17| + VGS12 | + VGS11| + VGS18, where VGS is the source and gate voltage. Therefore, as long as the voltage rejection ratio (PSRR) of the current bias circuit is high, | VGS17| + VGS12 is a stable value in the case where the input power supply voltage VIN varies widely, it is determined that | VGS11| + VGS18 is stable. Therefore, the low level voltage of the first switching device 1 does not change significantly with the change of the input voltage VIN.

Preferably, the input power detection circuit includes a third NMOS transistor 14, a drain of the third NMOS transistor 14 is connected to a source of the second NMOS transistor 18, and a source of the third NMOS transistor 14 is grounded.

Preferably, the capacitive charge pump further comprises a second switching device 2, a third switching device 3 and a fourth switching device 4; the switch driving circuit comprises two cascaded two-phase non-overlapping clock circuits, wherein one two-phase non-overlapping clock circuit outputs switch control signals to the first switch device 1 and the fourth switch device 4, and the other two-phase non-overlapping clock circuit outputs switch control signals to the second switch device 2 and the third switch device 3; the first switching device 1 and the fourth switching device 4 cannot be turned on simultaneously; the second switching device 2 and the third switching device 3 cannot be turned on simultaneously.

In the scheme, two sets of cascaded two-phase non-overlapping clock circuits can control the turn-on and turn-off time sequences of the first switching device 1 to the fourth switching device 4, so that the situations that the first switching device 1 and the fourth switching device 4 are simultaneously turned on and the second switching device 2 and the third switching device 3 are simultaneously turned on are avoided, and the normal charge and discharge of the capacitive charge pump are ensured.

Preferably, the capacitive charge pump further comprises an output reference voltage generating circuit 400 and an output ripple control circuit 500; the input end of the output reference voltage generating circuit 400 is connected to one end of the second switching device 2 away from the input power supply; the first reference voltage VTH1 and the second reference voltage VTH2 output by the output reference voltage generation circuit 400 are respectively connected to two voltage input terminals of the output ripple control circuit 500.

In this embodiment, the output reference voltage generating circuit 400 generates two reference voltages from the voltage Vout1 output from the source terminal of the second NMOS transistor 18, and sends the two reference voltages to the output ripple control circuit 500, and the output ripple control circuit 500 generates a further output voltage Vout _ inter according to the two received reference voltages.

Preferably, the output reference voltage generating circuit 400 includes a first current source 401, a first resistor and a second resistor connected in series in sequence, a current input end of the first current source 401 is connected to one end of the second switching device 2 away from the input power source, and the second resistor is grounded.

Preferably, the output ripple control circuit 500 includes a first operational amplifier 501, a second operational amplifier 502, a second current source 503, a third PMOS transistor 20 and a fourth NMOS transistor 21, an input signal of an inverting terminal of the first operational amplifier 501 is the first reference voltage, and an input signal of a non-inverting terminal of the second operational amplifier 502 is the second reference voltage; the output end of the first operational amplifier 501 is connected to the gate of the third PMOS transistor 20, the source of the third PMOS transistor 20 is connected to the end of the second switching device 2 away from the input power supply, and the inverting terminal of the second operational amplifier 502, the drain of the fourth NMOS transistor 21, the in-phase terminal of the first operational amplifier 501 and the current input end of the second current source 503 are connected; the output end of the second operational amplifier 502 is connected to the gate of the fourth NMOS transistor 21, and the source of the fourth NMOS transistor 21 and the current outflow end of the second current source 503 are grounded.

In the scheme, when the Vout _ inter is lower than a set first reference VTH1, the third PMOS tube 20 is switched on, and the fourth NMOS tube 21 is switched off to charge the load; when the Vout _ inter is higher than a set second VTH2, the third PMOS tube 20 is turned off, and the fourth NMOS tube 21 is turned on, thereby discharging the Vout _ inter; when VTH1< Vout _ inter < VTH2, the third PMOS transistor 20 is turned off, and the fourth NMOS transistor 21 is turned off.

Preferably, the capacitive charge pump further comprises an output voltage slope control circuit 600, the output voltage slope control circuit 600 comprises a third operational amplifier 601, a fourth PMOS transistor 22, a charging current source 602, a discharging current source 603, a single-pole double-throw switch 604 and a slope control capacitor 803, the source of the fourth PMOS transistor 22 is connected to the output end of the output ripple control circuit 500, the non-inverting terminal of the third operational amplifier 601 and the drain of the fourth PMOS transistor 22 are grounded via a capacitor, the current input terminal of the charging current source 602 is connected to the terminal of the second switching device 2 remote from the input power source, the current outflow end of the discharging current source 603 is grounded, one end of the slope control capacitor 803 is grounded, the current outflow terminal of the charging current source 602 and the current input terminal of the discharging current source 603 are alternatively connected to the other terminal of the slope control capacitor 803 and the inverting terminal of the third operational amplifier 601 through the single-pole double-throw switch 604.

In this scheme, the output voltage slope control circuit is used for controlling the slope of the output voltage Vout2 of the circuit when the output voltage is powered on or powered off. At the rising edge, the charging current source 602 charges the slope control capacitor 803, controls the rising slope of the end of the slope control capacitor 803 far away from the ground, and controls the output voltage Vout2 to follow the voltage of the end of the slope control capacitor 803 far away from the ground through the third operational amplifier 601 and the fourth PMOS transistor 22.

Preferably, the first switch device, the second switch device and the third switch device are PMOS transistors, and the fourth switch device is an NMOS transistor.

The positive progress effects of the invention are as follows: the capacitor type charge pump provided by the invention is additionally provided with the transconductance linear ring and the current bias circuit on the basis of the existing charge pump, and the low level voltage of the first switching device of the capacitor type charge pump can be controlled not to obviously change along with the change of the input voltage, so that the functions of controlling the driving capability of the capacitor type charge pump and reducing the ripple waves of the output voltage are realized, and the power supply quality of the output voltage of the capacitor type charge pump is further improved.

Drawings

Fig. 1 is a schematic circuit diagram of a capacitive charge pump in the prior art.

Fig. 2 is a schematic circuit diagram of a capacitive charge pump according to a preferred embodiment of the invention.

Fig. 3 is a timing diagram of four driving signals of the capacitive charge pump according to the embodiment of the invention.

Detailed Description

The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.

As shown in fig. 2, a capacitive charge pump includes a charging capacitor 802, a first switching device 1, a second switching device 2, a third switching device 3, and a fourth switching device 4, an output voltage detection circuit 300, a control logic circuit 200, an output reference voltage generation circuit 400, an output ripple control circuit 500, an output voltage slope control circuit 600, and a switch driving circuit 100. The switch driving circuit 100 includes two cascaded two-phase non-overlapping clock circuits, a transconductance linear loop, a current bias circuit, and an input power detection circuit. The first switching device 1, the second switching device 2 and the third switching device 3 are all PMOS transistors, and the fourth switching device 4 is an NMOS transistor.

The drain of the first switching device 1 is connected to the input power signal VIN and the drain of the third switching device 3, the source of the first switching device 1 is connected to one end of the charging capacitor 802, namely Cfly, and the drain of the fourth switching device 4, the source of the third switching device 3 is connected to the other end of Cfly and the drain of the second switching device, and the source of the second switching device 2 outputs Vout 1. Vout1 is used as the input voltage for the output voltage detection circuit 300, the output reference voltage generation circuit 400, and the output voltage slope control circuit 600. The control logic circuit 200 receives the signal output by the output voltage detection circuit 300 and outputs a control signal to the first stage two-phase non-overlap clock circuit of the switch driving circuit 100.

The switch driving circuit 100 adopts a NAND gate to realize two-phase non-overlapping clock signals, and adopts two sets of nestings, wherein the first-stage two-phase non-overlapping clock circuit of the two sets of nestings comprises a phase inverter 102, a phase inverter 103, a phase inverter 104, a phase inverter 108, a phase inverter 111, a phase inverter 112, a NAND gate 101, a NAND gate 109, a phase inverter consisting of a PMOS tube 24 and an NMOS tube 23, and a phase inverter consisting of a PMOS tube 19 and an NMOS tube 18; the second stage of the two-phase non-overlapping clock circuit comprises an inverter 106, an inverter 107, an inverter 113, an inverter 114, an inverter 115, an inverter 116, a nand gate 105 and a nand gate 114. Wherein the output of the inverter 102 is used for driving the K4 signal of the gate of the fourth switching device 4, the drain of the NMOS transistor 18 is used for driving the K1 signal of the gate of the first switching device 1, the output of the inverter 107 is used for driving the K3 signal of the gate of the third switching device 3, and the output of the inverter 116 is used for driving the K2 signal of the gate of the second switching device 2.

The timing relationships among the four corresponding driving signals K3, K2, K1 and K4 are shown in FIG. 3:

1) the PMOS transistor 1 and the NMOS transistor 4 cannot be turned on simultaneously, that is, K1 is "0" and K4 is "1";

2) PMOS transistor 3 and PMOS transistor 2 cannot be turned on simultaneously, that is, K3 is "0" and K2 is "0";

3) when the charging phase is entered, the NMOS tube 4 is firstly switched on, and the PMOS tube 3 is switched on later, namely, the rising edge comes first from K4, and the falling edge comes next from K3;

4) when the charging phase is exited, the PMOS tube 3 is disconnected firstly, the NMOS tube 4 is disconnected later, namely the rising edge of K3 comes first, and the falling edge of K4 comes later;

5) when the discharge phase is entered, the PMOS tube 1 is firstly connected, and the PMOS tube 2 is connected later, namely K1 comes first to fall, and K2 comes second to fall;

6) when the discharge phase is exited, the PMOS transistor 2 is turned off first, and the PMOS transistor 1 is turned off later, namely, the rising edge of K2 comes first and the rising edge of K1 comes later.

In this embodiment, the PMOS transistor 6, the PMOS transistor 7, the PMOS transistor 5, the NMOS transistor 8, the NMOS transistor 9, and the NMOS transistor 10 are current bias circuits, and the PMOS transistor 17, the NMOS transistor 12, the NMOS transistor 18, and the PMOS transistor 11 form a linear transconductance loop. The grid and the drain of the PMOS tube 17 are connected with the grid of the NMOS tube 12, and the source of the PMOS tube 17 and the drain of the NMOS tube 12 are connected with an input power supply; the source electrode of the NMOS tube 12 is connected with the grid electrode of the PMOS tube 11, the drain electrode of the PMOS tube 11 is grounded, and the source electrode of the PMOS tube 11 is connected with the source electrode of the NMOS tube 18; the drain electrode of the NMOS tube 9 of the current bias circuit is connected with the grid electrode of the PMOS tube 17, and the drain electrode of the NMOS tube 10 is connected with the source electrode of the NMOS tube 12. There is a relationship of | VGS17| + VGS12 | + VGS18 | VGS11| + VGS. Therefore, as long as the voltage rejection ratio (PSRR) of the current bias circuit is high, | VGS17| + VGS12 is a stable value in the case where the input power supply voltage VIN varies widely, it is determined that | VGS11| + VGS18 is stable. Therefore, the low level voltage at the node of the K1 signal does not change significantly with the change of the input voltage VIN. Thus, under the condition that the input power supply voltage VIN is changed in a large range, the amount of charge transferred to the output by the capacitive charge pump in each period is fixed, namely the driving capability is fixed. This only controls the output voltage ripple well. Without this control mechanism, the driving capability can be strong, but the ripple seen on the output voltage can be large. The present embodiment controls the driving capability and the output voltage ripple of the capacitive charge pump by controlling the low level voltage of the node pulse where the K1 signal is located and the pull-down discharge rate.

The input power detection circuit in this embodiment includes a PMOS transistor 5, an NMOS transistor 16, an NMOS transistor 15, an NMOS transistor 13, an NMOS transistor 14, a phase inverter 117, and a phase inverter 118. The drain of the NMOS transistor 14 is connected to the source of the NMOS transistor 18, and the source of the NMOS transistor 14 is grounded. And when the input power supply voltage VIN is lower than a certain threshold value, releasing the driving capability limitation. When the input power voltage VIN is lowered, the node L1 is lowered, so that the node L2 is raised, the node L3 is lowered, and the node L4 is raised, thereby finally turning on the NMOS transistor 14, so as to short-circuit the PMOS transistor 11, and the low level of the node where the K1 signal is located is pulled to GND, thereby releasing the driving capability limitation.

The output reference voltage generating circuit 400 in this embodiment includes a current source 401, a first resistor R3 and a second resistor R4 connected in series in sequence, wherein a current input terminal Vout1 of the current source 401 is connected, and the second resistor R4 is grounded.

In this embodiment, the output ripple control circuit 500 includes a first operational amplifier 501, a second operational amplifier 502, a second current source 503, a third PMOS transistor 20 and a fourth NMOS transistor 21, an input signal of an inverting terminal of the first operational amplifier 501 is a first reference voltage VTH1, and an input signal of a non-inverting terminal of the second operational amplifier 502 is a second reference voltage VTH 2; the output end of the first operational amplifier 501 is connected with the gate of a third PMOS transistor 20, the source of the third PMOS transistor 20 is connected with Vout1, the inverting end of the second operational amplifier 502, the drain of a fourth NMOS transistor 21, the in-phase end of the first operational amplifier 501 and the current input end of a second current source 503; the output end of the second operational amplifier 502 is connected to the gate of the fourth NMOS transistor 21, and the source of the fourth NMOS transistor 21 and the current outflow end of the second current source 503 are grounded. When Vout _ inter is lower than the set VTH1, the PMOS tube 20 is switched on, the NMOS tube 21 is switched off, and the load is charged; when Vout _ inter is higher than the set VTH2, the PMOS tube 20 is turned off, the NMOS tube 21 is turned on, and the output is discharged; when VTH1< Vout _ inter < VTH2, PMOS transistor 20 is turned off, NMOS transistor 21 is turned off.

The output voltage slope control circuit 600 in this embodiment includes a third operational amplifier 601, a fourth PMOS transistor 22, a charging current source 602, a discharging current source 603, a single-pole double-throw switch 604, and a slope control capacitor 803, wherein a source of the fourth PMOS transistor 22 is connected to an output terminal of the output ripple control circuit 500, a non-inverting terminal of the third operational amplifier 601 and a drain of the fourth PMOS transistor 22 are grounded via a capacitor Cload2, a current input terminal of the charging current source 602 is connected to a Vout1, a current outflow terminal of the discharging current source 603 is grounded, one end of the slope control capacitor 803 is grounded, and a current outflow terminal of the charging current source 602 and a current input terminal of the discharging current source 603 are alternatively connected to the other end of the slope control capacitor 803 and an inverting terminal of the third operational amplifier 601 through the single-pole double-throw switch 604. At the rising edge, the capacitor Cslew is charged by the charging current source 602, the rising slope of the node L5 is controlled, and the output voltage Vout2 is controlled to follow the voltage of the node L5 through the third operational amplifier 601 and the fourth PMOS transistor 22.

While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims

1. A capacitance type charge pump comprises a charging capacitor (802), a first switch device (1) and a switch driving circuit, wherein the input of one end of the first switch device (1) is an input power supply signal, the other end of the first switch device (1) is connected with the charging capacitor (802), the capacitance type charge pump is characterized by further comprising a transconductance linear loop and a current bias circuit, the output signal of the current bias circuit is connected to one end of the transconductance linear loop, the other end of the transconductance linear loop is connected with a NOT gate of the switch driving circuit, and the NOT gate outputs a switch control signal to the first switch device (1);

the transconductance linear ring comprises a first PMOS (P-channel metal oxide semiconductor) tube (17), a second PMOS tube (11), a first NMOS (N-channel metal oxide semiconductor) tube (12) and a second NMOS tube (18), wherein the grid electrode and the drain electrode of the first PMOS tube (17) are connected with the grid electrode of the first NMOS tube (12), and the source electrode of the first PMOS tube (17) and the drain electrode of the first NMOS tube (12) are connected with an input power supply; the source electrode of the first NMOS tube (12) is connected with the grid electrode of the second PMOS tube (11), the drain electrode of the second PMOS tube (11) is grounded, the source electrode of the second PMOS tube (11) is connected with the source electrode of the second NMOS tube (18), and the drain electrode of the second NMOS tube (18) is used for driving the NOT gate of the switch driving circuit.

2. The capacitive charge pump of claim 1, wherein the switch driver circuit further comprises an input power supply detection circuit, an output signal of the input power supply detection circuit controlling the other end of the transconductance linear loop to ground.

3. The capacitive charge pump according to claim 2, wherein an output terminal of the current bias circuit is connected to the gate of the first PMOS transistor (17), and another output terminal of the current bias circuit is connected to the source of the first NMOS transistor (12).

4. The capacitive charge pump of claim 3, wherein the input power detection circuit comprises a third NMOS transistor (14), a drain of the third NMOS transistor (14) is connected to a source of the second NMOS transistor (18), and a source of the third NMOS transistor (14) is grounded.

5. The capacitive charge pump according to any of the claims 1 to 4, characterized in that it further comprises a second switching device (2), a third switching device (3) and a fourth switching device (4); the switch driving circuit comprises two cascaded two-phase non-overlapping clock circuits, wherein one two-phase non-overlapping clock circuit outputs switch control signals to the first switch device (1) and the fourth switch device (4), and the other two-phase non-overlapping clock circuit outputs switch control signals to the second switch device (2) and the third switch device (3); the first switching device (1) and the fourth switching device (4) cannot be turned on simultaneously; the second switching device (2) and the third switching device (3) cannot be switched on simultaneously.

6. The capacitive charge pump according to claim 5, further comprising an output reference voltage generation circuit (400) and an output ripple control circuit (500); the input end of the output reference voltage generating circuit (400) is connected to one end, far away from an input power supply, of the second switching device (2); the first reference voltage and the second reference voltage output by the output reference voltage generating circuit (400) are respectively connected to two voltage input ends of the output ripple control circuit (500).

7. The capacitive charge pump according to claim 6, wherein the output reference voltage generating circuit (400) comprises a first current source (401), a first resistor and a second resistor connected in series in sequence, wherein a current input terminal of the first current source (401) is connected to a terminal of the second switching device (2) away from an input power source, and the second resistor is grounded.

8. The capacitive charge pump according to claim 6, wherein the output ripple control circuit (500) comprises a first operational amplifier (501), a second operational amplifier (502), a second current source (503), a third PMOS transistor (20) and a fourth NMOS transistor (21), an input signal at an inverting terminal of the first operational amplifier (501) is the first reference voltage, and an input signal at a non-inverting terminal of the second operational amplifier (502) is the second reference voltage; the output end of the first operational amplifier (501) is connected with the gate of the third PMOS tube (20), the source of the third PMOS tube (20) is connected with one end, far away from an input power supply, of the second switching device (2), and the inverting end of the second operational amplifier (502), the drain of the fourth NMOS tube (21), the in-phase end of the first operational amplifier (501) and the current input end of the second current source (503) are connected to serve as the output end of the output ripple control circuit (500); the output end of the second operational amplifier (502) is connected with the grid electrode of the fourth NMOS tube (21), and the source electrode of the fourth NMOS tube (21) and the current outflow end of the second current source (503) are grounded.

9. The capacitive charge pump according to claim 8, further comprising an output voltage slope control circuit (600), wherein the output voltage slope control circuit (600) comprises a third operational amplifier (601), a fourth PMOS transistor (22), a charging current source (602), a discharging current source (603), a single-pole double-throw switch (604), and a slope control capacitor (803), a source of the fourth PMOS transistor (22) is connected to an output terminal of the output ripple control circuit (500), a non-inverting terminal of the third operational amplifier (601) and a drain of the fourth PMOS transistor (22) are grounded via capacitors, a current input terminal of the charging current source (602) is connected to a terminal of the second switching device (2) away from an input power source, a current output terminal of the discharging current source (603) is grounded, and a terminal of the slope control capacitor (803) is grounded, the current outflow end of the charging current source (602) and the current input end of the discharging current source (603) are alternatively connected with the other end of the slope control capacitor (803) and the inverting end of the third operational amplifier (601) through the single-pole double-throw switch (604).

10. The capacitive charge pump of any of claims 6 to 9, wherein the first, second and third switching devices are PMOS transistors and the fourth switching device is an NMOS transistor.