JP2005204366A - Dc-dc converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DC-DC converter capable of enhancing power conversion efficiency while reducing the design area furthermore. <P>SOLUTION: The DC-DC converter comprises MOS transistors SW1-SW4 for switching, a capacitor C1, and level shifters LS1' and LS2' arranged such that the MOS transistors SW1-SW4 are turned on/off to charge the capacitor C1 with the input voltage and a desired output voltage is obtained through the utilization of the charging voltage. Based on the source voltage of the MOS transistor SW1, the level shifter LS1' generates an on/off control signal ΦSW1 of the MOS transistor SW1. Based on the source voltage of the MOS transistor SW2, the level shifter LS2' generates an on/off control signal ΦSW2 of the MOS transistor SW2. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a DC-DC converter that is used in, for example, a power source for a liquid crystal panel and converts it into an arbitrary output DC voltage based on an input DC voltage.

Conventionally, a charge pump type DC-DC converter is known as an example of this type of DC-DC converter (see, for example, Patent Document 1).
Further, as an example of another conventional one-stage charge pump type DC-DC converter, the one shown in FIG. 6 is known.
As shown in FIG. 6, the DC-DC converter includes two types of capacitors C1 and C2, switching MOS transistors SW1 to SW4 connecting the capacitors, level shifters LS1 and LS2, and a timing signal generation circuit TG1. Is done.

The capacitor C1 is a charge transfer capacitor, and the capacitor C2 is a smoothing capacitor. The MOS transistors SW1, SW2, and SW3 are P-type MOS transistors, and the MOS transistor SW4 is an N-type MOS transistor.
This DC-DC converter controls the MOS transistors SW1 to SW4 on and off by a signal output from the timing signal generation circuit TG1. Then, by the on / off control, electric charge is transferred from the capacitor C1 to the capacitor C2, voltage conversion is performed, and when the input voltage is VDD, an output voltage of 2VDD can be ideally obtained.

The MOS transistors SW3 and SW4 can be controlled to be turned on / off by the input voltage VDD, and low-voltage MOS transistors having resistance to the input voltage VDD can be used. However, when the maximum output voltage 2VDD is higher than the withstand voltage of the low withstand voltage MOS transistor, the MOS transistors SW1 and SW2 need to use high withstand voltage MOS transistors with output voltage tolerance.
Since the MOS transistors SW1 and SW2 need to be turned on / off by the output voltage VOUT, the level of the signal output from the timing signal generation circuit TG1 is shifted by the level shifters LS1 and LS2 as shown in FIG. Control.

As shown in FIG. 7, the level shifter includes MOS transistors L1 to L4 that convert a signal at an input voltage VDD level to a signal at an output voltage VOUT level, and MOS transistors L5 and L6 that allow a large output current to flow. .
Here, the MOS transistors L1, L3, and L5 are P-type MOS transistors, and the MOS transistors L2, L4, and L6 are N-type MOS transistors. Further, as the MOS transistors L1 to L6, high voltage MOS transistors having output voltage tolerance are used.

Next, the operation of the conventional DC-DC converter having such a configuration will be described with reference to FIGS.
The timing signal generation circuit TG1 shown in FIG. 6 includes timing signals Φ1 and Φ2 that are no overlap clocks and a timing signal Φ1B obtained by inverting the timing signals to prevent a reverse current flowing from the capacitor C2 toward the capacitor C1. Φ2B is generated respectively.
The timing signal Φ1 becomes a control signal (ON / OFF control signal) for the MOS transistor SW4. Further, the timing signals Φ1 and Φ1B are input to the level shifter LS1, and the voltage is level-shifted to become the control signal ΦSW1 of the MOS transistor SW1.

The timing signal Φ2 is a control signal for the MOS transistor SW3. Further, the timing signals Φ2 and Φ2B are input to the level shifter LS2 and the voltage is level-shifted to become the control signal ΦSW2 for the MOS transistor SW2.
Such control signals Φ1, Φ2, ΦSW1, and ΦSW2 are supplied to the gates of the MOS transistors, whereby the MOS transistors are turned on and off. A waveform example of each of the control signals Φ1, Φ2, ΦSW1, and ΦSW2 is as shown in FIG.

Next, a specific example of the on / off control operation of each MOS transistor by the control signals Φ1, Φ2, ΦSW1, and ΦSW2 will be described with reference to FIG.
In the period T1 ′ shown in FIG. 8, the MOS transistors SW1 and SW4 are turned on and the MOS transistors SW2 and SW3 are turned off. At this time, the capacitor C1 is charged by the input voltage VDD, the potential VC1 + on one end side of the capacitor C1 becomes VDD as shown in FIG. 8B, and the potential VC1- on the other end side of the capacitor C1 is shown in FIG. As shown in FIG.

  In the initial state until the output voltage VOUT is boosted to the potential VC1 + on one end side of the capacitor C1, since the MOS transistor SW2 is a P-type MOS transistor, the PN junction between its drain and well becomes a forward bias. . For this reason, the output voltage VOUT is a potential that is lowered from the potential VC1 + on one end side of the capacitor C1 by the forward voltage of the diode of the PN junction. After the output voltage VOUT is boosted above the VDD of the potential VC1 + on one end side of the capacitor C1, there is no charge movement between the capacitor C1 and the capacitor C2, and the voltage does not change.

  On the other hand, in the period T2 'shown in FIG. 8, the MOS transistors SW2 and SW3 are turned on and the MOS transistors SW1 and SW4 are turned off. At this time, the potential VC1- on the other end side of the capacitor C1 becomes the input voltage VDD. On the other hand, the potential VC1 + on the one end side of the capacitor C1 is a voltage 2VDD which is the sum of the charging voltage VDD of the capacitor C1 and the potential VC1- (VDD). At the same time, the charge of the capacitor C1 moves to the capacitor C2, and the output voltage VOUT becomes 2VDD.

  In this manner, by repeating the operations in the period T1 'and the period T2', the output voltage VOUT is boosted to a voltage (2VDD) that is twice the input voltage VDD when the resistance of the MOS transistor or the like is ignored. Further, in the period T0 'shown in FIG. 8, the MOS transistors SW1 to SW4 are turned off, and charge transfer between the capacitors C1 and C2 is eliminated. Therefore, when the period T1 'and the period T2' are switched, no reverse current flows from the capacitor C2 toward the capacitor C1, and the power conversion efficiency does not decrease.

Next, the case where the constant current IOUT flows through the output after the output voltage has been boosted to 2VDD will be described.
In the period T1 shown in FIG. 8, since the control state is the same as that in the period T1 ′, and the output voltage VOUT is higher than the potential VDD of VC1 +, no charge is transferred between the capacitor C1 and the capacitor C2. The output voltage VOUT decreases from 2VDD due to the decrease in the charge stored in the capacitor C2 as the output current (see FIG. 8).

Further, in the period T2 shown in FIG. 8, the control state is the same as that in the period T2 ′, the charge moves from the capacitor C1 to the capacitor C2, and the output voltage is boosted to 2VDD. At the same time, the electric charge flowing out as the output current also moves from the capacitor C1.
Such operations in the period T1 and the period T2 are repeated, and the output voltage is stabilized with a constant voltage drop from 2VDD. Further, in the period T0 shown in FIG. 8, the switch MOS transistors SW1 to SW4 are turned off, and charge transfer between the capacitors C1 and C2 is eliminated. Therefore, when the period T1 ′ and the period T2 ′ are switched, no reverse current flows from the capacitor C2 toward the capacitor C1, and the power conversion efficiency does not decrease.

The input current of this circuit is the current from the input voltage VDD and the current supplied from the timing signal generation circuit. When the output current IOUT flows in a stable state, refer to FIGS. 8 and 9 for the current flowing in the circuit. To explain.
In the period T1, if the charge / discharge current to the parasitic capacitance is ignored, an average current of 2IOUT flows in the direction of the solid line arrow in FIG. 9, and the capacitor C1 is charged. At the same time, the charge stored in the capacitor C2 is discharged, and the output current IOUT flows.

On the other hand, in the period T2, if the charge / discharge current to the parasitic capacitance is ignored, an average current of 2IOUT flows in the direction of the broken line arrow in FIG. 9, and IOUT flows as an output current. At the same time, the remaining charge discharged from the capacitor C1 is charged into the capacitor C2.
In the period T0, there is no movement of charge between the capacitor C1 and the capacitor C2, the charge stored in the capacitor C2 is discharged, and the output current IOUT flows.

During this entire period, the average current flowing through the MOS transistors SW1 to SW4 for each switch is all IOUT, and the average current of the input current is 2IOUT when the charge / discharge current to the parasitic capacitance is ignored.
Here, the power conversion efficiency η of the DC-DC converter is defined by the following equation (1).
η = (output power / input power) × 100 (1)
If the parasitic resistances and parasitic capacitances of the switching MOS transistors SW1 to SW4 and the like are ignored, input power = 2IOUT × VDD, output power = IOUT × 2VDD, and power conversion efficiency η = 100%.
JP 2002-209375 A

  However, in this conventional DC-DC converter, a voltage drop occurs due to a resistance such as a MOS transistor connecting the output current IOUT and the capacitor, and the power conversion efficiency is lowered. Therefore, the conventional DC-DC converter is configured to reduce the resistance of the switching MOS transistor by increasing the gate-source voltage for turning on the switching MOS transistor, thereby increasing the gate-source voltage. A high voltage MOS transistor with high resistance is used.

Generally, a high breakdown voltage MOS transistor increases the withstand voltage between the terminals, so that the drain and source have a special structure, and the design area is larger than that of the low breakdown voltage MOS transistor. In addition, since the gate insulating film has a thick structure and the minimum gate length becomes long, the resistance value is several times larger than that of the low breakdown voltage MOS transistor at the same transistor size.
For this reason, the conventional DC-DC converter has a demerit that the design area of the high-breakdown-voltage switch MOS transistor is increased and the gate parasitic capacitance is also increased, so that the power conversion efficiency is lowered.
In view of the above, an object of the present invention is to provide a DC-DC converter capable of improving power conversion efficiency and further reducing the design area.

In order to solve the above-described problems and achieve the object of the present invention, each invention described in claims 1 to 4 has the following configuration.
That is, the invention described in claim 1 includes a plurality of switching MOS transistors and a capacitor. The plurality of MOS transistors are turned on and off to charge the capacitor with an input voltage, and the charging voltage is used. A charge pump type DC-DC converter configured to obtain a desired output voltage, comprising a level shift circuit for generating a control signal for controlling on / off of a predetermined MOS transistor among the plurality of MOS transistors, The level shift circuit is driven and controlled by the source voltage of the predetermined MOS transistor that is on / off controlled.

  According to a second aspect of the present invention, in the DC-DC converter according to the first aspect, the level shift circuit converts the level of a predetermined timing signal to a source voltage of the predetermined MOS transistor that is controlled to be turned on / off. And an output control unit that controls the output of the level of the timing signal converted by the level conversion unit in accordance with a bias voltage generated based on the source voltage.

  The invention according to claim 3 is a charge pump type DC-DC converter having a first terminal and a second terminal, and alternately from the first terminal and the second terminal. A capacitor to which an input voltage is supplied, a source connected to the first terminal of the capacitor, an input voltage to the drain, and a first MOS transistor that is turned on in a first period; a second of the capacitor; A second MOS transistor connected between the terminal and ground and turned on in the first period; a drain connected to the second terminal of the capacitor; an input voltage input to the source; and a second period A third MOS transistor that is turned on, a drain connected to the first terminal of the capacitor, a source connected to the output terminal, and a fourth MOS transistor that is turned on in the second period; A first level shift circuit that generates an on / off control signal supplied to the gate of the MOS transistor; and a second level shift circuit that generates an on / off control signal supplied to the gate of the fourth MOS transistor, The first level shift circuit generates the on / off control signal based on the source voltage of the first MOS transistor, and the second level shift circuit generates the above-described signal based on the source voltage of the fourth MOS transistor. An on / off control signal is generated.

  According to a fourth aspect of the present invention, in the DC-DC converter according to the third aspect, the first level shift circuit converts the level of a predetermined timing signal into a source voltage of the first MOS transistor. And an output control unit that controls the output of the level of the timing signal converted by the level conversion unit according to a bias voltage generated based on the source voltage, and the second level shift circuit includes: A level converter that converts a predetermined timing signal into a source voltage of the fourth MOS transistor, and a level of the timing signal converted by the level converter according to a bias voltage generated based on the source voltage And an output control unit that performs output control.

As described above, according to the present invention, in the DC-DC converter that generates a positive and negative high voltage, the on / off control voltage supplied to the gate of the MOS transistor is set to a low withstand voltage in accordance with the varying source potential of the switching MOS transistor. The maximum potential of the MOS transistor is controlled.
Therefore, a low breakdown voltage MOS transistor having a smaller resistance value and a smaller gate parasitic capacitance than the high breakdown voltage MOS transistor can be used as the switching MOS transistor.
As a result, according to the present invention, it is possible to improve the power conversion efficiency and further reduce the design area.

Hereinafter, embodiments of the DC-DC converter of the present invention will be described with reference to FIGS.
FIG. 1 is a circuit diagram showing a configuration of a single-stage charge pump type DC-DC converter according to an embodiment of the present invention.
As shown in FIG. 1, the DC-DC converter according to this embodiment relates to two types of capacitors C1 and C2, switching MOS transistors SW1 to SW4 connecting between them, and ON / OFF control of the MOS transistors SW1 to SW4. A timing signal generation circuit TG1 that generates a timing signal, and level shifters (level shift circuits) LS1 ′ and LS2 ′ that generate signals for controlling on / off of the MOS transistors SW1 and SW2 using the timing signal from the timing signal generation circuit TG1. , An input terminal IN for supplying the input voltage VDD, and an output terminal OUT for taking out the output voltage VOUT.

Here, the capacitor C1 is a charge transfer capacitor, and the capacitor C2 is a smoothing capacitor. The MOS transistors SW1, SW2, and SW3 are P-type MOS transistors, and the MOS transistor SW4 is an N-type MOS transistor.
In this embodiment, when the MOS transistors SW1 to SW4 are controlled to be turned on / off by a signal output from the timing signal generation circuit TG1, the voltage is converted by transferring charges from the capacitor C1 to the capacitor C2, and the input voltage is set to VDD. Ideally, 2VDD is output as the output voltage VOUT.

In this embodiment, as will be described later, the MOS transistors SW3 and SW4 can be controlled by the input voltage VDD, and low-voltage MOS transistors having resistance to the input voltage VDD are used.
Further, in this embodiment, as will be described later, the voltage between the terminals of the MOS transistors SW1 and SW2 is controlled within the tolerance range of the low breakdown voltage MOS transistor. Therefore, even when the maximum output voltage 2VDD is higher than the withstand voltage of the low withstand voltage MOS transistor, the low withstand voltage MOS transistors are used for the MOS transistors SW1 and SW2.

Next, a specific configuration of this embodiment will be described with reference to FIG.
As shown in FIG. 1, a MOS transistor SW1 and a MOS transistor SW2 are connected in series between an input terminal IN and an output terminal OUT. That is, the drain of the MOS transistor SW1 is connected to the input terminal IN, the source of the MOS transistor SW1 is connected to the drain of the MOS transistor SW2, and the source of the MOS transistor SW2 is connected to the output terminal OUT.

  Further, the MOS transistor SW3 and the MOS transistor SW4 are connected in series between the input terminal IN and the ground (ground portion). That is, the source of the MOS transistor SW3 is connected to the input terminal IN, the drain of the MOS transistor SW3 is connected to the drain of the MOS transistor SW4, and the source of the MOS transistor SW4 is grounded.

  One end of the capacitor C1 is connected to a common connection where the source of the MOS transistor SW1 and the drain of the MOS transistor SW2 are connected in common. Further, the other end side of the capacitor C1 is connected to a common connection portion where the drain of the MOS transistor SW3 and the drain of the MOS transistor SW4 are commonly connected. Further, the capacitor C2 has one end connected to the output terminal OUT and the other end connected to the ground.

The timing signal generation circuit TG1 generates timing signals Φ1 and Φ2 that are no overlap clocks and their inverted signals Φ1B and Φ2B in order to prevent reverse current flowing from the capacitor C2 toward the capacitor C1. Yes.
The timing signal Φ1 from the timing signal generation circuit TG1 is supplied to the gate of the MOS transistor SW4, and the MOS transistor SW4 is controlled to be turned on / off. Further, the timing signal Φ2 from the timing signal generation circuit TG1 is supplied to the gate of the MOS transistor SW3, and the MOS transistor SW3 is controlled to be turned on / off.

Note that the levels of the timing signals Φ1 and Φ2 and the inverted signals Φ1B and Φ2B output from the timing signal generation circuit TG1 are the level of the input voltage VDD, that is, the range of 0 [V] to VDD [V].
The level shifter LS1 ′ receives the timing signals Φ1 and Φ1B generated by the timing signal generation circuit TG1 and having the level of the input voltage VDD, converts them into the source voltage Vsource of the MOS transistor SW1, and outputs it as the control signal ΦSW1. It has become. Therefore, the source voltage Vsource of the MOS transistor SW1 is supplied to the level shifter LS1 ′. Then, the control signal ΦSW1 is supplied to the gate of the MOS transistor SW1, so that the MOS transistor SW1 is on / off controlled.

  The level shifter LS2 ′ receives the timing signals Φ2 and Φ2B generated by the timing signal generation circuit TG1 and having the level of the input voltage VDD, converts them into the source voltage Vsource (VOUT) of the MOS transistor SW2, and outputs it as the control signal ΦSW2. It is supposed to be. For this reason, the source voltage Vsource of the MOS transistor SW2 is supplied to the level shifter LS2 '. Then, the control signal ΦSW2 is supplied to the gate of the MOS transistor SW2, whereby the MOS transistor SW2 is controlled to be turned on / off.

Next, a specific configuration of the level shifter LS1′LS2 ′ will be described with reference to FIG.
As described above, the level shifter LS1 ′ and the level shifter LS2 ′ are different from each other in the input signal and the value of the output signal obtained by converting the level of the input signal. However, since the configurations are basically the same, the level shifter LS1 is here. The configuration of 'will be described.
The level shifter LS1 ′ includes a level conversion unit 10 and an output control unit 20, as shown in FIG.
The level conversion unit 10 receives the timing signals Φ1 and Φ1B generated by the timing signal generation circuit TG1 and converts them into the source voltage Vsource of the MOS transistor SW1.

The output unit 20 controls the output of the level of the timing signal converted by the level conversion unit 10 according to a bias voltage Vbias generated by a bias voltage generation circuit 30 described later based on the source voltage Vsource of the MOS transistor SW1. The controlled signal is output from the output terminal 22 as the control signal ΦSW1.
As shown in FIG. 2, the level conversion unit 10 includes MOS transistors L1 to L4. The MOS transistors L1 to L4 are supplied with the source voltage Vsource of the MOS transistor SW2, and operate accordingly.

Here, as the MOS transistors L1 to L4, high voltage MOS transistors having source voltage tolerance are used.
More specifically, the power supply terminal 11 is supplied with the source voltage Vsource of the MOS transistor SW1. A P-type MOS transistor L1 and an N-type MOS transistor L2 are connected in series between the power supply terminal 11 and the ground. A P-type MOS transistor L3 and an N-type MOS transistor L4 are connected in series between the power supply terminal 11 and the ground.

  Further, the timing signal Φ1 from the timing signal generation circuit TG1 is supplied to the gate of the MOS transistor L2, and the timing signal ΦB1 from the timing signal generation circuit TG1 is supplied to the gate of the MOS transistor L4. Yes. In addition, a common connection portion between the MOS transistor L1 and the MOS transistor L2 is connected to the gates of the MOS transistors L3, L5, and L6. Furthermore, the common connection part of the MOS transistor L3 and the MOS transistor L4 is connected to the gate of the MOS transistor L1.

As shown in FIG. 2, the output control unit 20 includes MOS transistors L5 to L8, a bias supply terminal 21 for supplying a bias voltage Vbias generated by the bias voltage generation circuit 30 shown in FIG. 3, and a MOS transistor SW1. And an output terminal 22 for taking out a control signal ΦSW1 to be supplied to the gate.
Here, as the MOS transistors L5 to L8, high breakdown voltage MOS transistors having source voltage tolerance are used.

More specifically, a P-type MOS transistor L5, a P-type MOS transistor L7, and an N-type MOS transistor L6 are connected in series between the power supply terminal 11 and the ground. Further, a P-type MOS transistor L 8 is connected between the bias supply terminal 21 and the output terminal 22.
The gate of the MOS transistor L5 and the gate of the MOS transistor L6 are connected in common, and the output of the level converter 10 is supplied to this common connection. A bias voltage Vbias from the bias generation circuit 30 shown in FIG. 3 is supplied to the gate of the MOS transistor L7. The common connection portion of the MOS transistors L5 and L7, the drain of the MOS transistor L8, and the gate of the MOS transistor L8 are connected to the output terminal 22.

  In the output control unit 20 configured as described above, the bias voltage Vbias generated by the bias voltage generation circuit 30 in accordance with the source voltage of the MOS transistor SW1 is supplied to the gate of the MOS transistor L7. As a result, the current flowing through the MOS transistor L7 is controlled, and the level of the control signal ΦSW1 output from the output terminal 22 varies. That is, the gate voltage of the MOS transistor SW1 can be controlled to the maximum resistance potential of the low breakdown voltage MOS transistor according to the source voltage.

Next, a specific configuration of the bias generation circuit 30 that generates the bias voltage Vbias to be supplied to the level shifters LS1′LS2 ′ will be described with reference to FIG.
As shown in FIG. 3, the bias generation circuit 30 includes a resistor R1, a diode-connected P-type MOS transistor L9, an output terminal 32, and a constant current circuit 33 that generates a constant current. The power supply terminal 31 and the ground are connected in series. Here, as the MOS transistor L9, a high-breakdown-voltage MOS transistor having a source voltage tolerance is used.

More specifically, the source voltage Vsource of the MOS transistor SW1 or the source voltage Vsource (VOUT) of the MOS transistor SW2 is supplied to the power supply terminal 31.
A bias voltage Vbias is taken out from the output terminal 32. That is, when the source voltage Vsource of the MOS transistor SW1 is supplied to the power supply terminal 31, the bias voltage Vbias extracted from the output terminal 32 is supplied to the level shifter LS1 ′. On the other hand, when the source voltage Vsource (VOUT) of the MOS transistor SW2 is supplied to the power supply terminal 31, the bias voltage Vbias extracted from the output terminal 32 is supplied to the level shifter LS2 ′.

  As shown in FIG. 3, the constant current circuit 33 includes a reference voltage generating circuit VR1, an operational amplifier OP1, an N-type MOS transistor L10, and a resistor R2. The operational amplifier OP1 generates an error signal according to the difference between the potential of the common connection between the MOS transistor L10 and the resistor R2 and the reference voltage from the reference voltage generation circuit VR1. The error signal is supplied to the gate of the MOS transistor L10, whereby the current flowing through the MOS transistor L10 is controlled to be constant. That is, a desired constant current can be obtained.

The reference voltage generation circuit VR1 uses a band gap or the like and further generates a desired reference voltage by resistance division.
In the bias generation circuit 30 having such a configuration, a constant current flows through the resistor R1 and the diode-connected MOS transistor L9 by the constant current circuit 33, and a constant voltage drop occurs. For this reason, a constant voltage drop occurs with respect to the source voltage Vsource of the MOS transistor SW1 or SW2 supplied to the power supply terminal 31, and a desired bias voltage Vbias is obtained.

FIG. 4 shows the relationship between the source voltage Vsource and the bias voltage Vbias, and the relational expression will be described below.
Here, the threshold voltage of the MOS transistor L7 shown in FIG. 2 is Vthp, and its gate voltage is Vgate. When the maximum withstand voltage Vmax of the MOS transistors SW1 and SW2 is assumed, the following equations (2) and (3) are obtained.
Vgate = Vbias + Vthp (2)
Vmax = Vsource−Vthp (3)
The following equation (4) is obtained from the equations (2) and (3).
Vbias = Vsource−Vthp−Vmax (4)

When the embodiment having such a configuration is operated at an operating frequency of 1000 [kHz] and the output current IOUT is set to 5 [mA], the MOS transistors SW1 and SW2 have the same size as that of the conventional high voltage MOS transistor. In the case of the conventional circuit configuration, the channel width W and the channel length L are about W = 20000 [μm] and L = 2.5 [μm].
On the other hand, in the case of the circuit configuration using the low breakdown voltage MOS transistors for the MOS transistors SW1 and SW2 as in this embodiment, W = 5000 [μm] and L = 0.7 [μm], Compared with the case of using a high voltage MOS transistor, the transistor size is ¼ or less.

Next, an example of the operation of the embodiment having such a configuration will be described with reference to FIGS.
The timing signal generation circuit TG1 shown in FIG. 1 generates timing signals Φ1 and Φ2 and their inverted signals Φ1B and Φ2B as shown in (G) and (F) of FIG. The timing signal Φ1 is supplied to the gate of the MOS transistor SW4, and the MOS transistor SW4 is controlled to be turned on / off. The timing signal Φ2 is supplied to the gate of the MOS transistor SW3, and the MOS transistor SW3 is controlled to be turned on / off.

  The level shifter LS1 'receives the timing signals Φ1 and Φ1B generated by the timing signal generation circuit TG1 and having the level of the input voltage VDD, converts them into the source voltage Vsource of the MOS transistor SW1, and outputs it as the control signal ΦSW1. The control signal ΦSW1 is supplied to the gate of the MOS transistor SW1, whereby the MOS transistor SW1 is on / off controlled.

  On the other hand, the level shifter LS2 ′ receives the timing signals Φ2 and Φ2B generated by the timing signal generation circuit TG1 and having the level of the input voltage VDD, converts this into the source voltage Vsource (VOUT) of the MOS transistor SW2, and the control signal ΦSW2 Output as. The control signal ΦSW2 is supplied to the gate of the MOS transistor SW2, whereby the MOS transistor SW2 is on / off controlled.

  By such control, in the period T1 'shown in FIG. 5, the MOS transistors SW1 and SW4 are turned on and the MOS transistors SW2 and SW3 are turned off. At this time, the capacitor C1 is charged by the input voltage VDD, the potential VC1 + on one end side of the capacitor C1 becomes VDD as shown in FIG. 5B, and the potential VC1- on the other end side of the capacitor C1 is shown in FIG. As shown in FIG.

  In the initial state until the output voltage VOUT is boosted to the potential VC1 on one end side of the capacitor C1, the MOS transistor SW2 is a P-type MOS transistor, so that the PN junction between its drain and well becomes a forward bias. Become. For this reason, the output voltage VOUT is a potential that is lowered from the potential VC1 + on one end side of the capacitor C1 by the forward voltage of the diode of the PN junction. After the output voltage VOUT is boosted to the potential VC1 + on one end side of the capacitor C1, there is no charge movement between the capacitor C1 and the capacitor C2, and the voltage does not change.

At this time, the level shifter LS1 ′ uses the source voltage (VC1 +) of the MOS transistor SW1 and the bias voltage Vbias1 generated by the bias voltage generation circuit 30 of FIG. 3 according to the source voltage, to gate the MOS transistor SW1. A control signal ΦSW1 to be supplied to is generated (see FIG. 5E).
That is, the level shifter LS1 ′ controls the gate voltage of the MOS transistor SW1 to [(VC1 +) − (maximum tolerance potential difference of the low breakdown voltage MOS transistor)] to turn on the MOS transistor SW1. As a result, the voltage between the terminals of the MOS transistor SW1 is controlled to the maximum withstand voltage of the low breakdown voltage MOS transistor.

Further, the level shifter LS2 ′ supplies the gate of the MOS transistor SW2 using the source voltage (VOUT) of the MOS transistor SW2 and the bias voltage generated by the bias voltage generation circuit 30 of FIG. 3 according to the source voltage. The control signal ΦSW2 to be generated is generated (see FIG. 5D).
That is, the level shifter LS2 ′ outputs the source voltage (VOUT) as the gate voltage of the MOS transistor SW2, and turns off the MOS transistor SW2. As a result, the voltage between the drain and source of the MOS transistor SW2 becomes VDD, so that the potential difference between the terminals of the MOS transistor SW2 is controlled within the tolerance range of the low breakdown voltage MOS transistor.

  On the other hand, in the period T2 'shown in FIG. 5, the MOS transistors SW2 and SW3 are turned on and the MOS transistors SW1 and SW4 are turned off. At this time, the potential VC1- on the other end side of the capacitor C1 becomes the input voltage VDD. On the other hand, the potential VC1 + on the one end side of the capacitor C1 is a voltage 2VDD which is the sum of the charging voltage VDD of the capacitor C1 and the potential VC1- (VDD). At the same time, the electric charge of the capacitor C1 moves to the capacitor C2, and the output voltage VOUOT becomes 2VDD.

At this time, the level shifter LS1 ′ uses the source voltage (VC1 +) of the MOS transistor SW1 and the bias voltage generated by the bias voltage generation circuit 30 of FIG. 3 according to the source voltage to the gate of the MOS transistor SW1. A control signal ΦSW1 to be supplied is generated (see FIG. 5E).
That is, the level shifter LS1 ′ outputs the source voltage (VC1 +) as the gate voltage of the MOS transistor SW1, and turns off the MOS transistor SW1. As a result, since the voltage between the drain and source of the MOS transistor SW1 becomes VDD, the potential difference between the terminals of the MOS transistor SW1 is controlled within the tolerance range of the low breakdown voltage MOS transistor.

Further, the level shifter LS2 ′ uses the source voltage (VOUT) of the MOS transistor SW2 and the bias voltage Vbias2 generated by the bias voltage generation circuit 30 of FIG. 3 according to the source voltage, to the gate of the MOS transistor SW2. A control signal ΦSW2 to be supplied is generated (see FIG. 5D).
That is, the level shifter LS2 ′ controls the gate voltage of the MOS transistor SW2 to [(VOUT) − (maximum tolerance potential difference of the low breakdown voltage MOS transistor)] to turn on the MOS transistor SW2. As a result, the voltage between the terminals of the MOS transistor SW2 is controlled to the maximum withstand voltage of the low breakdown voltage MOS transistor.

  In this manner, by repeating the operations in the period T1 'and the period T2', the output voltage VOUT is boosted to a voltage (2VDD) that is twice the input voltage VDD when the resistance of the MOS transistor or the like is ignored. Further, in the period T0 'shown in FIG. 5, the MOS transistors SW1 to SW4 are turned off, and charge transfer between the capacitors C1 and C2 is eliminated. Therefore, when the period T1 'and the period T2' are switched, no reverse current flows from the capacitor C2 toward the capacitor C1, and the power conversion efficiency does not decrease.

Next, the case where the constant current IOUT flows to the output after the output voltage has been boosted to 2VDD will be described.
In the period T1 shown in FIG. 5, since the control state is the same as that in the period T1 ′, the voltage between the terminals of the MOS transistor SW1 is controlled to the maximum withstand voltage of the low breakdown voltage MOS transistor, and the voltage between the terminals of the MOS transistor SW2. Is controlled within the tolerance range of the low breakdown voltage MOS transistor. In addition, since the output voltage VOUT is higher than the potential of VC1 +, there is no movement of charge between the capacitor C1 and the capacitor C2, and the output voltage VOUT is equivalent to the reduction of the charge stored in the capacitor C2 as the output current. Decreases from 2VDD.

  Further, since the period T2 shown in FIG. 5 is in the same control state as the period T2 ′, the voltage between the terminals of the MOS transistor SW1 is controlled within the tolerance range of the low breakdown voltage MOS transistor, and each terminal of the MOS transistor SW2 is controlled. The inter-voltage is controlled to the maximum withstand voltage of the low breakdown voltage MOS transistor. Further, the output voltage VOUT is boosted to 2VDD as the charge moves from the capacitor C1 to the capacitor C2. At the same time, the electric charge flowing out as the output current also moves from the capacitor C1.

  Such operations in the period T1 and the period T2 are repeated, and the output voltage is stabilized with a constant voltage drop from 2VDD. Further, in the period T0 shown in FIG. 5, the MOS transistors SW1 to SW4 are turned off, and charge transfer between the capacitors C1 and C2 is eliminated. For this reason, when the period T1 and the period T2 are switched, the reverse current does not flow from the capacitor C2 toward the capacitor C1, and the power conversion efficiency does not decrease.

As described above, the voltage between the terminals of the MOS transistors SW1 and SW2 is controlled within the tolerance range of the low breakdown voltage MOS transistor in the boosting period until the voltage is stabilized and in the period after the stabilization. .
As a result, the MOS transistors SW1 and SW2 can use low withstand voltage MOS transistors having lower resistance than the high withstand voltage MOS transistors. Further, the MOS transistors SW1 and SW2 can always reduce the resistance of the MOS transistor in the boosting period and the stable period by controlling the fluctuation of the gate voltage according to the source voltage.

As described above, in this embodiment, the resistance of the switching MOS transistor is reduced, and the power conversion efficiency is improved.
Further, in this embodiment, when the gate parasitic capacitance of the switching MOS transistor is reduced, if the gate parasitic capacitance is Cgate, the gate voltage is Vgate, and the operating frequency is f, the wasteful current Igate = Cgate × Vgate × f decreases. As a result, it is possible to suppress a decrease in power conversion efficiency η represented by the following equation (5).
η = (2VDD × IOUT) / (VDD × (2IOUT + Igate)) × 100 (5)
Further, in this embodiment, by using a low-breakdown-voltage MOS transistor having a small resistance value with the same transistor size, the design area can be reduced to about ½ without reducing the power conversion efficiency.

In the above embodiment, the single-stage charge pump type DC-DC converter has been described. However, the number of stages is not limited to one. That is, the present invention can be applied to not only generating an output voltage twice as large as the input voltage VDD but also generating an output voltage such as three times, four times,.
In the above embodiment, the case where a positive voltage is generated has been described. However, a circuit that generates a negative voltage may be used. Furthermore, not only in the charge pump type DC-DC converter, in the positive and negative high voltage generation circuit used in the DC-DC converter, the maximum voltage of the drain-source voltage is within the tolerance range of the low breakdown voltage MOS transistor, The present invention is applicable to all circuits using high voltage MOS transistors.

It is a circuit diagram which shows the structure of embodiment of this invention. FIG. 2 is a circuit diagram showing a specific configuration of the level shifter shown in FIG. 1. It is a circuit diagram which shows the specific structure of a bias voltage generation circuit. It is a figure which shows the relationship between the supply voltage of a bias voltage generation circuit, and the bias voltage produced | generated. It is a wave form diagram which shows the example of a waveform of each part at the time of operation | movement of this embodiment. It is a circuit diagram of a conventional charge pump type DC-DC converter. It is a circuit diagram of a conventional level shifter. It is a wave form diagram which shows the example of a waveform of each part at the time of operation | movement of the conventional charge pump type DC-DC converter. In a conventional circuit, it is explanatory drawing of the current in a circuit at the time of output current.

Explanation of symbols

SW1-SW4 MOS transistors for switching C1, C2 capacitor TG1 Timing signal generation circuit LS1 ′, LS2 ′ level shifter (level shift circuit)
IN input terminal OUT output terminal 10 level conversion unit 20 output control unit 30 bias voltage generation circuit

Claims (4)

A charge comprising a plurality of switching MOS transistors and a capacitor, wherein the plurality of MOS transistors are turned on / off to charge the capacitor with an input voltage, and a desired output voltage is obtained using the charged voltage. A pump type DC-DC converter,
A level shift circuit for generating a control signal for controlling on / off of a predetermined MOS transistor among the plurality of MOS transistors;
The level shift circuit is driven and controlled by a source voltage of the predetermined MOS transistor that is on / off controlled. The level shift circuit includes:
A level converter that converts a level of a predetermined timing signal into a source voltage of a predetermined MOS transistor that is controlled to be turned on and off;
An output control unit for controlling output of the level of the timing signal converted by the level conversion unit according to a bias voltage generated based on the source voltage;
The DC-DC converter according to claim 1, further comprising: A charge pump type DC-DC converter,
A capacitor having a first terminal and a second terminal, to which an input voltage is alternately supplied from the first terminal and the second terminal;
A first MOS transistor having a source connected to the first terminal of the capacitor, an input voltage input to the drain, and being turned on in a first period;
A second MOS transistor connected between the second terminal of the capacitor and the ground and turned on during the first period;
A third MOS transistor having a drain connected to the second terminal of the capacitor, an input voltage input to the source, and being turned on in the second period;
A fourth MOS transistor having a drain connected to the first terminal of the capacitor, a source connected to the output terminal, and being turned on in the second period;
A first level shift circuit for generating an on / off control signal to be supplied to the gate of the first MOS transistor;
A second level shift circuit for generating an on / off control signal to be supplied to the gate of the fourth MOS transistor,
The first level shift circuit generates the on / off control signal based on the source voltage of the first MOS transistor, and the second level shift circuit is based on the source voltage of the fourth MOS transistor. A DC-DC converter that generates the on / off control signal. The first level shift circuit includes:
A level converter that converts a predetermined timing signal into a source voltage of the first MOS transistor, and a level of the timing signal converted by the level converter according to a bias voltage generated based on the source voltage And an output control unit for controlling output,
The second level shift circuit includes:
A level converter that converts a predetermined timing signal into a source voltage of the fourth MOS transistor, and a level of the timing signal converted by the level converter according to a bias voltage generated based on the source voltage The DC-DC converter according to claim 3, further comprising an output control unit that performs output control.

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