JP3475178B2 - Charge pump circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit used in a power supply circuit or the like, and more particularly to a charge pump circuit capable of high efficiency and large current output.

[0002]

2. Description of the Related Art In recent years, video equipment such as video cameras, digital still cameras (DSC), and DSC phones use CCDs (Charge Coupled Devices) to capture the video. The CCD drive circuit for driving the CCD has a positive and negative high voltage (tens of volts) and a large current (several mA).
Need a power circuit. Currently, this high voltage is generated using a switching regulator.

A switching regulator can generate a high voltage with high performance, that is, high power efficiency (output power / input power). However, this circuit has a drawback of generating harmonic noise at the time of switching current, and therefore the power supply circuit must be shielded for use. Furthermore, a coil is required as an external component.

On the other hand, the charge pump circuit can generate a high voltage with a small noise, but has a drawback that the power efficiency is lower than the conventional one. Therefore, the charge pump circuit is used as a power supply circuit of a portable device having power efficiency as a priority specification. It is not possible. Therefore, if a high-performance charge pump circuit can be realized, it can contribute to downsizing of portable devices.

A Dickson charge pump circuit is known as the most basic conventional charge pump circuit. This circuit is described, for example, in the technical document "John F. Dickson.
“On-chip High-Voltage Generation in MNOS Integra
ted Circuits Using an Improved Voltage Multiplier
Technique ”IEEE JOURNAL OF SOLID-STATE CIRCUITS, V
OL.SC-11, NO.3 pp.374-378 JUNE 1976. ”.

FIG. 11 is a schematic circuit diagram showing a four-stage Dickson charge pump circuit. In FIG. 11, five diodes are connected in series. C is the coupling capacity, CL
Is the output capacitance, and CLK and CLKB are the input clock pulses having opposite phases. Further, 51 is a clock driver, and 52 is a current load.

When the constant current Iout flows in the output in the stable state, the input current to the charge pump circuit is the current from the input voltage Vin and the current supplied from the clock driver. These currents are as follows, ignoring the charging / discharging current to the parasitic capacitance. Φ1 = High,
2Io in the direction of the solid line arrow in the figure during the period of Φ2 = Low
The average current of ut flows. Also, Φ1 = Low, Φ2 =
During the period of High (High), the average current of 2Iout flows in the direction of the broken line arrow in the figure. All these average currents in a clock cycle will be Iout. The boosted voltage Vout of the charge pump circuit in the stable state is expressed as follows.

[0008]

[Equation 1]

Here, V _φ 'is at each connection node,
It is the voltage amplitude caused by the coupling capacitance as the clock pulse changes. V _l is a voltage drop caused by the output current Iout, and Vin is an input voltage, which is normally set to the power supply voltage Vdd for positive boosting and 0 V for negative boosting. Vd is the forward bias diode voltage
tage) n is the number of pumping stages. Further, V _l and V _φ 'are expressed by the following equations.

[0010]

[Equation 2]

[0011]

[Equation 3]

Here, C is a clock coupling capacity (clock cou
pling capacitance), C _S is the stray capacitance at each node, V _φ is the clock pulse amplitude, f is the frequency of the clock pulse, and T is the clock period.
Is. For the power efficiency of the charge pump circuit, the charge / discharge current flowing from the clock driver to the parasitic capacitance is ignored, and V
When in = Vdd, it is represented by the following formula.

[0013]

[Equation 4]

As described above, in the charge pump circuit, the diode is used as a charge transfer device (charge transfer device).
It is used as e) to boost the voltage by successively transferring the charges to the next stage. However, considering mounting on a MOS integrated circuit, it is easier to use a MOS transistor rather than a pn junction diode because of compatibility with the process. Therefore, it has been proposed to use a MOS transistor instead of a diode as a charge transfer element. In this case, in the equation (1), Vd is the threshold voltage Vt of the MOS transistor.

The voltage loss (voltage loss) corresponding to the threshold voltage Vt
In order to eliminate the loss) and realize a high-performance charge pump circuit, the impedance of the charge transfer MOS transistor must be lowered according to the value of Iout. For that purpose, it is effective to optimize the channel width of the charge transfer MOS transistor and at the same time raise the gate-source voltage Vgs thereof to the power supply voltage Vdd or higher. A charge pump circuit that realizes this is described in, for example, the technical document “Jieh
-Tsorng Wu “MOS Charge Pumps for Low-Voltage Oper
ation ”IEEE JOURNAL OF SOLID-STATE CIRCUITS.VOL.3
3, NO.4 APRIL 1998 ”.

[0016]

The present inventor has studied the charge pump circuit of the above-mentioned technical documents and found the following problems. FIG. 12 shows a circuit diagram of one charge pump circuit published in the document. In the figure, MD1 to MD4
Is a diode for initial setting of each pump node and does not contribute to pumping operation. The characteristic of this circuit is that the voltage of the pumping node at the subsequent stage, which is boosted as the gate-source voltage Vgs of the charge transfer MOS transistors MS1 to MS3, is returned to give 2Vdd. However, it is difficult to give 2Vdd as Vgs to the charge transfer MOS transistor MS4 at the final stage.
It is inevitable that voltage loss will occur.

Another charge pump circuit described in the above document is a dynamic type charge pump circuit shown in FIG. This circuit uses a bootstrap high voltage clock in order to prevent Vgs of the MOS transistor MD4 from dropping to Vdd + (Vdd-Vth) and Vgs of the MOS transistor MD0 to (Vdd-Vth). Generator (High-voltage clock generat
or) is used. Further, all the charge transfer MOS transistors MS1 to MS4 are of N-channel type.

This method is effective when the current load is small because the size of the charge transfer MOS transistor is small, that is, the gate parasitic capacitance is small. However, in order to realize a charge pump circuit with a large current output, the channel width of the charge transfer MOS transistor must be set to several millimeters, which results in a large gate parasitic capacitance of the MOS transistor (several pF), resulting in bootstrap. It becomes very difficult to generate a 2Vdd clock depending on the method. In addition, there is a drawback that a method of applying a voltage equal to or higher than the power supply voltage Vdd as the gate-source voltage Vgs of the charge transfer MOS transistor in the subsequent stage must be devised separately.

The present invention has been made in view of the problem to solve the above-mentioned problems of the prior art, and eliminates the voltage loss due to the threshold voltage Vt of the charge transfer MOS transistor, resulting in high efficiency and large output current. It is an object to provide a charge pump circuit. Another object of the present invention is to secure the gate oxide film breakdown voltage and to enable the optimum design of the charge transfer MOS transistors by setting the absolute value of the gate-source voltage Vgs of all the charge transfer MOS transistors to 2Vdd. And

[0020]

The typical ones of the inventions of the present application will be outlined below.

In the first charge pump circuit, a predetermined input voltage is applied to the charge transfer MOS transistor at the first stage and (n + 2) charge transfer MOS transistors are connected in series.
A MOS transistor for charge transfer at a subsequent stage, which includes a transistor, a coupling capacitor whose one end is connected to each connection point of the charge transfer MOS transistor, and a clock driver which alternately supplies a clock pulse of an opposite phase to the other end of the coupling capacitor. In a charge pump circuit that outputs a positive boosted voltage from a transistor, two charge transfer MOS transistors in the latter stage are configured by P channels and the remaining n charge transfer MOS transistors are formed.
The transistor is of N-channel type, and circuit means is provided for applying a gate voltage such that the gate-source voltage becomes a constant value when the charge transfer MOS transistor is turned on.

According to such means, it is possible to provide a charge pump circuit with high efficiency and large output current by eliminating the voltage loss due to the threshold voltage Vt of the charge transfer MOS transistor. Moreover, by setting the absolute value of the gate-source voltage Vgs of all the charge transfer MOS transistors to a constant value (for example, 2 Vdd), the gate oxide film breakdown voltage can be stably ensured and the charge transfer M
Optimal design of OS transistors is possible.

The second charge pump circuit is the same as the first charge pump circuit, except that the circuit means controls the on / off of the N-channel type charge transfer MOS transistor in response to the clock pulse, and the clock pulse. And a non-inverting level shift circuit for controlling ON / OFF of a P-channel type charge transfer MOS transistor according to the above, and using a boosted voltage at a connection point at a subsequent stage as a power source on the high potential side of the inverting level shift circuit. The voltage at the connection point of the preceding stage is used as the low-potential-side power source of the non-inverting level shift circuit.

According to such means, the charge transfer MO is constituted by the inverting level shift circuit and the non-inverting level shift circuit.
It is possible to control ON / OFF of the S transistors to enable boosting, and to make the gate-source voltage Vgs of all the charge transfer MOS transistors constant.

The third charge pump circuit uses, in the second charge pump circuit, the voltage at the connection point after one stage as the power source on the high potential side of the inverting level shift circuit and the low potential of the non-inverting level shift circuit. 1 as the power source on the side
The voltage at the connection point before the stage is used.

According to such means, all charge transfer M
Set the gate-source voltage Vgs of the OS transistor to 2Vd
It can be d.

The fourth charge pump circuit outputs the boosted voltage of the charge transfer MOS transistor at the intermediate stage in the third charge pump circuit and uses it as a power source for other circuits.

According to such means, it is possible to omit the power supply circuit for other circuits which require high voltage, and to improve the efficiency in designing the integrated circuit.

The fifth charge pump circuit differs from the third charge pump circuit in that the duty of the clock pulse supplied to the coupling capacitor and the duty of the clock pulse supplied to the inverting level shift circuit and the non-inverting level shift circuit are made different. The reverse current of the charge transfer MOS transistor is prevented.

According to such means, it is possible to prevent the loss of power consumption.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a schematic circuit diagram showing a three-stage charge pump circuit according to the first embodiment of the present invention.

In FIG. 1, four charge transfer MOS transistors M1 to M4 are connected in series. M in the previous stage
One of the features is that 1 and M2 are N-channel type, and M3 and M4 in the latter stage are P-channel type. The gate and the substrate voltage Vgb of M1 to M4 are connected to have the same potential as the gate and source voltage Vgs, and the source and the substrate have the same potential. The input voltage V is applied to the source of M1.
The power supply voltage Vdd is supplied as in. Also, M
The boosted voltage Vout is output from the drain of the No. 4 and is supplied to the current load L.

C1, C2 and C3 are coupling capacitors whose one ends are connected to connection points (pumping nodes) of the charge transfer MOS transistors M1 to M4. A clock pulse CLK and a clock pulse CLKB having an opposite phase to the clock pulse CLK are alternately applied to the other ends of the coupling capacitors C1 to C3. The clock pulses CLK and CLKB are output from a clock driver (not shown). It is assumed that the clock driver is supplied with the power supply voltage Vdd.

Charge transfer MOS transistors M1 and M2
The outputs of the inversion level shift circuits S1 and S2 are supplied to the respective gates. Further, the non-inverting level shift circuit S is provided at each gate of the charge transfer MOS transistors M3 and M4.
The outputs of 3 and S4 are supplied.

FIG. 2 shows the circuit configuration and operation waveform diagram of the inversion level shift circuits S1 and S2. As shown in FIG. 2A, this inverting level shift circuit has an input inverter IN.
V, differential input MOS transistors M11 and M12, and cross-connected MOS transistors M13 and M14. The configuration up to this point is similar to that of the conventional level shift circuit.

In addition to these, the inverting level shift circuit includes a pull-up connected MOS transistor M15,
Equipped with M16. Then, the MOS transistor M1
The voltage V12 is applied to the gate of No. 5 and the potential A is applied to the source.

Further, the voltage V11 having a phase opposite to V12 is applied to the gate of the MOS transistor M16, and the potential B is applied to the source thereof. Here, potential A> potential B. M11 and M12 are N-channel type, M13 to M
16 is a P-channel type.

Further, as shown in FIG. 2B, in the level shift circuit having the above structure, the MOS transistor M
You may change so that 15 and M16 may become an inverter structure.

The operation waveforms of the inverting level shift circuit having the above-mentioned configuration are shown in FIG. The conventional level shift circuit outputs a high voltage and 0V, whereas the level shift circuit alternately outputs the potential A and the intermediate potential B (A>B> 0V). By using this circuit, the absolute value of the gate-drain voltage of the charge transfer MOS transistors M1 and M2 can be made uniform to a constant voltage (2Vdd), as described later.

Next, the non-inverting level shift circuits S3 and S4
FIG. 3 shows a circuit configuration and an operation waveform diagram of the above. The difference from the inverting level shift circuits S1 and S2 is that the voltage V11 is applied to the gate of the MOS transistor M15 pulled up to the potential A.
Is applied and the voltage V12 is applied to the gate of the MOS transistor M16 pulled up to the potential B (FIG. 3A). As shown in FIG. 3B, the MOS transistors M15 and M16 may have an inverter configuration.

As shown in the operation waveform diagram of FIG. 3C, the non-inverted level shift circuits S3 and S4 perform a non-inverted level shift operation with respect to the input voltage IN. By using this level shift circuit, the absolute value of the gate-drain voltage of the charge transfer MOS transistors M3 and M4 can be made uniform to a constant voltage (2Vdd), as described later.

The connection relationship between the inverting level shift circuits S1 and S2, the non-inverting level shift circuits S3 and S4, and the charge pump circuit is as follows. Inversion level shift circuit S
The clock pulse CLK 'is input to 1 and the clock pulse CLKB' is input to the inversion level shift circuit S2. The clock pulses CLK 'and CLKB' are created from the clock pulses CLK and CLKB, respectively, but charge transfer MOS
The low period is short in order to prevent the current from flowing back to the transistors M1 to M4. That is, after the charge transfer MOS transistors M1 to M4 are completely turned off, the boosting of each pumping node is performed by the change of the clock pulses CLK and CLKB. The phase relationship of the clock pulses is shown in FIG.

Further, as shown in FIG. 1, the boosted voltage V2 of the pumping node after one stage is fed back and used as the power supply (potential A) on the high potential side of the inverting level shift circuit S1. . Similarly, the boosted voltage V3 of the pumping node after one stage is fed back and used as the power source (potential A) on the high potential side of the inverting level shift circuit S2. Further, as the power source (potential B) on the low potential side of the inversion level shift circuits S1 and S2, the voltages Vdd and V1 of the respective stages are applied, respectively.

On the other hand, as the power source (potential B) on the low potential side of the non-inverting level shift circuit S3, the voltage V1 of the pumping node of the preceding stage is used, and similarly, the power source on the low potential side of the non-inverting level shift circuit S4. As the power supply (potential B), the voltage V2 of the pumping node one stage before is used. Further, as the power source (potential A) on the high potential side of the inversion level shift circuits S1 and S2, the voltages V3 and Vout of the respective stages are applied, respectively.

The features of the charge pump circuit according to the present embodiment described above are summarized as follows. First, the two charge transfer MOS transistors M1 and M2 in the preceding stage are N
This is that it is a channel type, and the two subsequent charge transfer MOS transistors M3 and M4 are P channel type. Secondly, the inverting level shift circuits S1 and S2 and the non-inverting level shift circuit S3 capable of outputting the intermediate potential.
And S4 are provided.

With these configurations, the gate-source voltage Vgs of the charge transfer transistors M1 to M4 (when the transistors are in the ON state) is guided to 2Vdd as follows. First, the following equation holds. Vgs (M1) = V2 (High) -Vdd Vgs (M2) = V3 (High) -V1 (High) Vgs (M3) = V1 (Low) -V3 (Low) Vgs (M4) = V2 (Low) -Vout Next, the following relationship is further established from the boosting operation of the charge pump in the steady state. V1 (High) = 2Vdd, V1 (Low) = Vdd V2 (High) = 3Vdd, V2 (Low) = 2Vdd V3 (High) = 4Vdd, V3 (Low) = 3Vdd, Vou
t = 4Vdd From these relational expressions, it is derived that the absolute value of Vgs when all the charge transfer MOS transistors are on is the same value 2Vdd as shown in Table 1. Therefore, high V
The on resistance of the charge transfer MOS transistors M1 to M4 is reduced by gs, and a charge pump circuit with high efficiency and large output current can be realized. Further, the gate oxide film thickness (thickness of gate of each of the charge transfer MOS transistors M1 to M4) is
xide) can be uniformly designed to have a thickness that can withstand 2 Vdd, so that compared with the case where Vgs of the charge transfer MOS transistor is non-uniform, the on-state resistance (ON-state resistanc
e) can be designed low and efficiency is good.

[0047]

[Table 1]

FIG. 4 is a timing chart for explaining the operation of the charge pump circuit. The charge transfer MOS transistors M1 to M4 are alternately turned on / off in response to a clock pulse. Here, the inversion level shift circuit S1
And S2 and the clock pulses CLK 'and CLKB' applied to the non-inverting level shift circuits S3 and S4 have different duties. That is, as shown in the figure, the low period is set to be short. Therefore, the ON period of the charge transfer MOS transistors M1 to M4 is shortened. The reason for this is as follows.

Charge transfer MOS transistors M1 to M4
Since is not diode-connected, there is a risk of reverse current flow, which reduces power efficiency. Therefore, in order to prevent this reverse current, the ON period of the charge transfer MOS transistors M1 to M4 is shortened, and during the OFF period,
Pumping is performed by changing the clock pulses CLK and CLKB applied to the coupling capacitors C1 to C3.

FIG. 5 is a diagram showing voltage waveforms V1, V2 and V3 at each pumping node. In the figure, V _Φ is the amplitude of the clock pulses CLK ′ and CLKB ′, and ΔVds is M.
It is the voltage between the source and drain of the OS transistor.

In FIG. 1, the charge transfer M in the second stage
An output circuit for extracting 2Vdd from the OS transistor M2 is provided. This circuit is an inversion level shift circuit S
It is composed of a MOS transistor Mm controlled by 2 and a capacitor Cm. According to this circuit, 2V
Since a stable DC voltage of dd can be obtained, it is suitable as a power source for other circuits, for example, a clock driver.

Although the three-stage charge pump circuit according to the embodiment of the present invention has been described above, the number of stages is not limited to three. That is, a charge pump circuit having an arbitrary number of stages can be realized by configuring the latter two stages as P-channel type and the remaining preceding stages as N-channel type as the charge transfer MOS transistors.

Although it has been shown that the absolute value of Vgs of the charge transfer MOS transistor can be made equal to 2Vdd in the above-described three-stage charge pump circuit, the Vgs of the charge transfer MOS transistor in the multi-stage charge pump circuit has been shown. It is also possible to set the absolute value to 3 Vdd or more.

For that purpose, the inversion level shift circuit S
The voltage of the connection node in the subsequent stage may be used as the power supply on the high potential side of S1 and S2, and the voltage of the connection node in the subsequent stage may be used as the power supply on the high potential side of the non-inverting level shift circuits S3 and S4. However, the gate oxide breakdown voltage (breakdown v
The absolute value of 2Vdd is most suitable in consideration of the gate of gate oxide).

Next, a charge pump circuit according to the second embodiment of the present invention will be described. Although the charge pump circuit described above performs positive boosting, FIG. 6 is a schematic circuit diagram showing a two-stage charge pump circuit that performs negative boosting (boosting below 0 V). This two-stage charge pump circuit
It outputs a boosted voltage of −2 Vdd, and for example −
It is suitable for boosting up to 6.5V.

In FIG. 6, the clock pulse CLK ',
The combination of CLKB 'and the level shift circuit is changed. That is, the charge transfer MOS transistor M
1 ', M2', M3 'are connected in series, and coupling capacitors C1', C2 'are connected to the connection node. M
Reference numeral 1'denotes a P-channel type, and a ground potential (0V) is applied to the source. M2 'and M3' are N-channel type.

The output of the inverting level shift circuit S1 'is applied to the gate of M1', and the outputs of the non-inverting level shift circuits S2 'and S3' are applied to the gates of M2 'and M3'. Then, the minus boosted voltage −Vout is output from the drain of the charge transfer MOS transistor M3 ′ and is supplied to the current load L.

Here, the charge transfer MOS transistor M
2'gate-source voltage Vgs (when ON) is 2Vd
In order to set d, the power source on the high potential side of the non-inverting level shift circuit S2 ′ is set to Vdd. As a result, the absolute value of the gate-source voltage Vgs (when on) of all the charge transfer MOS transistors M1 ′, M2 ′, M3 ′ is 2Vdd.
Can be

In FIG. 6, the charge transfer M in the second stage
An output circuit for extracting -Vdd from the OS transistor M2 'is provided. This circuit is a MOS transistor Mm 'controlled by a non-inverting level shift circuit S2'.
And a capacitor Cm '. According to this circuit, a stable DC voltage of -Vdd can be obtained, so that it can be used for other circuits.

FIG. 7 is a timing chart for explaining the operation of the charge pump circuit having the above structure. Charge transfer M
By the voltages Vgs (M1) to Vgs (M3) applied to the gates of the OS transistors M1 ′, M2 ′, M3 ′,
M1 ', M2' and M3 'are alternately turned on and off repeatedly.
Here, the clock pulses CLK 'and CLKB' prevent the current from flowing backward by shortening the low period. The voltage waveforms V1 and V2 of each pumping node are shown in FIG.

Next, a charge pump circuit according to the third embodiment of the present invention will be described. Figure 9 shows negative boost 3
It is a schematic circuit diagram which shows a stage charge pump circuit. The configuration of this circuit is basically the polarity of the components of the charge pump circuit shown in FIG. 1 reversed. That is,
Charge transfer MOS transistors M1 ′, M of the two previous stages
2'is a P-channel type, and the latter two stages of charge transfer MOS transistors M3 'and M4' are N-channel types.

As the power source (potential B) on the low potential side of the inverting level shift circuit S1 ', the boosted voltage V2' of the pumping node one stage after is used. Similarly, the low-potential-side power supply (potential B) of the inverting level shift circuit S2 'returns the boosted voltage V3' of the pumping node one stage later and uses it. Further, as the power supply (potential A) on the high potential side of the inversion level shift circuits S1 ′ and S2 ′, the voltages Vss and V1 ′ of each stage are applied, respectively.

On the other hand, as the power supply (potential A) on the high potential side of the non-inverting level shift circuit S3 ', the voltage V1' of the pumping node one stage before is used, and similarly, the high potential of the non-inverting level shift circuit S4 'is used. As the power supply (potential A) on the potential side,
The voltage V2 ′ of the pumping node one stage before is used. Further, as the power source (potential B) on the low potential side of the inversion level shift circuits S3 ′ and S4 ′, the voltage of each stage is V
3'and -Vout are applied respectively.

The inversion level shift circuits S1 'and S
The configuration of 2'is the same as that shown in FIG. 2, and the configuration of the non-inverting level shift circuits S3 'and S4' is the same as that shown in FIG. Further, the operation of this charge pump circuit can be understood in the same manner as the operation of the positive boosting charge pump circuit described above, and therefore detailed description thereof is omitted.

According to the above configuration, all charge transfer M
The absolute value of Vgs of the OS transistors M1 ′ to M4 ′ is the same value 2Vdd. Therefore, the ON resistance of the MOS transistors M1 'to M4' for charge transfer is lowered due to the high Vgs, and it is possible to realize a charge pump circuit of high efficiency and a negative boost of a large output current. Further, the gate oxide film thickness of the charge transfer MOS transistors M1 ′ to M4 ′ is uniformly 2
Since the thickness can be designed to withstand Vdd, the ON resistance can be designed to be lower and efficiency is higher than that in the case where Vgs of the charge transfer MOS transistor is nonuniform.

Although the three-stage charge pump circuit for performing negative boosting has been described above, the number of stages is not limited to three. That is, a charge pump circuit that performs negative boosting by an arbitrary number of stages can be realized by configuring the former two stages as P-channel type and the remaining latter stages as N-channel type as the charge transfer MOS transistors.

Next, a charge pump circuit according to the fourth embodiment of the present invention will be described. Figure 10 shows negative boosting 2
It is a schematic circuit diagram which shows a stage charge pump circuit. Differences from the second-stage charge pump circuit according to the second embodiment shown in FIG. 6 are the following two points. 1) The charge transfer MOS transistors M1, M2 and M3 are all N-channel type. 2) Vdd or GND is used as the ON voltage (gate voltage at the time of ON) of the charge transfer MOS transistor. That is, Vdd, Vdd, and GND are used as high-potential-side power supplies of the non-inverting level shift circuits S1, S2, and S3, respectively.
Is used.

Therefore, in this charge pump circuit, Vgs when the charge transfer MOS transistor is on is Vdd for M1, and 2Vdd for M2 and M3. As described above, in the charge pump circuit according to the present embodiment, unlike the second stage charge pump circuit according to the second embodiment, it is not possible to set all the charge transfer MOS transistors to the same Vgs value when they are on.

However, since the charge transfer MOS transistors are all formed in the same channel type, the manufacturing process (manufacturing process) is different from that of the second embodiment.
The advantage is that it can be simplified. Specifically, in the second embodiment, a triple well structure
However, according to the present embodiment, since a twin well structure is sufficient, the number of manufacturing steps can be reduced accordingly.

[0070]

According to the present invention, a high voltage equal to or higher than the threshold voltage can be applied as the gate-source voltage Vgs of the charge transfer MOS transistor, so that a highly efficient charge pump circuit without voltage loss can be provided. it can.

In addition, a high gate with an absolute value of 2 Vdd or more
The on-resistance of the charge transfer MOS transistors M1 to M4 is reduced by the source-to-source voltage Vgs, and a charge pump circuit with high efficiency and large output current can be realized.

Furthermore, since the gate-source voltage and the gate-substrate voltage of the charge transfer MOS transistor can be made constant to a constant voltage (for example, 2Vdd in absolute value), the gate oxide film thickness is uniformly in absolute value. The thickness may be designed to withstand 2Vdd. As a result, the charge transfer MOS
The ON resistance can be designed to be lower than in the case where the gate-source voltage Vgs of the transistor is nonuniform.

Further, according to the present invention, it is possible to provide a charge pump circuit for plus boosting and minus boosting, and since the number of charge pump stages can be set arbitrarily, it is possible to obtain a desired boosted voltage. Become.

[Brief description of drawings]

FIG. 1 is a schematic circuit diagram showing a charge pump circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration and an operation waveform of an inverting level shift circuit.

FIG. 3 is a diagram showing a configuration and an operation waveform of a non-inverting level shift circuit.

FIG. 4 is a timing chart for explaining the operation of the charge pump circuit according to the first embodiment of the present invention.

FIG. 5 is a diagram showing voltage waveforms at respective pumping nodes of the charge pump circuit according to the first embodiment of the present invention.

FIG. 6 is a schematic circuit diagram showing a charge pump circuit according to a second embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of the charge pump circuit according to the second embodiment of the present invention.

FIG. 8 is a diagram showing voltage waveforms at respective pumping nodes of the charge pump circuit according to the second embodiment of the present invention.

FIG. 9 is a schematic circuit diagram showing a charge pump circuit according to a third embodiment of the present invention.

FIG. 10 is a schematic circuit diagram showing a charge pump circuit according to a fourth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a charge pump circuit according to a conventional example.

FIG. 12 is a circuit diagram showing a charge pump circuit according to a conventional example.

FIG. 13 is a circuit diagram showing a charge pump circuit according to a conventional example.

[Explanation of symbols]

M1 to M4 charge transfer MOS transistors C1-C3 coupling capacitors Cout output capacitor L current load S1, S2 Inversion level shift circuit S3, S4 Non-inverting level shift circuit CLK, CLKB clock pulse

Claims (9)

(57) [Claims] 1. A predetermined input voltage to the charge transfer MOS transistor of the first stage is connected in series with applied (n
+2) charge transfer MOS transistors, a coupling capacitor having one end connected to each connection point of the charge transfer MOS transistors, and a clock driver for alternately supplying a clock pulse of opposite phase to the other end of the coupling capacitor And a charge pump circuit for outputting a positive boosted voltage from the charge transfer MOS transistor in the subsequent stage, the two charge transfer MOS transistors in the subsequent stage are configured by P channels, and the remaining n charge transfer MOS transistors are N
A charge pump circuit, which is of a channel type and is provided with circuit means for applying a gate voltage such that a gate-source voltage becomes a constant value when the charge transfer MOS transistor is turned on. 2. The charge pump circuit according to claim 1, wherein the circuit means controls an on / off state of the N-channel type charge transfer MOS transistor according to the clock pulse, and the clock. A P-channel charge transfer MOS according to a pulse
A non-inverted level shift circuit for controlling on / off of a transistor, using a boosted voltage at a connection point at a subsequent stage as a power source on the high potential side of the inverted level shift circuit, and a low potential of the non-inverted level shift circuit. A charge pump circuit characterized by using the voltage at the connection point of the preceding stage as the power supply on the side. 3. The charge pump circuit according to claim 2, wherein a voltage at a connection point after one stage is used as a power source on the high potential side of the inverting level shift circuit, and a low potential side of the non-inverting level shift circuit is used. The charge pump circuit is characterized in that the voltage at the connection point of one stage before is used as the power supply of. 4. The charge pump circuit according to claim 3, wherein the boosted voltage of the charge transfer MOS transistor at the intermediate stage is output and used as a power supply for another circuit. 5. The charge pump circuit according to claim 3, wherein the duty of the clock pulse supplied to the coupling capacitor is made different from that of the clock pulse supplied to the inverting level shift circuit and the non-inverting level shift circuit. A charge pump circuit, characterized in that a reverse current flow of the charge transfer MOS transistor is prevented. 6. A predetermined input voltage to the charge transfer MOS transistor of the first stage is connected in series with applied (n
+2) charge transfer MOS transistors, a coupling capacitor having one end connected to each connection point of the charge transfer MOS transistors, and a clock driver for alternately supplying a clock pulse of opposite phase to the other end of the coupling capacitor And a charge pump circuit for outputting a negative boosted voltage from the charge transfer MOS transistor in the subsequent stage, the two charge transfer MOS transistors in the rear stage are configured by N channels, and the remaining n charge transfer MOS transistors are formed. P
A charge pump circuit comprising a channel type circuit, and circuit means for applying a gate voltage such that a gate-source voltage becomes a constant value when the charge transfer MOS transistor is turned on. 7. The charge pump circuit according to claim 6, wherein the circuit means controls an on / off state of the P-channel type charge transfer MOS transistor in response to the clock pulse, and the clock. The N-channel type charge transfer MOS according to a pulse
A non-inverting level shift circuit for controlling ON / OFF of a transistor, and using a boosted voltage at a connection point at a subsequent stage as a power source on the low potential side of the inverting level shift circuit, and a high voltage level of the non-inverting level shift circuit. A charge pump circuit characterized by using the voltage at the connection point of the previous stage as a power source on the potential side. 8. The charge pump circuit according to claim 7, wherein the voltage at the connection point after one stage is used as a power source on the low potential side of the inverting level shift circuit, and the high potential side of the non-inverting level shift circuit is used. A charge pump circuit characterized by using a voltage at a connection point of one stage before as a power source of. 9. A plurality of charge transfer MOS transistor of the same channel type connected in series with the input voltage to the charge transfer MOS transistor of the first stage is applied, one end to the connection points of the charge transfer MOS transistor A connected coupling capacitor, a clock driver that alternately supplies opposite-phase clock pulses to the other end of the coupling capacitor, and a charge transfer MOS according to the clock pulse.
A charge pump circuit comprising a level shift circuit for supplying a voltage for turning on and off the charge transfer MOS transistor to a gate of the transistor.